From nobody Thu Oct 2 16:34:32 2025 Received: from mail-4317.protonmail.ch (mail-4317.protonmail.ch [185.70.43.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F9D913BC0C; Sun, 14 Sep 2025 19:34:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878475; cv=none; b=Ug+22tCCWJplqunEsR+8JMe+DFL+fvNROMQUMxwksrBjAJixN1i3Mgq9ZVJambWIfP653Dzc7zHnFIJhOI/t2MF17+zmzpfJ5zjLRR7P0XYmUE4pqRMAm2+5adq26+sx5gEUTddfSFy8LamQBKsKWg2kfeV7jIzB2/sjfI1dh68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878475; c=relaxed/simple; bh=XyJr1Et83VSZI4TiOdi7NfvvgURQCYI5SyEeqwKJn9c=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wofj8RLBVkKKCmvxfTi0nFHtW2H33gaTVGzm/H3Q1N79zWD8TE4CWZxmoHRTHzWDzbGN0XiYjlLU84WjIjtAYHsI2IesLN9yyyXOKY9muTVx8rsSvYGlGPeJvW8EkNAtMsNF1quOIUvkMd3m9Hh1yVudf3yrc7FxgmIWpVEdSdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=iYkeJ7ox; arc=none smtp.client-ip=185.70.43.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="iYkeJ7ox" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757878471; x=1758137671; bh=7lpOnihuzgN8aXgYGmo1vFZZPGJlskHF0+CRgoIdYsg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=iYkeJ7oxFPeF0Ogfj0g+m4tDHNF5R4qLTuXc13KtuJfY6tNvzutx6m/Kr+3ssKMlR YJ4PDNBJsWBved463O2SI2fTo3nlDQGJ0su5gpVUMUXTV5MGY2QUcL5yq7dNfXBXDO wcQ/jeoGACuYYU6wDoQWLmNTgAHPJ8I9dql4ewIh97NeeVQAa3a4agVtIFkrCBwh8u uSlQAvnIznj1zOKnqMJReXCpCgIYa/QOPCCMeGtFLeBn3JZaQE6AuV371Sw6KE8zBU EgBIiwbzY88hXMJLUsbq4JkUg2kxQ+UEMKJWI8i7SK2pMayRfmMmqn5ZQJ/dcDtFh6 jqWxcg2weinsw== Date: Sun, 14 Sep 2025 19:34:26 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Message-ID: <20250914-exynos9610-pinctrl-v1-1-90eda0c8fa03@chimac.ro> In-Reply-To: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> References: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: e3fd850e34ca0b8637da029291435a099c697aac Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document pin controller support on Exynos9610-series SoCs. Signed-off-by: Alexandru Chimac Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml= b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de846085614166087ef9046cf5d154fb9dad8309..2ebe9353d3bff9f708118a249b5= e969aa5fc393f 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -56,6 +56,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9610-pinctrl - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl --=20 2.47.3 From nobody Thu Oct 2 16:34:32 2025 Received: from mail-24422.protonmail.ch (mail-24422.protonmail.ch [109.224.244.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 707652DCF70; Sun, 14 Sep 2025 19:34:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878491; cv=none; b=gZygVUzS+ksrGphrn3zDESWBy9rcgCNqNdMdsL7+bkZp5lnxcSzZiWvnIW3nthLUAwOH7+7FtIAZvdwhfn7jPGmu4cmwavKVpQ82uGK6w3V+2nkhfBm6ELeDOOGHH533pApgJetKK3SeHzZrVifRXWL5bfUq5h28Zdsp2YlNbsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878491; c=relaxed/simple; bh=F//VEGGKQ4dySAaUx/MMsnPS7gqkPc0NM8iIn0Frh7c=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PrwCctEgcLBDxvB7AMX9/TuVptkhg9ksePN5hcWwUbv9Z5/51MbLRNBNmJMuHsi4mEC5xePy4TffW+NBlsMTC15KmD8fUY3F2Lgd949hl65yvqsOiDqEl6o4dsnN4M4uwpIIhqHwk3iiPbJ5p/P0tyHsYFxs3xvA9ZE1XFSJ/zE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=XZN50oF8; arc=none smtp.client-ip=109.224.244.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="XZN50oF8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757878481; x=1758137681; bh=E+xJKNk5JY17fob/Z1mGipjlu1Tw15TGNfmIUUFMZBc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=XZN50oF8Qh12FYWKXsXrL1uoywEBL24DVU8/X/BPINIvJe4Lk+x9aM2GrpD+Efqag A+jW9jPemMx3yzWUtaNdRWq6doD9DII1t6XUbwtK/8D4WBOXxb2m1mE7aj463b+0B2 SzI/TpkdegotG9aB/YS9PSFep1rZeIah+SapcJ38B0SthBRqudCvbJZ521dDlYKcTg 2s3rBoX9yUi7LS8TrftiN4SCDMclS1OWhjUw8tsCL0qAZu0FTU53RKvbhxws5Dowcr ghjiKWtbPocHyhtS9QxPWvcj6TaxQ7+fCtv4Mik4/Q2+qySm4BOORddn3HoIbu6Z8+ 2lQvt7aVeQ72g== Date: Sun, 14 Sep 2025 19:34:37 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Message-ID: <20250914-exynos9610-pinctrl-v1-2-90eda0c8fa03@chimac.ro> In-Reply-To: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> References: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 3c75b62b02e9849df976c000fd5158f746a985f1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a dedicated compatible for the exynos9610-wakeup-eint node, which is compatbile with Exynos850's implementation (and the Exynos7 fallback). Signed-off-by: Alexandru Chimac Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | = 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wake= up-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinct= rl-wakeup-interrupt.yaml index 0da6d69f599171b6946992c036f23c5dea17bd0d..fe06c0d2734960d3fe57783c1c5= 28f58fa297c57 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml @@ -49,6 +49,7 @@ properties: - enum: - google,gs101-wakeup-eint - samsung,exynos2200-wakeup-eint + - samsung,exynos9610-wakeup-eint - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint @@ -123,6 +124,7 @@ allOf: contains: enum: - samsung,exynos850-wakeup-eint + - samsung,exynos9610-wakeup-eint - samsung,exynosautov920-wakeup-eint then: properties: --=20 2.47.3 From nobody Thu Oct 2 16:34:32 2025 Received: from mail-24421.protonmail.ch (mail-24421.protonmail.ch [109.224.244.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF15A2DEA73; Sun, 14 Sep 2025 19:34:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878492; cv=none; b=OSysRkmtsPWTl3ijPKc1QNsvhriLRDbVls7f6vByZJsjN3Mzx2sH5vap0GNUz+z4HhLLuuFRk3KWiQQhpVdNylJdCMdLS+H531uM1UzAkMcYGnxG3rJY/DyP4vrhQZ0j7t6J++biBJ66/xodTaHRHanNlMBgXaIgJawEk8HJXhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757878492; c=relaxed/simple; bh=72kAhFJnVAeefwdU3Nw6qEjbXqrvFaUtrejk470Gw9U=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Tllj5RDZLSuXIWnjD3w9xjVnKzNQzT2b/+r2PW8AscmAew6Qg5S+OdaVkXej9rsD2pKskbpmPa40eEDJNZtqVDsUh1bScKvmAzjNP3Yn79IZVjpFWd7xxopyFKrp1QH76NNEFfQedYPjxWHmUToOMAxhu2bVJLFgDXsqeTqzXAM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=sK+4rO6o; arc=none smtp.client-ip=109.224.244.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="sK+4rO6o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757878488; x=1758137688; bh=J5NIBzHXHLTvGZLCPYIRsSe5gBL+3KSRcfZdaGnG5L8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=sK+4rO6oG/pTd2IwSniKK4XZZqj+SapzlITiiNOsxU74NPeXXkDpyEa6Z4WUmLwA4 btwHtRGJ3HqafxTEmL7BqF21eIxUVdjx8kiCB/i/OJxPwoKaPP3tlD2+Gt5TStrOdI I4eW0xn6+u0qfSDnXLOZcJJoPMarAuyUe78+fQzVra3gqLawI59mu4S/zlzR+FrbiV W6RdThh/JJn6m0ZUVBbemfEUM+Csub4DspeJnAtAnviz9f/FwRPCyZ9NzoNwJiZn2G /eFOwoIayoXqiXnZ7MUmZhSlTkfTNVVEYCn8HVllz+pLKft0OM6CB1YF8ngJYN5KrQ XjJRSQC40yjVw== Date: Sun, 14 Sep 2025 19:34:45 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Message-ID: <20250914-exynos9610-pinctrl-v1-3-90eda0c8fa03@chimac.ro> In-Reply-To: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> References: <20250914-exynos9610-pinctrl-v1-0-90eda0c8fa03@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 97105e46a9afaa2b00f7a321c6efb135deac6307 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinctrl configuration for Exynos9610. The bank types used are the same as on Exynos850, so we can reuse the macros. Signed-off-by: Alexandru Chimac --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 109 +++++++++++++++++++++= ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 112 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 5fe7c4b9f7bd424f396082f1b1b16bfb65f26cdf..a100962c51c28e2422c61a67d20= faf03486f4f70 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1604,6 +1604,115 @@ const struct samsung_pinctrl_of_match_data exynos88= 95_of_data __initconst =3D { .num_ctrl =3D ARRAY_SIZE(exynos8895_pin_ctrl), }; =20 +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos9610_pin_banks0[] =3D { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"), +}; + +/* pin banks of exynos9610 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks1[] =3D { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64), +}; + +/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ +static struct samsung_pin_bank_data exynos9610_pin_banks2[] =3D { + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04), + EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 3 (FSYS) */ +static struct samsung_pin_bank_data exynos9610_pin_banks3[] =3D { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08), +}; + +/* pin banks of exynos9610 pin-controller 4 (TOP) */ +static struct samsung_pin_bank_data exynos9610_pin_banks4[] =3D { + EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10), + EXYNOS850_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18), + EXYNOS850_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20), + EXYNOS850_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24), + EXYNOS850_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28), +}; + +/* pin banks of exynos9610 pin-controller 5 (SHUB) */ +static struct samsung_pin_bank_data exynos9610_pin_banks5[] =3D { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04), +}; + +static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst =3D= { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks =3D exynos9610_pin_banks0, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks0), + .eint_wkup_init =3D exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks =3D exynos9610_pin_banks1, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks1), + .eint_wkup_init =3D exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 DISPAUD data */ + .pin_banks =3D exynos9610_pin_banks2, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks2), + }, { + /* pin-controller instance 3 FSYS data */ + .pin_banks =3D exynos9610_pin_banks3, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks3), + }, { + /* pin-controller instance 4 TOP data */ + .pin_banks =3D exynos9610_pin_banks4, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks4), + }, { + /* pin-controller instance 5 SHUB data */ + .pin_banks =3D exynos9610_pin_banks5, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks5), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = =3D { + .ctrl =3D exynos9610_pin_ctrl, + .num_ctrl =3D ARRAY_SIZE(exynos9610_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 24745e1d78cec59c932ed57fdb8ca85410376ff7..2036212bf3d079cc61f1827847a= 37025c12e0961 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1498,6 +1498,8 @@ static const struct of_device_id samsung_pinctrl_dt_m= atch[] =3D { .data =3D &exynos850_of_data }, { .compatible =3D "samsung,exynos8895-pinctrl", .data =3D &exynos8895_of_data }, + { .compatible =3D "samsung,exynos9610-pinctrl", + .data =3D &exynos9610_of_data }, { .compatible =3D "samsung,exynos9810-pinctrl", .data =3D &exynos9810_of_data }, { .compatible =3D "samsung,exynos990-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 1cabcbe1401a614ea33803132db776e97c1d56ee..c711580a8729d05edf5057e0c0a= 7fed65d692c43 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -395,6 +395,7 @@ extern const struct samsung_pinctrl_of_match_data exyno= s7870_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; --=20 2.47.3