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Sun, 14 Sep 2025 15:39:07 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:49 +0200 Subject: [PATCH v2 6/6] arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-6-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4690; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=faHpJABUmh2pQbfVmmffgLLfTnAIPKwSQ01C5YgS5kg=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkqckss5fns2pYXRTq3oqdw9ziKPbM6Wn312aU9Zu4 3vdqLSgo5SFQYyLQVZMkSVJ+2UHw+oaxZjaB2Ewc1iZQIYwcHEKwETu1jMyrGT58Knnz6Z2uUj2 S2cSS/exrZz/JfmDwTfdziWPt0x1mcLIcFD+fP3uMh21B38Tvy7JPjNzh8wz8y+fI+YeLOy7U7z 8KRsA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 From: Hector Martin The M2 Ultra in the Mac Pro differs from the M2 Ultra Mac Studio in its PCIe setup. It uses all available 16 PCIe Gen4 on the first die and 8 PCIe Gen4 lanes on the second die to connect to ann 100 lane Microchip Switchtec PCIe switch. All internal PCIe devices and the PCIe slots are connected to the PCIe switch. Each die has implements a PCIe controller with a single 16 or 8 lane port. The PCIe controller is mostly compatible with existing implementation in pcie-apple.c. The resources for other 8 lanes on the second die are used to connect the NVMe flash with the controller in the SoC. This initial device tree does not include PCIe support. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t6022-j180d.dts | 121 ++++++++++++++++++++++++++= ++++ 2 files changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index 21c4e02a4429fa1db506dd85637a44000073590e..4eebcd85c90fcf0f358b0b32deb= f2475f6dbbf2c 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6022-j180d.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j414s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j414c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j416s.dtb diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dt= s/apple/t6022-j180d.dts new file mode 100644 index 0000000000000000000000000000000000000000..dca6bd167c225aa23e78e1c644b= f6c97f42d46b5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) + * + * target-type: J180d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible =3D "apple,j180d", "apple,t6022", "apple,arm-platform"; + model =3D "Apple Mac Pro (M2 Ultra, 2023)"; + aliases { + nvram =3D &nvram; + serial0 =3D &serial0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + power-domains =3D <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; + }; + }; + + memory@10000000000 { + device_type =3D "memory"; + reg =3D <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status =3D "okay"; +}; + +/* USB Type C Rear */ +&i2c0 { + hpm2: usb-pd@3b { + compatible =3D "apple,cd321x"; + reg =3D <0x3b>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm3: usb-pd@3c { + compatible =3D "apple,cd321x"; + reg =3D <0x3c>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ + + hpm6: usb-pd@3d { + compatible =3D "apple,cd321x"; + reg =3D <0x3d>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm7: usb-pd@3e { + compatible =3D "apple,cd321x"; + reg =3D <0x3e>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +/* USB Type C Front */ +&i2c3 { + status =3D "okay"; + + hpm0: usb-pd@38 { + compatible =3D "apple,cd321x"; + reg =3D <0x38>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm1: usb-pd@3f { + compatible =3D "apple,cd321x"; + reg =3D <0x3f>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +/* + * Delete unused PCIe nodes, the Mac Pro uses slightly different PCIe + * controllers with a single port connected to a PM40100 PCIe switch + */ +/delete-node/ &pcie0; +/delete-node/ &pcie0_dart_0; +/delete-node/ &pcie0_dart_1; +/delete-node/ &pcie0_dart_2; +/delete-node/ &pcie0_dart_3; + +&nco_clkref { + clock-frequency =3D <1068000000>; +}; + +#include "spi1-nvram.dtsi" --=20 2.51.0