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Sun, 14 Sep 2025 15:38:54 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:44 +0200 Subject: [PATCH v2 1/6] dt-bindings: arm: apple: Add t6020x compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-1-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3210; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=yAz8uxGOoeAELBwQQr/MUQrZttiky7faDv9NWAZtF4Y=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkifDd0zgzHb7tFto9gSmK2dr3Sb0KxtzX+Mt7JO2+ BLD1KXbUcrCIMbFICumyJKk/bKDYXWNYkztgzCYOaxMIEMYuDgFYCJPlzH8r1uTo7XifMDsf4dr V7co9vpdlNySt0E99/Vu78b/Hq+czjD8z7geuKJAgnO6wGaZ5FiVQ5ESp+0Xc9+Yr5n4S1YqNuE ANwA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 This adds the following apple,t6020/t6021/t6022 platforms: - apple,j414s - MacBook Pro (14-inch, M2 Pro, 2023) - apple,j414c - MacBook Pro (14-inch, M2 Nax, 2023) - apple,j416s - MacBook Pro (16-inch, M2 Pro, 2023) - apple,j416c - MacBook Pro (16-inch, M2 Max, 2023) - apple,j474s - Mac mini (M2 Pro, 2023) - apple,j475c - Mac Studio (M2 Max, 2023) - apple,j475d - Mac Studio (M2 Ultra, 2023) - apple,j475d - Mac Pro (M2 Ultra, 2023) Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple.yaml | 39 ++++++++++++++++++++= +++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentati= on/devicetree/bindings/arm/apple.yaml index 7073535b7c5b5ce885391699af56751241ddacb5..5c2629ec3d4cbcee49d3ff6a4db= 1cc8298e2a2e1 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,7 +96,7 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) =20 - And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: =20 - MacBook Pro (14-inch, M1 Pro, 2021) - MacBook Pro (14-inch, M1 Max, 2021) @@ -105,6 +105,17 @@ description: | - Mac Studio (M1 Max, 2022) - Mac Studio (M1 Ultra, 2022) =20 + Devices based on the "M2 Pro", "M2 Max" and "M2 Ultra" SoCs: + + - MacBook Pro (14-inch, M2 Pro, 2023) + - MacBook Pro (14-inch, M2 Max, 2023) + - MacBook Pro (16-inch, M2 Pro, 2023) + - MacBook Pro (16-inch, M2 Max, 2023) + - Mac mini (M2 Pro, 2023) + - Mac Studio (M2 Max, 2023) + - Mac Studio (M2 Ultra, 2023) + - Mac Pro (M2 Ultra, 2023) + The compatible property should follow this format: =20 compatible =3D "apple,", "apple,", "apple,arm-platfor= m"; @@ -310,6 +321,32 @@ properties: - const: apple,t6002 - const: apple,arm-platform =20 + - description: Apple M2 Pro SoC based platforms + items: + - enum: + - apple,j414s # MacBook Pro (14-inch, M2 Pro, 2023) + - apple,j416s # MacBook Pro (16-inch, M2 Pro, 2023) + - apple,j474s # Mac mini (M2 Pro, 2023) + - const: apple,t6020 + - const: apple,arm-platform + + - description: Apple M2 Max SoC based platforms + items: + - enum: + - apple,j414c # MacBook Pro (14-inch, M2 Max, 2023) + - apple,j416c # MacBook Pro (16-inch, M2 Max, 2023) + - apple,j475c # Mac Studio (M2 Max, 2023) + - const: apple,t6021 + - const: apple,arm-platform + + - description: Apple M2 Ultra SoC based platforms + items: + - enum: + - apple,j180d # Mac Pro (M2 Ultra, 2023) + - apple,j475d # Mac Studio (M2 Ultra, 2023) + - const: apple,t6022 + - const: apple,arm-platform + additionalProperties: true =20 ... --=20 2.51.0 From nobody Thu Oct 2 16:32:29 2025 Received: from fhigh-b5-smtp.messagingengine.com (fhigh-b5-smtp.messagingengine.com [202.12.124.156]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C0552E1EE4; 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Sun, 14 Sep 2025 15:38:57 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:45 +0200 Subject: [PATCH v2 2/6] arm64: dts: apple: Add ethernet0 alias for J375 template Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-2-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=762; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=W0OKDz1j+KjVHP3zG7O8HDQskqjMR1ZP/OoML7KXvAw=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkicjsxcYfzJhyixt5OcWjajdME1gxU2nUOkDmddNF KvPrMvsKGVhEONikBVTZEnSftnBsLpGMab2QRjMHFYmkCEMXJwCMBHzo4wMT0TLG0ru7ZZSapt6 7cuEx7NubjwaFfAo5+iOAo5n33Ob5jH8j/VSYHlx72vu47lh9QXLWeZ2KcQrW9/+qP3g4NtE3Vn O7AA= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 The alias is used by the boot loader to fill the MAC address. Fixes: aaa1d42a4ce3 ("arm64: dts: apple: Add J375 devicetrees") Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-j375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dt= s/apple/t600x-j375.dtsi index ed38acc0dfc36a1e30b1d44f1a8dcee089e87232..c0fb93ae72f4d4fcb254a36dc40= 8d55ab1bca0e9 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -12,6 +12,7 @@ / { aliases { bluetooth0 =3D &bluetooth0; + ethernet0 =3D ðernet0; serial0 =3D &serial0; wifi0 =3D &wifi0; }; --=20 2.51.0 From nobody Thu Oct 2 16:32:29 2025 Received: from fout-b4-smtp.messagingengine.com (fout-b4-smtp.messagingengine.com [202.12.124.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282212E2838; Sun, 14 Sep 2025 19:39:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 14 Sep 2025 15:38:59 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:46 +0200 Subject: [PATCH v2 3/6] arm64: dts: apple: Add initial t6020/t6021/t6022 DTs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-3-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=123509; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=7s3LDTDbvBtZ3eJqO6TM9KGKWpwZuL/YNqxjbL/TOfI=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkqfu/LzKWMBntkTEhK3yoGnSuZzC6ctKWC5NvRSxv Th02qSNHaUsDGJcDLJiiixJ2i87GFbXKMbUPgiDmcPKBDKEgYtTACayQpThn8o5o8cHL6yfOjOo MXW9lhJrsk2/l7eXX2WV3oIcJfmPDgx/+P6JumkUy7yfLXTwhvqr9xPWbdqSn/95nsjUx9Yywp9 0OQE= X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 From: Hector Martin These SoCs are found in Apple devices with M2 Pro (t6020), M2 Max (t6021) and M2 Ultra (t6022) and follow the pattern of their M1 counterparts. t6020 is a cut-down version of t6021, so the former just includes the latter and disables the missing bits (This is currently just one PMGR node and all of its domains. t6022 is two connected t6021 dies. The implementation seems to use t6021 with blocks disabled (mostly on the second die). MMIO addresses on the second die have a constant offset. The interrupt controller is multi-die aware. This setup can be represented in the device tree with two top level "soc" nodes. The MMIO offset is applied via "ranges" and devices are included with preproceesor macros to make the node labels unique and to specify the die number for the interrupt definition. Device nodes are distributed over dtsi files based on whether they are present on both dies or just on the first die. The only exception is the NVMe controller which resides on the second die. Its nodes are in a separate file. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- arch/arm64/boot/dts/apple/t6020.dtsi | 22 + arch/arm64/boot/dts/apple/t6021.dtsi | 69 + arch/arm64/boot/dts/apple/t6022.dtsi | 349 ++++ arch/arm64/boot/dts/apple/t602x-common.dtsi | 465 +++++ arch/arm64/boot/dts/apple/t602x-die0.dtsi | 575 ++++++ arch/arm64/boot/dts/apple/t602x-dieX.dtsi | 128 ++ arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi | 81 + arch/arm64/boot/dts/apple/t602x-nvme.dtsi | 42 + arch/arm64/boot/dts/apple/t602x-pmgr.dtsi | 2265 ++++++++++++++++++++= ++++ 9 files changed, 3996 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6020.dtsi b/arch/arm64/boot/dts/app= le/t6020.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..bffa66a3ffff3fea9e980f2a31f= 2bf87da9d7bfd --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6020 "M2 Pro" SoC + * + * Other names: H14J, "Rhodes Chop" + * + * Copyright The Asahi Linux Contributors + */ + +/* This chip is just a cut down version of t6021, so include it and disabl= e the missing parts */ + +#include "t6021.dtsi" + +/ { + compatible =3D "apple,t6020", "apple,arm-platform"; +}; + +/delete-node/ &pmgr_south; + +&gpu { + compatible =3D "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021.dtsi b/arch/arm64/boot/dts/app= le/t6021.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..62907ad6a546836676952edd324= 8f3388cb480e4 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6021 "M2 Max" SoC + * + * Other names: H14J, "Rhodes" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible =3D "apple,t6021", "apple,arm-platform"; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + ranges; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&{/soc} { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-gpio-pins.dtsi" +#include "t602x-pmgr.dtsi" + +#undef DIE +#undef DIE_NO + + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>; + }; + }; +}; + +&gpu { + compatible =3D "apple,agx-g14c", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022.dtsi b/arch/arm64/boot/dts/app= le/t6022.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e73bf2f7510ae2e840b3607d888= 09757ead51164 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022.dtsi @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6022 "M2 Ultra" SoC + * + * Other names: H14J, "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible =3D "apple,t6022", "apple,arm-platform"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + cpu-map { + cluster3 { + core0 { + cpu =3D <&cpu_e10>; + }; + core1 { + cpu =3D <&cpu_e11>; + }; + core2 { + cpu =3D <&cpu_e12>; + }; + core3 { + cpu =3D <&cpu_e13>; + }; + }; + + cluster4 { + core0 { + cpu =3D <&cpu_p20>; + }; + core1 { + cpu =3D <&cpu_p21>; + }; + core2 { + cpu =3D <&cpu_p22>; + }; + core3 { + cpu =3D <&cpu_p23>; + }; + }; + + cluster5 { + core0 { + cpu =3D <&cpu_p30>; + }; + core1 { + cpu =3D <&cpu_p31>; + }; + core2 { + cpu =3D <&cpu_p32>; + }; + core3 { + cpu =3D <&cpu_p33>; + }; + }; + }; + + cpu_e10: cpu@800 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x800>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_3>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e_die1>; + }; + + cpu_e11: cpu@801 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x801>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_3>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e_die1>; + }; + + cpu_e12: cpu@802 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x802>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_3>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e_die1>; + }; + + cpu_e13: cpu@803 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x803>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_3>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e_die1>; + }; + + cpu_p20: cpu@10900 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10900>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_4>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0_die1>; + }; + + cpu_p21: cpu@10901 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10901>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_4>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0_die1>; + }; + + cpu_p22: cpu@10902 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10902>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_4>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0_die1>; + }; + + cpu_p23: cpu@10903 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10903>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_4>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0_die1>; + }; + + cpu_p30: cpu@10a00 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10a00>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_5>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1_die1>; + }; + + cpu_p31: cpu@10a01 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10a01>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_5>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1_die1>; + }; + + cpu_p32: cpu@10a02 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10a02>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_5>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1_die1>; + }; + + cpu_p33: cpu@10a03 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10a03>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_5>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1_die1>; + }; + + l2_cache_3: l2-cache-3 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x1000000>; + }; + + l2_cache_5: l2-cache-5 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x1000000>; + }; + }; + + die0: soc@200000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, + <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, + <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges =3D <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; + + die1: soc@2200000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, + <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges =3D <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&die0 { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" +}; + +#include "t602x-pmgr.dtsi" +#include "t602x-gpio-pins.dtsi" + +#undef DIE +#undef DIE_NO + +#define DIE _die1 +#define DIE_NO 1 + +&die1 { + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-pmgr.dtsi" + +/delete-node/ &ps_pmp_die1; + +#undef DIE +#undef DIE_NO + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03 + &cpu_e10 &cpu_e11 &cpu_e12 &cpu_e13>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 + &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 + &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; + }; + }; +}; + +&ps_gfx { + // On t6022, the die0 GPU power domain needs both AFR power domains + power-domains =3D <&ps_afr>, <&ps_afr_die1>; +}; + +&gpu { + compatible =3D "apple,agx-g14d", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-common.dtsi b/arch/arm64/boot/= dts/apple/t602x-common.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9c800a391e7e87f86dce0f34c08= 276e69d2cb780 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-common.dtsi @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra) + * + * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + gpu =3D &gpu; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_e00>; + }; + core1 { + cpu =3D <&cpu_e01>; + }; + core2 { + cpu =3D <&cpu_e02>; + }; + core3 { + cpu =3D <&cpu_e03>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_p00>; + }; + core1 { + cpu =3D <&cpu_p01>; + }; + core2 { + cpu =3D <&cpu_p02>; + }; + core3 { + cpu =3D <&cpu_p03>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu_p10>; + }; + core1 { + cpu =3D <&cpu_p11>; + }; + core2 { + cpu =3D <&cpu_p12>; + }; + core3 { + cpu =3D <&cpu_p13>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x0>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + }; + + cpu_e01: cpu@1 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x1>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + }; + + cpu_e02: cpu@2 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x2>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + }; + + cpu_e03: cpu@3 { + compatible =3D "apple,blizzard"; + device_type =3D "cpu"; + reg =3D <0x0 0x3>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* to be filled by loader */ + next-level-cache =3D <&l2_cache_0>; + i-cache-size =3D <0x20000>; + d-cache-size =3D <0x10000>; + operating-points-v2 =3D <&blizzard_opp>; + capacity-dmips-mhz =3D <756>; + performance-domains =3D <&cpufreq_e>; + }; + + cpu_p00: cpu@10100 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10100>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0>; + }; + + cpu_p01: cpu@10101 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10101>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0>; + }; + + cpu_p02: cpu@10102 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10102>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0>; + }; + + cpu_p03: cpu@10103 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10103>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_1>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p0>; + }; + + cpu_p10: cpu@10200 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10200>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_2>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1>; + }; + + cpu_p11: cpu@10201 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10201>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_2>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1>; + }; + + cpu_p12: cpu@10202 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10202>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_2>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1>; + }; + + cpu_p13: cpu@10203 { + compatible =3D "apple,avalanche"; + device_type =3D "cpu"; + reg =3D <0x0 0x10203>; + enable-method =3D "spin-table"; + cpu-release-addr =3D <0 0>; /* To be filled by loader */ + next-level-cache =3D <&l2_cache_2>; + i-cache-size =3D <0x30000>; + d-cache-size =3D <0x20000>; + operating-points-v2 =3D <&avalanche_opp>; + capacity-dmips-mhz =3D <1024>; + performance-domains =3D <&cpufreq_p1>; + }; + + l2_cache_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x1000000>; + }; + + l2_cache_2: l2-cache-2 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + cache-size =3D <0x1000000>; + }; + }; + + blizzard_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + /* pstate #1 is a dummy clone of #2 */ + opp02 { + opp-hz =3D /bits/ 64 <912000000>; + opp-level =3D <2>; + clock-latency-ns =3D <7700>; + }; + opp03 { + opp-hz =3D /bits/ 64 <1284000000>; + opp-level =3D <3>; + clock-latency-ns =3D <25000>; + }; + opp04 { + opp-hz =3D /bits/ 64 <1752000000>; + opp-level =3D <4>; + clock-latency-ns =3D <33000>; + }; + opp05 { + opp-hz =3D /bits/ 64 <2004000000>; + opp-level =3D <5>; + clock-latency-ns =3D <38000>; + }; + opp06 { + opp-hz =3D /bits/ 64 <2256000000>; + opp-level =3D <6>; + clock-latency-ns =3D <44000>; + }; + opp07 { + opp-hz =3D /bits/ 64 <2424000000>; + opp-level =3D <7>; + clock-latency-ns =3D <48000>; + }; + }; + + avalanche_opp: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz =3D /bits/ 64 <702000000>; + opp-level =3D <1>; + clock-latency-ns =3D <7400>; + }; + opp02 { + opp-hz =3D /bits/ 64 <948000000>; + opp-level =3D <2>; + clock-latency-ns =3D <18000>; + }; + opp03 { + opp-hz =3D /bits/ 64 <1188000000>; + opp-level =3D <3>; + clock-latency-ns =3D <21000>; + }; + opp04 { + opp-hz =3D /bits/ 64 <1452000000>; + opp-level =3D <4>; + clock-latency-ns =3D <24000>; + }; + opp05 { + opp-hz =3D /bits/ 64 <1704000000>; + opp-level =3D <5>; + clock-latency-ns =3D <28000>; + }; + opp06 { + opp-hz =3D /bits/ 64 <1968000000>; + opp-level =3D <6>; + clock-latency-ns =3D <31000>; + }; + opp07 { + opp-hz =3D /bits/ 64 <2208000000>; + opp-level =3D <7>; + clock-latency-ns =3D <33000>; + }; + opp08 { + opp-hz =3D /bits/ 64 <2400000000>; + opp-level =3D <8>; + clock-latency-ns =3D <45000>; + }; + opp09 { + opp-hz =3D /bits/ 64 <2568000000>; + opp-level =3D <9>; + clock-latency-ns =3D <47000>; + }; + opp10 { + opp-hz =3D /bits/ 64 <2724000000>; + opp-level =3D <10>; + clock-latency-ns =3D <50000>; + }; + opp11 { + opp-hz =3D /bits/ 64 <2868000000>; + opp-level =3D <11>; + clock-latency-ns =3D <52000>; + }; + opp12 { + opp-hz =3D /bits/ 64 <3000000000>; + opp-level =3D <12>; + clock-latency-ns =3D <57000>; + }; + opp13 { + opp-hz =3D /bits/ 64 <3132000000>; + opp-level =3D <13>; + clock-latency-ns =3D <60000>; + }; + opp14 { + opp-hz =3D /bits/ 64 <3264000000>; + opp-level =3D <14>; + clock-latency-ns =3D <64000>; + }; + opp15 { + opp-hz =3D /bits/ 64 <3360000000>; + opp-level =3D <15>; + clock-latency-ns =3D <64000>; + turbo-mode; + }; + opp16 { + opp-hz =3D /bits/ 64 <3408000000>; + opp-level =3D <16>; + clock-latency-ns =3D <64000>; + turbo-mode; + }; + opp17 { + opp-hz =3D /bits/ 64 <3504000000>; + opp-level =3D <17>; + clock-latency-ns =3D <64000>; + turbo-mode; + }; + }; + + pmu-e { + compatible =3D "apple,blizzard-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,avalanche-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupt-parent =3D <&aic>; + interrupt-names =3D "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts =3D , + , + , + ; + }; + + clkref: clock-ref { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "clkref"; + }; + + clk_200m: clock-200m { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "clk_200m"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "nco_ref"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gpu_globals: globals { + status =3D "disabled"; + }; + + gpu_hw_cal_a: hw-cal-a { + status =3D "disabled"; + }; + + gpu_hw_cal_b: hw-cal-b { + status =3D "disabled"; + }; + + uat_handoff: uat-handoff { + status =3D "disabled"; + }; + + uat_pagetables: uat-pagetables { + status =3D "disabled"; + }; + + uat_ttbs: uat-ttbs { + status =3D "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dt= s/apple/t602x-die0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..2e7d2bf08ddc829e87d37761635= 03b0eaae843a7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on die 0 on the Apple T6022 "M2 Ultra" SoC and present on + * Apple T6020 / T6021 "M2 Pro" / "M2 Max". + * + * Copyright The Asahi Linux Contributors + */ + + nco: clock-controller@28e03c000 { + compatible =3D "apple,t6020-nco", "apple,t8103-nco"; + reg =3D <0x2 0x8e03c000 0x0 0x14000>; + clocks =3D <&nco_clkref>; + #clock-cells =3D <1>; + }; + + aic: interrupt-controller@28e100000 { + compatible =3D "apple,t6020-aic", "apple,aic2"; + #interrupt-cells =3D <4>; + interrupt-controller; + reg =3D <0x2 0x8e100000 0x0 0xc000>, + <0x2 0x8e10c000 0x0 0x1000>; + reg-names =3D "core", "event"; + power-domains =3D <&ps_aic>; + }; + + nub_spmi0: spmi@29e114000 { + compatible =3D "apple,t6020-spmi", "apple,t8103-spmi"; + reg =3D <0x2 0x9e114000 0x0 0x100>; + #address-cells =3D <2>; + #size-cells =3D <0>; + + pmic1: pmic@f { + compatible =3D "apple,maverick-pmic", "apple,spmi-nvmem"; + reg =3D <0xb SPMI_USID>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + pm_setting: pm-setting@1405 { + reg =3D <0x1405 0x1>; + }; + + rtc_offset: rtc-offset@1411 { + reg =3D <0x1411 0x6>; + }; + + boot_stage: boot-stage@6001 { + reg =3D <0x6001 0x1>; + }; + + boot_error_count: boot-error-count@6002,0 { + reg =3D <0x6002 0x1>; + bits =3D <0 4>; + }; + + panic_count: panic-count@6002,4 { + reg =3D <0x6002 0x1>; + bits =3D <4 4>; + }; + + boot_error_stage: boot-error-stage@6003 { + reg =3D <0x6003 0x1>; + }; + + shutdown_flag: shutdown-flag@600f,3 { + reg =3D <0x600f 0x1>; + bits =3D <3 1>; + }; + + fault_shadow: fault-shadow@867b { + reg =3D <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg =3D <0x8b00 0x400>; + }; + }; + }; + }; + + wdt: watchdog@29e2c4000 { + compatible =3D "apple,t6020-wdt", "apple,t8103-wdt"; + reg =3D <0x2 0x9e2c4000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + smc_mbox: mbox@2a2408000 { + compatible =3D "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg =3D <0x2 0xa2408000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + interrupt-names =3D "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells =3D <0>; + }; + + smc: smc@2a2400000 { + compatible =3D "apple,t6020-smc", "apple,t8103-smc"; + reg =3D <0x2 0xa2400000 0x0 0x4000>, + <0x2 0xa3e00000 0x0 0x100000>; + reg-names =3D "smc", "sram"; + mboxes =3D <&smc_mbox>; + + smc_gpio: gpio { + compatible =3D "apple,smc-gpio"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + smc_reboot: reboot { + compatible =3D "apple,smc-reboot"; + nvmem-cells =3D <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names =3D "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + pinctrl_smc: pinctrl@2a2820000 { + compatible =3D "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg =3D <0x2 0xa2820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl_smc 0 0 30>; + apple,npins =3D <30>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + sio_dart: iommu@39b008000 { + compatible =3D "apple,t6020-dart", "apple,t8110-dart"; + reg =3D <0x3 0x9b008000 0x0 0x8000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_sio_cpu>; + }; + + fpwm0: pwm@39b030000 { + compatible =3D "apple,t6020-fpwm", "apple,s5l-fpwm"; + reg =3D <0x3 0x9b030000 0x0 0x4000>; + power-domains =3D <&ps_fpwm0>; + clocks =3D <&clkref>; + #pwm-cells =3D <2>; + status =3D "disabled"; + }; + + i2c0: i2c@39b040000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b040000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c0>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + }; + + i2c1: i2c@39b044000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b044000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c1>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c2: i2c@39b048000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b048000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c2_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c2>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c3: i2c@39b04c000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b04c000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c3_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c3>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c4: i2c@39b050000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b050000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c4_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c4>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c5: i2c@39b054000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b054000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c5_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c5>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c6: i2c@39b054000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b054000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c6_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c6>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c7: i2c@39b054000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b054000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c7_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c7>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + i2c8: i2c@39b054000 { + compatible =3D "apple,t6020-i2c", "apple,t8103-i2c"; + reg =3D <0x3 0x9b054000 0x0 0x4000>; + clocks =3D <&clkref>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + pinctrl-0 =3D <&i2c8_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_i2c8>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + status =3D "disabled"; + }; + + spi1: spi@39b104000 { + compatible =3D "apple,t6020-spi", "apple,t8103-spi"; + reg =3D <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clk_200m>; + pinctrl-0 =3D <&spi1_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi1>; + status =3D "disabled"; + }; + + spi2: spi@39b108000 { + compatible =3D "apple,t6020-spi", "apple,t8103-spi"; + reg =3D <0x3 0x9b108000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi2_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi2>; + status =3D "disabled"; + }; + + spi4: spi@39b110000 { + compatible =3D "apple,t6020-spi", "apple,t8103-spi"; + reg =3D <0x3 0x9b110000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&clkref>; + pinctrl-0 =3D <&spi4_pins>; + pinctrl-names =3D "default"; + power-domains =3D <&ps_spi4>; + status =3D "disabled"; + }; + + serial0: serial@39b200000 { + compatible =3D "apple,s5l-uart"; + reg =3D <0x3 0x9b200000 0x0 0x4000>; + reg-io-width =3D <4>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks =3D <&clkref>, <&clkref>; + clock-names =3D "uart", "clk_uart_baud0"; + power-domains =3D <&ps_uart0>; + status =3D "disabled"; + }; + + admac: dma-controller@39b400000 { + compatible =3D "apple,t6020-admac", "apple,t8103-admac"; + reg =3D <0x3 0x9b400000 0x0 0x34000>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + interrupts-extended =3D <0>, + <&aic AIC_IRQ 0 1218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + iommus =3D <&sio_dart 2>; + power-domains =3D <&ps_sio_adma>; + resets =3D <&ps_audio_p>; + }; + + mca: mca@39b600000 { + compatible =3D "apple,t6020-mca", "apple,t8103-mca"; + reg =3D <0x3 0x9b600000 0x0 0x10000>, + <0x3 0x9b500000 0x0 0x20000>; + clocks =3D <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; + dmas =3D <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; + dma-names =3D "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + power-domains =3D <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>; + resets =3D <&ps_audio_p>; + #sound-dai-cells =3D <1>; + }; + + gpu: gpu@406400000 { + compatible =3D "apple,agx-g14s"; + reg =3D <0x4 0x6400000 0 0x40000>, + <0x4 0x4000000 0 0x1000000>; + reg-names =3D "asc", "sgx"; + mboxes =3D <&agx_mbox>; + power-domains =3D <&ps_gfx>; + memory-region =3D <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>, + <&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>; + memory-region-names =3D "ttbs", "pagetables", "handoff", + "hw-cal-a", "hw-cal-b", "globals"; + + apple,firmware-abi =3D <0 0 0>; + }; + + agx_mbox: mbox@406408000 { + compatible =3D "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg =3D <0x4 0x6408000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + interrupt-names =3D "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells =3D <0>; + }; + + pcie0: pcie@580000000 { + compatible =3D "apple,t6020-pcie"; + device_type =3D "pci"; + + reg =3D <0x5 0x80000000 0x0 0x1000000>, /* config */ + <0x5 0x91000000 0x0 0x4000>, /* rc */ + <0x5 0x94008000 0x0 0x4000>, /* port0 */ + <0x5 0x95008000 0x0 0x4000>, /* port1 */ + <0x5 0x96008000 0x0 0x4000>, /* port2 */ + <0x5 0x97008000 0x0 0x4000>, /* port3 */ + <0x5 0x9e00c000 0x0 0x4000>, /* phy0 */ + <0x5 0x9e010000 0x0 0x4000>, /* phy1 */ + <0x5 0x9e014000 0x0 0x4000>, /* phy2 */ + <0x5 0x9e018000 0x0 0x4000>; /* phy3 */ + reg-names =3D "config", "rc", + "port0", "port1", "port2", "port3", + "phy0", "phy1", "phy2", "phy3"; + + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + + msi-controller; + msi-parent =3D <&pcie0>; + msi-ranges =3D <&aic AIC_IRQ 0 1672 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map =3D <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>, + <0x400 &pcie0_dart_3 1 1>; + iommu-map-mask =3D <0xff00>; + + bus-range =3D <0 4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + + power-domains =3D <&ps_apcie_gp_sys>; + pinctrl-0 =3D <&pcie_pins>; + pinctrl-names =3D "default"; + + port00: pci@0,0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type =3D "pci"; + reg =3D <0x800 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + status =3D "disabled"; + }; + + port02: pci@2,0 { + device_type =3D "pci"; + reg =3D <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + status =3D "disabled"; + }; + + port03: pci@3,0 { + device_type =3D "pci"; + reg =3D <0x1800 0x0 0x0 0x0 0x0>; + reset-gpios =3D <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + + interrupt-controller; + #interrupt-cells =3D <1>; + + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + status =3D "disabled"; + }; + }; + + pcie0_dart_0: iommu@594000000 { + compatible =3D "apple,t6020-dart", "apple,t8110-dart"; + reg =3D <0x5 0x94000000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp_sys>; + }; + + pcie0_dart_1: iommu@595000000 { + compatible =3D "apple,t6020-dart", "apple,t8110-dart"; + reg =3D <0x5 0x95000000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp_sys>; + status =3D "disabled"; + }; + + pcie0_dart_2: iommu@596000000 { + compatible =3D "apple,t6020-dart", "apple,t8110-dart"; + reg =3D <0x5 0x96000000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp_sys>; + status =3D "disabled"; + }; + + pcie0_dart_3: iommu@597000000 { + compatible =3D "apple,t6020-dart", "apple,t8110-dart"; + reg =3D <0x5 0x97000000 0x0 0x4000>; + #iommu-cells =3D <1>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + power-domains =3D <&ps_apcie_gp_sys>; + status =3D "disabled"; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dt= s/apple/t602x-dieX.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cb07fd82b32e67a41d8290bf834= 7d4eca474af23 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes present on both dies of T6022 (M2 Ultra) and present on M2 Pro/Ma= x. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(cpufreq_e): cpufreq@210e20000 { + compatible =3D "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufr= eq"; + reg =3D <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells =3D <0>; + }; + + DIE_NODE(cpufreq_p0): cpufreq@211e20000 { + compatible =3D "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufr= eq"; + reg =3D <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells =3D <0>; + }; + + DIE_NODE(cpufreq_p1): cpufreq@212e20000 { + compatible =3D "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufr= eq"; + reg =3D <0x2 0x12e20000 0 0x1000>; + #performance-domain-cells =3D <0>; + }; + + DIE_NODE(pmgr): power-management@28e080000 { + compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x8e080000 0 0x8000>; + }; + + DIE_NODE(pmgr_south): power-management@28e680000 { + compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x8e680000 0 0x8000>; + }; + + DIE_NODE(pmgr_east): power-management@290280000 { + compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x90280000 0 0xc000>; + }; + + DIE_NODE(pinctrl_nub): pinctrl@29e1f0000 { + compatible =3D "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg =3D <0x2 0x9e1f0000 0x0 0x4000>; + power-domains =3D <&DIE_NODE(ps_nub_gpio)>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&DIE_NODE(pinctrl_nub) 0 0 30>; + apple,npins =3D <30>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + DIE_NODE(pmgr_mini): power-management@29e280000 { + compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + reg =3D <0x2 0x9e280000 0 0x4000>; + }; + + DIE_NODE(pinctrl_aop): pinctrl@2a6820000 { + compatible =3D "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg =3D <0x2 0xa6820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&DIE_NODE(pinctrl_aop) 0 0 72>; + apple,npins =3D <72>; + + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + }; + + DIE_NODE(pinctrl_ap): pinctrl@39b028000 { + compatible =3D "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg =3D <0x3 0x9b028000 0x0 0x4000>; + + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + , + , + , + ; + + clocks =3D <&clkref>; + power-domains =3D <&DIE_NODE(ps_gpio)>; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&DIE_NODE(pinctrl_ap) 0 0 255>; + apple,npins =3D <255>; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + DIE_NODE(pmgr_gfx): power-management@404e80000 { + compatible =3D "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple= -mfd"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reg =3D <0x4 0x4e80000 0 0x4000>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi b/arch/arm64/bo= ot/dts/apple/t602x-gpio-pins.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e41b6475f7921840cd90b0203c6= 822808f13c5e3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * GPIO pin mappings for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + +&pinctrl_ap { + i2c0_pins: i2c0-pins { + pinmux =3D , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux =3D , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux =3D , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux =3D , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux =3D , + ; + }; + + i2c5_pins: i2c5-pins { + pinmux =3D , + ; + }; + + i2c6_pins: i2c6-pins { + pinmux =3D , + ; + }; + + i2c7_pins: i2c7-pins { + pinmux =3D , + ; + }; + + i2c8_pins: i2c8-pins { + pinmux =3D , + ; + }; + + spi1_pins: spi1-pins { + pinmux =3D , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + spi2_pins: spi2-pins { + pinmux =3D , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + spi4_pins: spi4-pins { + pinmux =3D , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + pcie_pins: pcie-pins { + pinmux =3D , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-nvme.dtsi b/arch/arm64/boot/dt= s/apple/t602x-nvme.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..590cec8ac804c0b5b35a53ad206= 66aee9bdb4da7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * NVMe related devices for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(ans_mbox): mbox@347408000 { + compatible =3D "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg =3D <0x3 0x47408000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + , + ; + interrupt-names =3D "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + power-domains =3D <&DIE_NODE(ps_ans2)>; + #mbox-cells =3D <0>; + }; + + DIE_NODE(sart): sart@34bc50000 { + compatible =3D "apple,t6020-sart", "apple,t6000-sart"; + reg =3D <0x3 0x4bc50000 0x0 0x10000>; + power-domains =3D <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(nvme): nvme@34bcc0000 { + compatible =3D "apple,t6020-nvme-ans2", "apple,t8103-nvme-ans2"; + reg =3D <0x3 0x4bcc0000 0x0 0x40000>, <0x3 0x47400000 0x0 0x4000>; + reg-names =3D "nvme", "ans"; + interrupt-parent =3D <&aic>; + /* The NVME interrupt is always routed to die 0 */ + interrupts =3D ; + mboxes =3D <&DIE_NODE(ans_mbox)>; + apple,sart =3D <&DIE_NODE(sart)>; + power-domains =3D <&DIE_NODE(ps_ans2)>, + <&DIE_NODE(ps_apcie_st_sys)>, + <&DIE_NODE(ps_apcie_st1_sys)>; + power-domain-names =3D "ans", "apcie0", "apcie1"; + resets =3D <&DIE_NODE(ps_ans2)>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi b/arch/arm64/boot/dt= s/apple/t602x-pmgr.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..f5382a2faf0b2530439ddf29e19= 12dd61b158028 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi @@ -0,0 +1,2265 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for Apple T602x "M2 Pro/Max/Ultra" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&DIE_NODE(pmgr) { + DIE_NODE(ps_afi): power-controller@100 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afi); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_aic): power-controller@108 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(aic); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_dwi): power-controller@110 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dwi); + }; + + DIE_NODE(ps_pms): power-controller@118 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pms); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_gpio): power-controller@120 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(gpio); + power-domains =3D <&DIE_NODE(ps_sio)>, <&DIE_NODE(ps_pms)>; + }; + + DIE_NODE(ps_soc_dpe): power-controller@128 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(soc_dpe); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pms_c1ppt): power-controller@130 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pms_c1ppt); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pmgr_soc_ocla): power-controller@138 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pmgr_soc_ocla); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_amcc0): power-controller@168 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc0); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc2): power-controller@170 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc2); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_00): power-controller@178 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_00); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_01): power-controller@180 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_01); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_02): power-controller@188 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_02); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_03): power-controller@190 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_03); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_08): power-controller@198 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_08); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_09): power-controller@1a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_09); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_10): power-controller@1a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_10); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_11): power-controller@1b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_11); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc1_ioa): power-controller@1b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc1_ioa); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afc): power-controller@1d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afc); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_afnc0_ioa): power-controller@1e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc0_ioa); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc1_ls): power-controller@1f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc1_ls); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc1_ioa)>; + }; + + DIE_NODE(ps_afnc0_ls): power-controller@1f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc0_ls); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc0_ioa)>; + }; + + DIE_NODE(ps_afnc1_lw0): power-controller@200 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc1_lw0); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw1): power-controller@208 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc1_lw1); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw2): power-controller@210 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc1_lw2); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc0_lw0): power-controller@218 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc0_lw0); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc0_ls)>; + }; + + DIE_NODE(ps_scodec): power-controller@220 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(scodec); + power-domains =3D <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_atc0_common): power-controller@228 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_common); + power-domains =3D <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc1_common): power-controller@230 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_common); + power-domains =3D <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc2_common): power-controller@238 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_common); + power-domains =3D <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc3_common): power-controller@240 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_common); + power-domains =3D <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_dispext1_sys): power-controller@248 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext1_sys); + power-domains =3D <&DIE_NODE(ps_afnc1_lw2)>; + }; + + DIE_NODE(ps_pms_bridge): power-controller@250 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pms_bridge); + apple,always-on; /* Core device */ + power-domains =3D <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_dispext0_sys): power-controller@258 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext0_sys); + power-domains =3D <&DIE_NODE(ps_afnc0_lw0)>, <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_ane_sys): power-controller@260 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_sys); + power-domains =3D <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_avd_sys): power-controller@268 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(avd_sys); + power-domains =3D <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_atc0_cio): power-controller@270 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_cio); + power-domains =3D <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc0_pcie): power-controller@278 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_pcie); + power-domains =3D <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_cio): power-controller@280 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_cio); + power-domains =3D <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc1_pcie): power-controller@288 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_pcie); + power-domains =3D <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_cio): power-controller@290 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x290 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_cio); + power-domains =3D <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc2_pcie): power-controller@298 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x298 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_pcie); + power-domains =3D <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_cio): power-controller@2a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_cio); + power-domains =3D <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_atc3_pcie): power-controller@2a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_pcie); + power-domains =3D <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_dispext1_fe): power-controller@2b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext1_fe); + power-domains =3D <&DIE_NODE(ps_dispext1_sys)>; + }; + + DIE_NODE(ps_dispext1_cpu0): power-controller@2b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext1_cpu0); + power-domains =3D <&DIE_NODE(ps_dispext1_fe)>; + apple,min-state =3D <4>; + }; + + DIE_NODE(ps_dispext0_fe): power-controller@2c0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext0_fe); + power-domains =3D <&DIE_NODE(ps_dispext0_sys)>; + }; + + DIE_NODE(ps_pmp): power-controller@2c8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pmp); + }; + + DIE_NODE(ps_pms_sram): power-controller@2d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(pms_sram); + }; + + DIE_NODE(ps_dispext0_cpu0): power-controller@2d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext0_cpu0); + power-domains =3D <&DIE_NODE(ps_dispext0_fe)>; + apple,min-state =3D <4>; + }; + + DIE_NODE(ps_ane_cpu): power-controller@2e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_cpu); + power-domains =3D <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_atc0_cio_pcie): power-controller@2e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_cio_pcie); + power-domains =3D <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc0_cio_usb): power-controller@2f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_cio_usb); + power-domains =3D <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc1_cio_pcie): power-controller@2f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_cio_pcie); + power-domains =3D <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc1_cio_usb): power-controller@300 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_cio_usb); + power-domains =3D <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc2_cio_pcie): power-controller@308 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_cio_pcie); + power-domains =3D <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc2_cio_usb): power-controller@310 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_cio_usb); + power-domains =3D <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc3_cio_pcie): power-controller@318 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_cio_pcie); + power-domains =3D <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_atc3_cio_usb): power-controller@320 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_cio_usb); + power-domains =3D <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_trace_fab): power-controller@390 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x390 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(trace_fab); + }; + + DIE_NODE(ps_ane_sys_mpm): power-controller@4000 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_sys_mpm); + power-domains =3D <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_td): power-controller@4008 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_td); + power-domains =3D <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_base): power-controller@4010 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_base); + power-domains =3D <&DIE_NODE(ps_ane_td)>; + }; + + DIE_NODE(ps_ane_set1): power-controller@4018 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_set1); + power-domains =3D <&DIE_NODE(ps_ane_base)>; + }; + + DIE_NODE(ps_ane_set2): power-controller@4020 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_set2); + power-domains =3D <&DIE_NODE(ps_ane_set1)>; + }; + + DIE_NODE(ps_ane_set3): power-controller@4028 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_set3); + power-domains =3D <&DIE_NODE(ps_ane_set2)>; + }; + + DIE_NODE(ps_ane_set4): power-controller@4030 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ane_set4); + power-domains =3D <&DIE_NODE(ps_ane_set3)>; + }; +}; + +&DIE_NODE(pmgr_south) { + DIE_NODE(ps_amcc4): power-controller@100 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc4); + apple,always-on; + }; + + DIE_NODE(ps_amcc5): power-controller@108 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc5); + apple,always-on; + }; + + DIE_NODE(ps_amcc6): power-controller@110 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc6); + apple,always-on; + }; + + DIE_NODE(ps_amcc7): power-controller@118 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc7); + apple,always-on; + }; + + DIE_NODE(ps_dcs_16): power-controller@120 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_16); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_17): power-controller@128 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_17); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_18): power-controller@130 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_18); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_19): power-controller@138 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_19); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_20): power-controller@140 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_20); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_21): power-controller@148 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_21); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_22): power-controller@150 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_22); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_23): power-controller@158 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_23); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_24): power-controller@160 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_24); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_25): power-controller@168 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_25); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_26): power-controller@170 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_26); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_27): power-controller@178 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_27); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_28): power-controller@180 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_28); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_29): power-controller@188 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_29); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_30): power-controller@190 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_30); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_31): power-controller@198 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_31); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc4_ioa): power-controller@1a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc4_ioa); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc4_ls): power-controller@1a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc4_ls); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc4_ioa)>; + }; + + DIE_NODE(ps_afnc4_lw0): power-controller@1b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc4_lw0); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc4_ls)>; + }; + + DIE_NODE(ps_afnc5_ioa): power-controller@1b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc5_ioa); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc5_ls): power-controller@1c0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc5_ls); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc5_ioa)>; + }; + + DIE_NODE(ps_afnc5_lw0): power-controller@1c8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc5_lw0); + apple,always-on; /* Apple Fabric */ + power-domains =3D <&DIE_NODE(ps_afnc5_ls)>; + }; + + DIE_NODE(ps_dispext2_sys): power-controller@1d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext2_sys); + }; + + DIE_NODE(ps_msr1): power-controller@1d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(msr1); + }; + + DIE_NODE(ps_dispext2_fe): power-controller@1e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext2_fe); + power-domains =3D <&DIE_NODE(ps_dispext2_sys)>; + }; + + DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext2_cpu0); + power-domains =3D <&DIE_NODE(ps_dispext2_fe)>; + apple,min-state =3D <4>; + }; + + DIE_NODE(ps_msr1_ase_core): power-controller@1f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(msr1_ase_core); + power-domains =3D <&DIE_NODE(ps_msr1)>; + }; + + DIE_NODE(ps_dispext3_sys): power-controller@220 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext3_sys); + }; + + DIE_NODE(ps_venc1_sys): power-controller@228 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_sys); + }; + + DIE_NODE(ps_dispext3_fe): power-controller@230 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext3_fe); + power-domains =3D <&DIE_NODE(ps_dispext3_sys)>; + }; + + DIE_NODE(ps_dispext3_cpu0): power-controller@238 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dispext3_cpu0); + power-domains =3D <&DIE_NODE(ps_dispext3_fe)>; + apple,min-state =3D <4>; + }; + + DIE_NODE(ps_venc1_dma): power-controller@4000 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_dma); + power-domains =3D <&DIE_NODE(ps_venc1_sys)>; + }; + + DIE_NODE(ps_venc1_pipe4): power-controller@4008 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_pipe4); + power-domains =3D <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_pipe5): power-controller@4010 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_pipe5); + power-domains =3D <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me0): power-controller@4018 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_me0); + power-domains =3D <&DIE_NODE(ps_venc1_pipe5)>, <&DIE_NODE(ps_venc1_pipe4= )>; + }; + + DIE_NODE(ps_venc1_me1): power-controller@4020 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc1_me1); + power-domains =3D <&DIE_NODE(ps_venc1_me0)>; + }; +}; + +&DIE_NODE(pmgr_east) { + DIE_NODE(ps_clvr_spmi0): power-controller@100 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(clvr_spmi0); + apple,always-on; /* PCPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi1): power-controller@108 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(clvr_spmi1); + apple,always-on; /* GPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi2): power-controller@110 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(clvr_spmi2); + apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used b= y SMC) */ + }; + + DIE_NODE(ps_clvr_spmi3): power-controller@118 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(clvr_spmi3); + apple,always-on; /* Additional voltage regulator, probably used on T6021= (SMC) */ + }; + + DIE_NODE(ps_clvr_spmi4): power-controller@120 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(clvr_spmi4); + apple,always-on; /* Additional voltage regulator, probably used on T6021= (SMC) */ + }; + + DIE_NODE(ps_ispsens0): power-controller@128 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ispsens0); + }; + + DIE_NODE(ps_ispsens1): power-controller@130 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ispsens1); + }; + + DIE_NODE(ps_ispsens2): power-controller@138 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x138 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ispsens2); + }; + + DIE_NODE(ps_ispsens3): power-controller@140 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x140 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ispsens3); + }; + + DIE_NODE(ps_afnc6_ioa): power-controller@148 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x148 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc6_ioa); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc6_ls): power-controller@150 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x150 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc6_ls); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc6_ioa)>; + }; + + DIE_NODE(ps_afnc6_lw0): power-controller@158 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x158 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc6_lw0); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc6_ls)>; + }; + + DIE_NODE(ps_afnc2_ioa): power-controller@160 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x160 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc2_ioa); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_dcs_10)>; + }; + + DIE_NODE(ps_afnc2_ls): power-controller@168 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x168 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc2_ls); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc2_ioa)>; + }; + + DIE_NODE(ps_afnc2_lw0): power-controller@170 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x170 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc2_lw0); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc2_lw1): power-controller@178 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x178 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc2_lw1); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc3_ioa): power-controller@180 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x180 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc3_ioa); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc3_ls): power-controller@188 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x188 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc3_ls); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc3_ioa)>; + }; + + DIE_NODE(ps_afnc3_lw0): power-controller@190 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x190 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(afnc3_lw0); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_apcie_gp): power-controller@198 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x198 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_gp); + power-domains =3D <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_apcie_st): power-controller@1a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_st); + power-domains =3D <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_ans2): power-controller@1a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(ans2); + power-domains =3D <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_disp0_sys): power-controller@1b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(disp0_sys); + power-domains =3D <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_jpg): power-controller@1b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(jpg); + power-domains =3D <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_sio): power-controller@1c0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio); + power-domains =3D <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_isp_sys): power-controller@1c8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_sys); + power-domains =3D <&DIE_NODE(ps_afnc2_lw1)>; + status =3D "disabled"; + }; + + DIE_NODE(ps_disp0_fe): power-controller@1d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(disp0_fe); + power-domains =3D <&DIE_NODE(ps_disp0_sys)>; + }; + + DIE_NODE(ps_disp0_cpu0): power-controller@1d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(disp0_cpu0); + power-domains =3D <&DIE_NODE(ps_disp0_fe)>; + apple,min-state =3D <4>; + }; + + DIE_NODE(ps_sio_cpu): power-controller@1e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio_cpu); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm0): power-controller@1e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(fpwm0); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm1): power-controller@1f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(fpwm1); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm2): power-controller@1f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x1f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(fpwm2); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c0): power-controller@200 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x200 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c0); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c1): power-controller@208 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x208 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c1); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c2): power-controller@210 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x210 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c2); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c3): power-controller@218 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x218 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c3); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c4): power-controller@220 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x220 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c4); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c5): power-controller@228 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x228 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c5); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c6): power-controller@230 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x230 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c6); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c7): power-controller@238 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x238 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c7); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c8): power-controller@240 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x240 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(i2c8); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi_p): power-controller@248 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x248 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi_p); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi0): power-controller@250 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x250 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio_spmi0); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi1): power-controller@258 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x258 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio_spmi1); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi2): power-controller@260 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x260 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio_spmi2); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_p): power-controller@268 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x268 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart_p); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_audio_p): power-controller@270 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x270 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(audio_p); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_adma): power-controller@278 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x278 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sio_adma); + power-domains =3D <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_aes): power-controller@280 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x280 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(aes); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_dptx_phy_ps): power-controller@288 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x288 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dptx_phy_ps); + power-domains =3D <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi0): power-controller@2d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi0); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi1): power-controller@2e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi1); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi2): power-controller@2e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi2); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi3): power-controller@2f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi3); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi4): power-controller@2f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x2f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi4); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi5): power-controller@300 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x300 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(spi5); + power-domains =3D <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_uart_n): power-controller@308 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x308 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart_n); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart0): power-controller@310 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x310 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart0); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_amcc1): power-controller@318 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x318 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc1); + apple,always-on; + }; + + DIE_NODE(ps_amcc3): power-controller@320 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x320 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(amcc3); + apple,always-on; + }; + + DIE_NODE(ps_dcs_04): power-controller@328 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x328 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_04); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_05): power-controller@330 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x330 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_05); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_06): power-controller@338 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x338 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_06); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_07): power-controller@340 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x340 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_07); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_12): power-controller@348 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x348 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_12); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_13): power-controller@350 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x350 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_13); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_14): power-controller@358 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x358 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_14); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_15): power-controller@360 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x360 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dcs_15); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_uart1): power-controller@368 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x368 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart1); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart2): power-controller@370 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x370 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart2); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart3): power-controller@378 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x378 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart3); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart4): power-controller@380 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x380 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart4); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart5): power-controller@388 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x388 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart5); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart6): power-controller@390 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x390 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(uart6); + power-domains =3D <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_mca0): power-controller@398 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x398 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mca0); + power-domains =3D <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca1): power-controller@3a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3a0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mca1); + power-domains =3D <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca2): power-controller@3a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3a8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mca2); + power-domains =3D <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca3): power-controller@3b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3b0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mca3); + power-domains =3D <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_dpa0): power-controller@3b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3b8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dpa0); + power-domains =3D <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa1): power-controller@3c0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3c0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dpa1); + power-domains =3D <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa2): power-controller@3c8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3c8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dpa2); + power-domains =3D <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa3): power-controller@3d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3d0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dpa3); + power-domains =3D <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0): power-controller@3d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3d8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(msr0); + }; + + DIE_NODE(ps_venc_sys): power-controller@3e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3e0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_sys); + }; + + DIE_NODE(ps_dpa4): power-controller@3e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3e8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dpa4); + power-domains =3D <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0_ase_core): power-controller@3f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3f0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(msr0_ase_core); + power-domains =3D <&DIE_NODE(ps_msr0)>; + }; + + DIE_NODE(ps_apcie_gpshr_sys): power-controller@3f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x3f8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_gpshr_sys); + power-domains =3D <&DIE_NODE(ps_apcie_gp)>; + }; + + DIE_NODE(ps_apcie_st_sys): power-controller@408 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x408 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_st_sys); + power-domains =3D <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(ps_apcie_st1_sys): power-controller@410 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x410 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_st1_sys); + power-domains =3D <&DIE_NODE(ps_apcie_st_sys)>; + }; + + DIE_NODE(ps_apcie_gp_sys): power-controller@418 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x418 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_gp_sys); + power-domains =3D <&DIE_NODE(ps_apcie_gpshr_sys)>; + apple,always-on; /* Breaks things if shut down */ + }; + + DIE_NODE(ps_apcie_ge_sys): power-controller@420 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x420 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_ge_sys); + power-domains =3D <&DIE_NODE(ps_apcie_gpshr_sys)>; + }; + + DIE_NODE(ps_apcie_phy_sw): power-controller@428 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x428 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(apcie_phy_sw); + apple,always-on; /* macOS does not turn this off */ + }; + + DIE_NODE(ps_sep): power-controller@c00 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xc00 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(sep); + apple,always-on; /* Locked on */ + }; + + /* There is a dependency tree involved with these PDs, + * but we do not express it here since the ISP driver + * is supposed to sequence them in the right order anyway. + * + * This also works around spurious parent PD activation + * on machines with ISP disabled (desktops), so we don't + * have to enable/disable everything in the per-model DTs. + */ + DIE_NODE(ps_isp_cpu): power-controller@4000 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_cpu); + /* power-domains =3D <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_fe): power-controller@4008 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_fe); + /* power-domains =3D <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_dprx): power-controller@4010 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(dprx); + /* power-domains =3D <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_vis): power-controller@4018 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_vis); + /* power-domains =3D <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_be): power-controller@4020 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_be); + /* power-domains =3D <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_raw): power-controller@4028 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4028 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_raw); + /* power-domains =3D <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_clr): power-controller@4030 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x4030 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(isp_clr); + /* power-domains =3D <&DIE_NODE(ps_isp_be)>; */ + }; + + DIE_NODE(ps_venc_dma): power-controller@8000 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x8000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_dma); + power-domains =3D <&DIE_NODE(ps_venc_sys)>; + }; + + DIE_NODE(ps_venc_pipe4): power-controller@8008 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x8008 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_pipe4); + power-domains =3D <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_pipe5): power-controller@8010 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x8010 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_pipe5); + power-domains =3D <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_me0): power-controller@8018 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x8018 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_me0); + power-domains =3D <&DIE_NODE(ps_venc_pipe5)>, <&DIE_NODE(ps_venc_pipe4)>; + }; + + DIE_NODE(ps_venc_me1): power-controller@8020 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x8020 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(venc_me1); + power-domains =3D <&DIE_NODE(ps_venc_me0)>; + }; + + DIE_NODE(ps_prores): power-controller@c000 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xc000 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(prores); + power-domains =3D <&DIE_NODE(ps_afnc3_lw0)>; + }; +}; + +&DIE_NODE(pmgr_mini) { + DIE_NODE(ps_debug): power-controller@58 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x58 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(debug); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi0): power-controller@60 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x60 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_spmi0); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi1): power-controller@68 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x68 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_spmi1); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_aon): power-controller@70 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x70 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_aon); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_msg): power-controller@78 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x78 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(msg); + apple,always-on; /* Core AON device? */ + }; + + DIE_NODE(ps_nub_gpio): power-controller@80 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x80 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_gpio); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_fabric): power-controller@88 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x88 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_fabric); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb_aon): power-controller@90 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x90 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc1_usb_aon): power-controller@98 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x98 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc2_usb_aon): power-controller@a0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xa0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc3_usb_aon): power-controller@a8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xa8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_mtp_fabric): power-controller@b0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xb0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_fabric); + apple,always-on; + power-domains =3D <&DIE_NODE(ps_nub_fabric)>; + status =3D "disabled"; + }; + + DIE_NODE(ps_nub_sram): power-controller@b8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xb8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(nub_sram); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_debug_switch): power-controller@c0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xc0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(debug_switch); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb): power-controller@c8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xc8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc0_usb); + power-domains =3D <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_usb): power-controller@d0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xd0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc1_usb); + power-domains =3D <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_usb): power-controller@d8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xd8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc2_usb); + power-domains =3D <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_usb): power-controller@e0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xe0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(atc3_usb); + power-domains =3D <&DIE_NODE(ps_atc3_common)>; + }; + +#if 0 + /* MTP stuff is self-managed */ + DIE_NODE(ps_mtp_gpio): power-controller@e8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xe8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_gpio); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_base): power-controller@f0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xf0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_base); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_periph): power-controller@f8 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0xf8 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_periph); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_spi0): power-controller@100 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x100 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_spi0); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_i2cm0): power-controller@108 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x108 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_i2cm0); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_uart0): power-controller@110 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x110 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_uart0); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_cpu): power-controller@118 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x118 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_cpu); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_scm_fabric): power-controller@120 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x120 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_scm_fabric); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_sram): power-controller@128 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x128 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_sram); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_scm_fabric)>, <&DIE_NODE(ps_mtp_cpu)= >; + }; + + DIE_NODE(ps_mtp_dma): power-controller@130 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x130 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(mtp_dma); + apple,always-on; /* MTP always stays on */ + power-domains =3D <&DIE_NODE(ps_mtp_sram)>; + }; +#endif +}; + +&DIE_NODE(pmgr_gfx) { + DIE_NODE(ps_gpx): power-controller@0 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x0 4>; + #power-domain-cells =3D <0>; + #reset-cells =3D <0>; + label =3D DIE_LABEL(gpx); + apple,min-state =3D <4>; + apple,always-on; + }; + + DIE_NODE(ps_afr): power-controller@100 { + compatible =3D "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg =3D <0x100 4>; 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Sun, 14 Sep 2025 15:39:02 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:47 +0200 Subject: [PATCH v2 4/6] arm64: dts: apple: Add J414 and J416 Macbook Pro device trees Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-4-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6075; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=oB8WY/oI9CwdJKKcWEmxl1NGWszokRrC4s3dN4D19h0=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkqcKX5swaLq/9TPd8mH6dqG5zHX24Yu8zp6tODG3e 9LlW9MvdJSyMIhxMciKKbIkab/sYFhdoxhT+yAMZg4rE8gQBi5OAZjI3ksM/x0nyBe+URdhznX6 66Pt9fbqitac+CqGgHtXXp96zHc3eAsjQ2NK+c2kWhXBgtULrpWpXo/9N/nCNYl61TniCxpm1J/ ayQEA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 From: Hector Martin Add device trees for the T6020 and T6021 based Macbook Pros (M2 Pro/Max, 14/16-inch). The devices are very similar to the T6000/T6001 based ones so reuse the device templates, include the new SoCs and correct for the minimal differences. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 4 +++ arch/arm64/boot/dts/apple/t6020-j414s.dts | 26 +++++++++++++++ arch/arm64/boot/dts/apple/t6020-j416s.dts | 26 +++++++++++++++ arch/arm64/boot/dts/apple/t6021-j414c.dts | 26 +++++++++++++++ arch/arm64/boot/dts/apple/t6021-j416c.dts | 26 +++++++++++++++ arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi | 45 ++++++++++++++++++++++= ++++ 6 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index df4ba8ef6213c9f7e4ef02a50d7250008977cc71..e97a6676387c6e4cbaf3b0834c4= e59338d08d1b8 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j414s.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j414c.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j416s.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j416c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6020-j414s.dts b/arch/arm64/boot/dt= s/apple/t6020-j414s.dts new file mode 100644 index 0000000000000000000000000000000000000000..631c54c5f03dee9e7d37a7811f8= 7f939e5187b10 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j414s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Pro, 2023) + * + * target-type: J414s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible =3D "apple,j414s", "apple,t6020", "apple,arm-platform"; + model =3D "Apple MacBook Pro (14-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type =3D "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type =3D "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6020-j416s.dts b/arch/arm64/boot/dt= s/apple/t6020-j416s.dts new file mode 100644 index 0000000000000000000000000000000000000000..c277ed5889a2145a4043b7f3230= dbd49971d3068 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j416s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Pro, 2023) + * + * target-type: J416s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible =3D "apple,j416s", "apple,t6020", "apple,arm-platform"; + model =3D "Apple MacBook Pro (16-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type =3D "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type =3D "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j414c.dts b/arch/arm64/boot/dt= s/apple/t6021-j414c.dts new file mode 100644 index 0000000000000000000000000000000000000000..cdcf0740714dcf71e8d0cead879= bce8f27431ccf --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j414c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Max, 2023) + * + * target-type: J414c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible =3D "apple,j414c", "apple,t6021", "apple,arm-platform"; + model =3D "Apple MacBook Pro (14-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type =3D "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type =3D "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j416c.dts b/arch/arm64/boot/dt= s/apple/t6021-j416c.dts new file mode 100644 index 0000000000000000000000000000000000000000..6d8146b941703692a0cd92508ad= d1784e0fc211b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j416c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Max, 2022) + * + * target-type: J416c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible =3D "apple,j416c", "apple,t6021", "apple,arm-platform"; + model =3D "Apple MacBook Pro (16-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type =3D "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type =3D "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi b/arch/arm64/bo= ot/dts/apple/t602x-j414-j416.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0e806d8ddf81b1073bfced964fa= 64c4e75a9e998 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14/16-inch, 2022) + * + * This file contains the parts common to J414 and J416 devices with both = t6020 and t6021. + * + * target-type: J414s / J414c / J416s / J416c + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are essentially identical to the previous generation, othe= r than + * the GPIO indices. + */ + +#include "t600x-j314-j316.dtsi" + +&framebuffer0 { + power-domains =3D <&ps_disp0_cpu0>, <&ps_dptx_phy_ps>; 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Sun, 14 Sep 2025 15:39:04 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:48 +0200 Subject: [PATCH v2 5/6] arm64: dts: apple: Add J474s, J475c and J475d device trees Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-5-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7359; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=ulmJ9Q9E5wPu/53catabwVrJTmiDve5jseB6PwOjhFc=; b=kA0DAAoWoRs8240vZWYByyZiAGjHGcqgLIp38IO8CSIRV+2sw3PRIytJCg8rLZdRyv147Sacv oh1BAAWCgAdFiEEYivpiACrfCFcfeBWoRs8240vZWYFAmjHGcoACgkQoRs8240vZWahlAD+OdwY is1e4dkCtjwaZ3Shn9aeJLoCsFjvjDGyESB4bRQBANqtXkdaXw1biDHV7Gbqs773X9AajSklOya WSPMiAw4M X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 Add device trees for the M2 Pro Mac mini and the M2 Max and Ultra Mac Studio. These devices are very similar to the M1 Max and Ultra Mac Studio so reuse the device template, include the .dtsi for the new SocS and correct for the minimal differences. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 3 ++ arch/arm64/boot/dts/apple/t6020-j474s.dts | 47 ++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t6021-j475c.dts | 37 ++++++++++++++++++++ arch/arm64/boot/dts/apple/t6022-j475d.dts | 42 +++++++++++++++++++++++ arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi | 38 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi | 38 +++++++++++++++++++++ 6 files changed, 205 insertions(+) diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index e97a6676387c6e4cbaf3b0834c4e59338d08d1b8..21c4e02a4429fa1db506dd85637= a44000073590e 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -83,6 +83,9 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j414s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j414c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j416s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j416c.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j474s.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j475c.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6022-j475d.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6020-j474s.dts b/arch/arm64/boot/dt= s/apple/t6020-j474s.dts new file mode 100644 index 0000000000000000000000000000000000000000..7c7ad5b8ad189e5d04d03189a07= c82426185dd7d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j474s.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) + * + * target-type: J474s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" + +/* + * This model is very similar to M1 and M2 Mac Studio models so base it on= those + * and remove the missing SDHCI controller. + */ + +#include "t602x-j474-j475.dtsi" + +/ { + compatible =3D "apple,j474s", "apple,t6020", "apple,arm-platform"; + model =3D "Apple Mac mini (M2 Pro, 2023)"; +}; + +/* PCIe devices */ +&wifi0 { + compatible =3D "pci14e4,4434"; + brcm,board-type =3D "apple,tasmania"; +}; + +&bluetooth0 { + compatible =3D "pci14e4,5f72"; + brcm,board-type =3D "apple,tasmania"; +}; + +/* + * port01 is unused, remove the PCIe sdhci0 node from t600x-j375.dtsi and = adjust + * the iommu-map. + */ +/delete-node/ &sdhci0; + +&pcie0 { + iommu-map =3D <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_2 1 1>, + <0x300 &pcie0_dart_3 1 1>; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j475c.dts b/arch/arm64/boot/dt= s/apple/t6021-j475c.dts new file mode 100644 index 0000000000000000000000000000000000000000..533e3577487469e868c05976013= f0d89ff3faea0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j475c.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Max, 2023) + * + * target-type: J475c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j474-j475.dtsi" + +/ { + compatible =3D "apple,j475c", "apple,t6021", "apple,arm-platform"; + model =3D "Apple Mac Studio (M2 Max, 2023)"; +}; + +&wifi0 { + compatible =3D "pci14e4,4434"; + brcm,board-type =3D "apple,canary"; +}; + +&bluetooth0 { + compatible =3D "pci14e4,5f72"; + brcm,board-type =3D "apple,canary"; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status =3D "okay"; +}; + +&pcie0_dart_1 { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dt= s/apple/t6022-j475d.dts new file mode 100644 index 0000000000000000000000000000000000000000..736594544f79b5e45f6ea0c98e6= c71d948ef7a43 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Ultra, 2023) + * + * target-type: J475d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t602x-j474-j475.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible =3D "apple,j475d", "apple,t6022", "apple,arm-platform"; + model =3D "Apple Mac Studio (M2 Ultra, 2023)"; +}; + +&framebuffer0 { + power-domains =3D <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status =3D "okay"; +}; + +&pcie0_dart_1 { + status =3D "okay"; +}; + +&wifi0 { + compatible =3D "pci14e4,4434"; + brcm,board-type =3D "apple,canary"; +}; + +&bluetooth0 { + compatible =3D "pci14e4,5f72"; + brcm,board-type =3D "apple,canary"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/d= ts/apple/t6022-jxxxd.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4f7bf2ebfe397dbde6451672d74= ef76fe782bcd0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) and Mac Studio (M2 Ultra, 2023) + * + * This file contains the parts common to J180 and J475 devices with t6022. + * + * target-type: J180d / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* delete power-domains for missing disp0 / disp0_die1 */ +/delete-node/ &ps_disp0_cpu0; +/delete-node/ &ps_disp0_fe; + +/delete-node/ &ps_disp0_cpu0_die1; +/delete-node/ &ps_disp0_fe_die1; + +/* USB Type C */ +&i2c0 { + /* front-right */ + hpm4: usb-pd@39 { + compatible =3D "apple,cd321x"; + reg =3D <0x39>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + /* front-left */ + hpm5: usb-pd@3a { + compatible =3D "apple,cd321x"; + reg =3D <0x3a>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi b/arch/arm64/bo= ot/dts/apple/t602x-j474-j475.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..ee12fea5b12cb37f95d9cb531c9= 065403665e8ca --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) and Mac Studio (2023) + * + * This file contains the parts common to J474 and J475 devices with t6020, + * t6021 and t6022. + * + * target-type: J474s / J475c / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are very similar to the previous generation Mac Studio, ot= her + * than GPIO indices. + */ + +#include "t600x-j375.dtsi" + +&framebuffer0 { + power-domains =3D <&ps_dispext0_cpu0>, <&ps_dptx_phy_ps>; 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Sun, 14 Sep 2025 15:39:07 -0400 (EDT) From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:49 +0200 Subject: [PATCH v2 6/6] arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-dt-apple-t6020-v2-6-1a738a98bb43@jannau.net> References: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> In-Reply-To: <20250914-dt-apple-t6020-v2-0-1a738a98bb43@jannau.net> To: Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hector Martin , Marc Zyngier Cc: asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4690; i=j@jannau.net; s=yk2025; h=from:subject:message-id; bh=faHpJABUmh2pQbfVmmffgLLfTnAIPKwSQ01C5YgS5kg=; b=owGbwMvMwCW2UNrmdq9+ahrjabUkhozjkqckss5fns2pYXRTq3oqdw9ziKPbM6Wn312aU9Zu4 3vdqLSgo5SFQYyLQVZMkSVJ+2UHw+oaxZjaB2Ewc1iZQIYwcHEKwETu1jMyrGT58Knnz6Z2uUj2 S2cSS/exrZz/JfmDwTfdziWPt0x1mcLIcFD+fP3uMh21B38Tvy7JPjNzh8wz8y+fI+YeLOy7U7z 8KRsA X-Developer-Key: i=j@jannau.net; a=openpgp; fpr=8B336A6BE4E5695E89B8532B81E806F586338419 From: Hector Martin The M2 Ultra in the Mac Pro differs from the M2 Ultra Mac Studio in its PCIe setup. It uses all available 16 PCIe Gen4 on the first die and 8 PCIe Gen4 lanes on the second die to connect to ann 100 lane Microchip Switchtec PCIe switch. All internal PCIe devices and the PCIe slots are connected to the PCIe switch. Each die has implements a PCIe controller with a single 16 or 8 lane port. The PCIe controller is mostly compatible with existing implementation in pcie-apple.c. The resources for other 8 lanes on the second die are used to connect the NVMe flash with the controller in the SoC. This initial device tree does not include PCIe support. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t6022-j180d.dts | 121 ++++++++++++++++++++++++++= ++++ 2 files changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple= /Makefile index 21c4e02a4429fa1db506dd85637a44000073590e..4eebcd85c90fcf0f358b0b32deb= f2475f6dbbf2c 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_APPLE) +=3D t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) +=3D t6022-j180d.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j414s.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6021-j414c.dtb dtb-$(CONFIG_ARCH_APPLE) +=3D t6020-j416s.dtb diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dt= s/apple/t6022-j180d.dts new file mode 100644 index 0000000000000000000000000000000000000000..dca6bd167c225aa23e78e1c644b= f6c97f42d46b5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) + * + * target-type: J180d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible =3D "apple,j180d", "apple,t6022", "apple,arm-platform"; + model =3D "Apple Mac Pro (M2 Ultra, 2023)"; + aliases { + nvram =3D &nvram; + serial0 =3D &serial0; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + stdout-path =3D "serial0"; + + framebuffer0: framebuffer@0 { + compatible =3D "apple,simple-framebuffer", "simple-framebuffer"; + reg =3D <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status =3D "disabled"; + power-domains =3D <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; + }; + }; + + memory@10000000000 { + device_type =3D "memory"; + reg =3D <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status =3D "okay"; +}; + +/* USB Type C Rear */ +&i2c0 { + hpm2: usb-pd@3b { + compatible =3D "apple,cd321x"; + reg =3D <0x3b>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm3: usb-pd@3c { + compatible =3D "apple,cd321x"; + reg =3D <0x3c>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ + + hpm6: usb-pd@3d { + compatible =3D "apple,cd321x"; + reg =3D <0x3d>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm7: usb-pd@3e { + compatible =3D "apple,cd321x"; + reg =3D <0x3e>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +/* USB Type C Front */ +&i2c3 { + status =3D "okay"; + + hpm0: usb-pd@38 { + compatible =3D "apple,cd321x"; + reg =3D <0x38>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; + + hpm1: usb-pd@3f { + compatible =3D "apple,cd321x"; + reg =3D <0x3f>; + interrupt-parent =3D <&pinctrl_ap>; + interrupts =3D <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "irq"; + }; +}; + +/* + * Delete unused PCIe nodes, the Mac Pro uses slightly different PCIe + * controllers with a single port connected to a PM40100 PCIe switch + */ +/delete-node/ &pcie0; +/delete-node/ &pcie0_dart_0; +/delete-node/ &pcie0_dart_1; +/delete-node/ &pcie0_dart_2; +/delete-node/ &pcie0_dart_3; + +&nco_clkref { + clock-frequency =3D <1068000000>; +}; + +#include "spi1-nvram.dtsi" --=20 2.51.0