From nobody Thu Oct 2 18:19:18 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1202ECE8F; Sat, 13 Sep 2025 10:13:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758438; cv=none; b=QrlZwXVvI0S2JXX8O0K4cPxyLG9p8SY0FTMbg8o75Pp6KMc127MKAM6TYYoROEP7qUf6s7sYmZGXZ+JxsxSWsvwimx+ND/lelJPRP2G40AWzloSmnIVkt6B+nxW9b6FXhLIvpcgWJNzzRfe7+nJe81eH50fLFZHk7hXHENtojec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758438; c=relaxed/simple; bh=F1DxGedyVmvL5QMILi5W2tfKDMHyreDrXh2WSu7hfs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D9iiM6sZ03grKWDh0ohC5gC1aRmDcH4LdMAxubiJh8AMDUg68vCk++lRzRzLw5R5J/pCkROebeBoN015pQ8mDIHtfU3t/52AyUJDRUJhz2yPN2dEvG6JleUzu/BpOLVri2sd5aFqmF37fvDT1Fm2GoAJ4Hq97ypPIGmCvm3sW0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DQQ5FjgV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DQQ5FjgV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C68E3C4CEF4; Sat, 13 Sep 2025 10:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758438; bh=F1DxGedyVmvL5QMILi5W2tfKDMHyreDrXh2WSu7hfs8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DQQ5FjgVKd3Jpu23xcfWXAhyXGmYcyzoFAZ+vaXeFiCObqH03QIqLWEJLX4kwXetO XgJMv+W3YKyMwzR4iZypPS3mB9dto9gvVv9PP1C8un23/RbK21uz1Xoz9RWWjJHQ68 0qRDYCyWe9t3XhiPGms5XWTTEZxy7unKMjMqjUFqP0jvY26gPnuYrloC0QWmWdJODS fmalaxwWs7ZnfLOMs3sbMnZw43aLEutXHGL4eiuzg8j3qQYOVGu9EioqJl7aBxpcwj Zw41g5e8Wil/BxBSSDOAEp6qrvC7VYvMMR+UqXqYs9F8FSQqBgdhGp/uylS5SpnF0y hTtcl54R22zgw== Received: by wens.tw (Postfix, from userid 1000) id 6E0175FE52; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v6 6/6] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Sat, 13 Sep 2025 18:13:49 +0800 Message-Id: <20250913101349.3932677-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 38cd8c7e92da..7afd6e57fe86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,11 +96,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5