From nobody Thu Oct 2 18:17:39 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF2022D0C7B; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; cv=none; b=fcyKDiOAlbe6JbCMUSJZUlhkkSYeL51SuQkOrITJiDy27orQgdKeF4QA+OH+EUi4S2TFcGqSgbNdOssO3eshgrXkc4tuUiV0Zp2yyxTdTGRwMPJGRCEmxSTwt+1KGq+S/P2IoNsnhoVzV68QuE1pdiVzYiQtvVLFKBGRYHp28nE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; c=relaxed/simple; bh=4zsAEhgPLF5E1lZqO74cbTZq68y+QkaCgneVZaDgIWM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kJkQvCMsIx0bKT0G1g6qi3AqfEpcVgtd+qC0EHoa2I2To6xLludIdHyx45BV5mruEZI0+0EHUfqqOQ8agRtStJnooPBR5lJd7VW+CmX+807kohKJPZjwJygNNGQxvVJv2J8TZp7S2nNxEuQ5iriYJzqN1pngoOEk+i+HFiX0+d4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=us0kZqdp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="us0kZqdp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41567C4CEEB; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758435; bh=4zsAEhgPLF5E1lZqO74cbTZq68y+QkaCgneVZaDgIWM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=us0kZqdpYRqjwaxB6OYXPMK3Ca3nQQEopN3oE5iPkEvrqb1uwzcWcp2x9HT35FyWk Zhjznfl9QrM+Tae3+7C4d6audEuRlMO6D9zyhzgQxnvWIqydD7Givxo2I4q5sLZ9yd +TMKlRJ0rX2MtOwEy3ChOAEeeHZpSKChgRp/gR/xxgHCj8DgtjqnroqJdbt8g42aV3 AV5RDeZD8FTQ5TaxRMlymIxOpBB8iOivusZZcO+gW28rpuLk6EfceFwEfqgMCJTDkT gdHxFc4Qr+Ue1t9NMQt8EtoE69g4MMw6Pf94NNoS7CXtmP5VwB+41QhxjPyHiCtvU8 zcizn7sYjuS0g== Received: by wens.tw (Postfix, from userid 1000) id 3DD185FE35; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v6 3/6] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Sat, 13 Sep 2025 18:13:46 +0800 Message-Id: <20250913101349.3932677-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 1b9a392f9bbf..9676caf9bd4e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -191,6 +191,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -681,6 +691,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5