From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C6632EBB9B; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758436; cv=none; b=bRZhOVB0RUS+4ud1TabQs9wSynaVhGthZLEVqy4xg+TPPare+ZD38FvaLaW4CVJO7TWqw+wXLkHM71u0hbU3xJmGTW+o7jZwXFwp32NCTcioWSHOnA1GEIsCRsKuRf7XIssjLyNo5DE+++GjYgDnT1ZfQSsL/Fmx3+WN9gl9Ppc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758436; c=relaxed/simple; bh=EUHf/HJMqycKHb+xK0fWFR42cC3Oe682CeoIddIqU/M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tSpUIHTLISV9q2CO1wPPRzJVgm0S8ji84AEdYlghfggFDVRT9xsi4xJil0vdokTShBV7vuDnvI8S8NK+w869zzBSEldVy955cnxqH5KLFY0D0xaSIQa9eUAN4w5Zf8ScyOSO7rYcDqGZrgr4XbMSnLhrV4w9fsTKIDz8oyQ2TBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kWFesRbq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kWFesRbq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62A3CC4CEFA; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758435; bh=EUHf/HJMqycKHb+xK0fWFR42cC3Oe682CeoIddIqU/M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kWFesRbqbkz4Jo9G1gp2l+AGKgjwXJqKG/MtzDM/A20Nm6hc1wcrOKUkpyagBa0m8 oZXBwmxJoANiT/OF61Ws5eLHUsAacRmciGpBtwLan0zEPE8dOGyY3qfdYMNw/AR63g q3jFCd95BnMQ5ju3ew1chQkKD6Xmq9IE2CjOXrLr/HyCjMC1gbr0DisA8T9XecUn5A BMKOOg6rm0yLPevGTz356dMAi5/HHLHCK+mhm2xAaWM8PUJE1gnbf/S7pq/oCyKdkL omWXT5tQlJsI03gLLldujUBe89PLnEUbhOBXOx9ijAtzSdKZyFxicv9qaucV64moDg 1hqqUZZQdrTQg== Received: by wens.tw (Postfix, from userid 1000) id 2E7AB5FBD7; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v6 1/6] dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Date: Sat, 13 Sep 2025 18:13:44 +0800 Message-Id: <20250913101349.3932677-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a compatible string entry for it, and work in the requirements for a second clock and a power domain. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) --- Changes since v4: - Move clock-names list to main schema (Rob) Changes since v2: - Added "select" to avoid matching against all dwmac entries Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../net/allwinner,sun8i-a83t-emac.yaml | 95 ++++++++++++++++++- 1 file changed, 93 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-ema= c.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.ya= ml index 2ac709a4c472..fc62fb2a68ac 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai - Maxime Ripard =20 +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a =20 reg: maxItems: 1 @@ -37,14 +55,21 @@ properties: const: macirq =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clock-names: - const: stmmaceth + minItems: 1 + items: + - const: stmmaceth + - const: mbus =20 phy-supply: description: PHY regulator =20 + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +216,42 @@ allOf: - mdio-parent-bus - mdio@1 =20 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + power-domains: false + + unevaluatedProperties: false =20 examples: @@ -323,4 +384,34 @@ examples: }; }; =20 + - | + ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu 117>, <&ccu 79>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu 43>; + reset-names =3D "stmmaceth"; + interrupts =3D <0 47 4>; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 4>; + syscon =3D <&syscon>; + phy-handle =3D <&ext_rgmii_phy_1>; + phy-mode =3D "rgmii-id"; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; ... --=20 2.39.5 From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E24312E8DF1; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="I4/ZZkC3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B99FC4CEF9; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758435; bh=2ycJx+XGnd4FebGA++3amDG08CwpEnAgC9ZyVof2ajA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I4/ZZkC3IBvcakY7a9rFjHnflhZ60/A1TjG2Zm4N/ZYWmdxI6DTFDBrQ0k4aFXitS f4xDQ6zLnOHr4fON+Q/AlrGzciq2M2dT4Vfi3tDDCFf7S60A+h+EgljJ9KL39vbxE8 6/TiY9XIPeI6/jrOxVTiLxCHpZ3B8HWqqH6i13/72pujE5LQ02Kr11smEPCCbkBxFB JIaWW+xyoZDEw7AZWXrxWlqFYOpFMSm9IPVmskOJI1hdz9xWltAHCZoCeOeYl4NOV7 gobu07At3yF06aVxe0RYvL15SuprJRnvZTIxr3lW+FaZd4S7K7EtRGd4TInAhSgh53 SdsFsI+DJ4ldA== Received: by wens.tw (Postfix, from userid 1000) id 496795FEDF; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara Subject: [PATCH net-next v6 2/6] net: stmmac: Add support for Allwinner A523 GMAC200 Date: Sat, 13 Sep 2025 18:13:45 +0800 Message-Id: <20250913101349.3932677-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner A523 SoC family has a second Ethernet controller, called the GMAC200 in the BSP and T527 datasheet, and referred to as GMAC1 for numbering. This controller, according to BSP sources, is fully compatible with a slightly newer version of the Synopsys DWMAC core. The glue layer around the controller is the same as found around older DWMAC cores on Allwinner SoCs. The only slight difference is that since this is the second controller on the SoC, the register for the clock delay controls is at a different offset. Last, the integration includes a dedicated clock gate for the memory bus and the whole thing is put in a separately controllable power domain. Add a new driver for this hardware supporting the integration layer. Signed-off-by: Chen-Yu Tsai --- Changes since v5: - Use plat->phy_interface instead of plat->mac_interface (Russell) Changes since v3: - Fixed printf format specifier warning Changes since v2 (all suggested by Russell King): - Include "ps" unit in "... must be multiple of ..." error message - Use FIELD_FIT to check if delay value is in range and FIELD_MAX to get the maximum value - Reword error message for delay value exceeding maximum - Drop MASK_TO_VAL Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Change dev_err() + return to dev_err_probe() - Check return value from syscon regmap write - Change driver name to match file name --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sun55i.c | 159 ++++++++++++++++++ 3 files changed, 172 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..38ce9a0cfb5b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -263,6 +263,18 @@ config DWMAC_SUN8I stmmac device driver. This driver is used for H3/A83T/A64 EMAC ethernet controller. =20 +config DWMAC_SUN55I + tristate "Allwinner sun55i GMAC200 support" + default ARCH_SUNXI + depends on OF && (ARCH_SUNXI || COMPILE_TEST) + select MDIO_BUS_MUX + help + Support for Allwinner A523/T527 GMAC200 ethernet controllers. + + This selects Allwinner SoC glue layer support for the + stmmac device driver. This driver is used for A523/T527 + GMAC200 ethernet controller. + config DWMAC_THEAD tristate "T-HEAD dwmac support" depends on OF && (ARCH_THEAD || COMPILE_TEST) diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..51e068e26ce4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_STI) +=3D dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) +=3D dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) +=3D dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) +=3D dwmac-sun8i.o +obj-$(CONFIG_DWMAC_SUN55I) +=3D dwmac-sun55i.o obj-$(CONFIG_DWMAC_THEAD) +=3D dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) +=3D dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) +=3D dwmac-intel-plat.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c b/drivers/n= et/ethernet/stmicro/stmmac/dwmac-sun55i.c new file mode 100644 index 000000000000..862df173d963 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun55i.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dwmac-sun55i.c - Allwinner sun55i GMAC200 specific glue layer + * + * Copyright (C) 2025 Chen-Yu Tsai + * + * syscon parts taken from dwmac-sun8i.c, which is + * + * Copyright (C) 2017 Corentin Labbe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define SYSCON_REG 0x34 + +/* RMII specific bits */ +#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */ +/* Generic system control EMAC_CLK bits */ +#define SYSCON_ETXDC_MASK GENMASK(12, 10) +#define SYSCON_ERXDC_MASK GENMASK(9, 5) +/* EMAC PHY Interface Type */ +#define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SYSCON_ETCS_MASK GENMASK(1, 0) +#define SYSCON_ETCS_MII 0x0 +#define SYSCON_ETCS_EXT_GMII 0x1 +#define SYSCON_ETCS_INT_GMII 0x2 + +static int sun55i_gmac200_set_syscon(struct device *dev, + struct plat_stmmacenet_data *plat) +{ + struct device_node *node =3D dev->of_node; + struct regmap *regmap; + u32 val, reg =3D 0; + int ret; + + regmap =3D syscon_regmap_lookup_by_phandle(node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Unable to map syscon\n"); + + if (!of_property_read_u32(node, "tx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "tx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set tx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ETXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "TX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ETXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ETXDC_MASK, val); + } + + if (!of_property_read_u32(node, "rx-internal-delay-ps", &val)) { + if (val % 100) + return dev_err_probe(dev, -EINVAL, + "rx-delay must be a multiple of 100ps\n"); + val /=3D 100; + dev_dbg(dev, "set rx-delay to %x\n", val); + if (!FIELD_FIT(SYSCON_ERXDC_MASK, val)) + return dev_err_probe(dev, -EINVAL, + "RX clock delay exceeds maximum (%u00ps > %lu00ps)\n", + val, FIELD_MAX(SYSCON_ERXDC_MASK)); + + reg |=3D FIELD_PREP(SYSCON_ERXDC_MASK, val); + } + + switch (plat->phy_interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + reg |=3D SYSCON_EPIT | SYSCON_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + reg |=3D SYSCON_RMII_EN; + break; + default: + return dev_err_probe(dev, -EINVAL, "Unsupported interface mode: %s", + phy_modes(plat->phy_interface)); + } + + ret =3D regmap_write(regmap, SYSCON_REG, reg); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to write to syscon\n"); + + return 0; +} + +static int sun55i_gmac200_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct device *dev =3D &pdev->dev; + struct clk *clk; + int ret; + + ret =3D stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + /* BSP disables it */ + plat_dat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + plat_dat->host_dma_width =3D 32; + + ret =3D sun55i_gmac200_set_syscon(dev, plat_dat); + if (ret) + return ret; + + clk =3D devm_clk_get_enabled(dev, "mbus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to get or enable MBUS clock\n"); + + ret =3D devm_regulator_get_enable_optional(dev, "phy"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get or enable PHY supply\n"); + + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); +} + +static const struct of_device_id sun55i_gmac200_match[] =3D { + { .compatible =3D "allwinner,sun55i-a523-gmac200" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun55i_gmac200_match); + +static struct platform_driver sun55i_gmac200_driver =3D { + .probe =3D sun55i_gmac200_probe, + .driver =3D { + .name =3D "dwmac-sun55i", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D sun55i_gmac200_match, + }, +}; +module_platform_driver(sun55i_gmac200_driver); + +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_DESCRIPTION("Allwinner sun55i GMAC200 specific glue layer"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF2022D0C7B; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; cv=none; b=fcyKDiOAlbe6JbCMUSJZUlhkkSYeL51SuQkOrITJiDy27orQgdKeF4QA+OH+EUi4S2TFcGqSgbNdOssO3eshgrXkc4tuUiV0Zp2yyxTdTGRwMPJGRCEmxSTwt+1KGq+S/P2IoNsnhoVzV68QuE1pdiVzYiQtvVLFKBGRYHp28nE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; c=relaxed/simple; bh=4zsAEhgPLF5E1lZqO74cbTZq68y+QkaCgneVZaDgIWM=; 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Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v6 3/6] arm64: dts: allwinner: a523: Add GMAC200 ethernet controller Date: Sat, 13 Sep 2025 18:13:46 +0800 Message-Id: <20250913101349.3932677-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has a second ethernet controller, called the GMAC200. It is not exposed on all the SoCs in the family. Add a device node for it. All the hardware specific settings are from the vendor BSP. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Fixed typo in tx-queues-config --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 1b9a392f9bbf..9676caf9bd4e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -191,6 +191,16 @@ rgmii0_pins: rgmii0-pins { bias-disable; }; =20 + rgmii1_pins: rgmii1-pins { + pins =3D "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", + "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", + "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; + allwinner,pinmux =3D <5>; + function =3D "gmac1"; + drive-strength =3D <40>; + bias-disable; + }; + uart0_pb_pins: uart0-pb-pins { pins =3D "PB9", "PB10"; allwinner,pinmux =3D <2>; @@ -681,6 +691,51 @@ mdio0: mdio { }; }; =20 + gmac1: ethernet@4510000 { + compatible =3D "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg =3D <0x04510000 0x10000>; + clocks =3D <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; + clock-names =3D "stmmaceth", "mbus"; + resets =3D <&ccu RST_BUS_EMAC1>; + reset-names =3D "stmmaceth"; + interrupts =3D ; + interrupt-names =3D "macirq"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins>; + power-domains =3D <&pck600 PD_VO1>; + syscon =3D <&syscon>; + snps,fixed-burst; + snps,axi-config =3D <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config =3D <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config =3D <&gmac1_mtl_tx_setup>; + status =3D "disabled"; + + mdio1: mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + + queue0 {}; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0xf>; + snps,rd_osr_lmt =3D <0xf>; + snps,blen =3D <256 128 64 32 16 8 4>; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + + queue0 {}; + }; + }; + ppu: power-controller@7001400 { compatible =3D "allwinner,sun55i-a523-ppu"; reg =3D <0x07001400 0x400>; --=20 2.39.5 From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF18E27EFEE; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; cv=none; b=qgReufQDvxQM5mM8HxjqA64fsWHIicdzX11/lGZGUEMgcqr6bA/dRbbH6wDSVc4rXac8IBXaM1NyROyBGmEV9pcjozOnuBL7Z7Y1j7bufKZNBL2OmP4aI0XzZpHbGLhpZxUzNgQO1lUygO8xu7q46BQfRggC5Bj1JT0qWx/GpnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758435; c=relaxed/simple; bh=uugv4ih9nUfyLSO+weAo82v6n2xq5poL7/MsFQnpIOA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DeFMX1J8TsHzuuG9xr4NTEtZ9LktDNWzQvKk4m6VOT9UZu7JpJBzBc36RACP2VRQHDwLsaFD85tp0vYIl7RcqbdjFkOgwi4RL7t/lmYF82Xg7eedE4FUDtO8Gw3CaEWN8fe0aqLCYwgzYrzd2943R9WN9zp+BLPz58f937+wdDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mFmdph8L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mFmdph8L" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D45FC4CEF4; Sat, 13 Sep 2025 10:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758435; bh=uugv4ih9nUfyLSO+weAo82v6n2xq5poL7/MsFQnpIOA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mFmdph8L2ZMfb6RQU3bnoznLMG+hO5vDVVOfZho1iUpVig1jyD858Q9YyafuZwLwm 4hfhX+N/bygrGFjg6ldvZ454mbPht5CzjKHpfmhFln06ytmWdZzH6PfqNwLSgGZcmu Z/bmFEDQouExnAwn/J9wy1k2NhnsiueLjavKThqxgYYaM1VBqE5OAUU/hn16u3bb/2 ZVWDKL1JYGSThb2rWqTzQcc3L3BZCX05TD/ixGcDhYJUv0H9b3zVi/AHFBwCQE4fny bXTdNUxCpEim/9Woxzr7x75A9IRVczrGYo2aEbNgbs98KxDWi4oBrIT/CJwqD6/BQb 2QERk49YDaVrA== Received: by wens.tw (Postfix, from userid 1000) id 522805FEF1; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v6 4/6] arm64: dts: allwinner: a527: cubie-a5e: Enable second Ethernet port Date: Sat, 13 Sep 2025 18:13:47 +0800 Message-Id: <20250913101349.3932677-5-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Radxa Cubie A5E board, the second Ethernet controller, aka the GMAC200, is connected to a second external Maxio MAE0621A PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. An enable delay for the PHY supply regulator is added to make sure the PHY's internal regulators are fully powered and the PHY is operational. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties - Add PHY regulator delay --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 28 +++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..e96a419faf21 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -14,6 +14,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -76,7 +77,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_cldo3>; =20 allwinner,tx-delay-ps =3D <300>; @@ -85,13 +86,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <300>; + rx-internal-delay-ps =3D <400>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -100,6 +112,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ @@ -240,6 +262,8 @@ reg_cldo4: cldo4 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc-pj-phy"; + /* enough time for the PHY to fully power on */ + regulator-enable-ramp-delay =3D <150000>; }; =20 reg_cpusldo: cpusldo { --=20 2.39.5 From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2B742ECD2C; Sat, 13 Sep 2025 10:13:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758437; cv=none; b=kBKlhq5/4RBE6bh4J7+KOMb6iJASHMPkZBjTTuUdgvvOG0ngQgBE9kSZ2t1G/Opst3c1klVuNIDMlU0lgZOZmHadqi3L7zpZgF4Zd1seCLniHPTZ5KQPb2zOwdXjNo7cP6kqkSeqUybQ7Af595jM1k+U8YbscnFLqto+2hj2F8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758437; c=relaxed/simple; bh=DMZOlPHKGGqu2GeBUhHX5OGLOzhVhpJibAq4mRN3kNs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ma+ziQux/Q9TwMlVmIA4ia663p1YeTc5FUAyUIFO5LZv5nzJ8ktiDeToAP2FmuBViZFQwRvVG8GeJv+SKY8i5aeVD2rzM2ZDsw86nebHszyJyUoA8XLsge3H+5gbv4LgYTpyBgINxy3llAoN7Hyohi/PnEtEBOFHjGc7D9hGOx8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PGaktS2U; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PGaktS2U" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5744DC4CEF8; Sat, 13 Sep 2025 10:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758437; bh=DMZOlPHKGGqu2GeBUhHX5OGLOzhVhpJibAq4mRN3kNs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PGaktS2UaEUclwr79I8quEPNzZSanM1g/BstUnAVgTInkxU57BTm43qmqAZipU6WB GZkZU9ILcVTGmgu3y2ZO+iv+NA9j3QCIE/jkbJmlYaijsKy8WQOGiP/8xjT7QPHTvd 2jqBuYMBu6guKS3dDEsdVsUQ4MQ6JCTPt+V/AFFpM2Dj2HxMIm8rWhkZ7UdQneEgxJ 5PxwthGCFduxexAVKJA5akLDUiQ9VH5GGLUFzX4c5ss4TGSGHEUy7PUDnx0Vz7p85K UuHvOxIiplFNMDnPr0PtrfhdsDxzv8/E4MoSxfeubxfujw79kKDqznPSdtgtnfrXBf n22MOmg8+KQ9A== Received: by wens.tw (Postfix, from userid 1000) id 6065A5FEE9; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v6 5/6] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Sat, 13 Sep 2025 18:13:48 +0800 Message-Id: <20250913101349.3932677-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..f540965ffaa4 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,13 +77,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -91,6 +103,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5 From nobody Thu Oct 2 17:01:15 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F1202ECE8F; Sat, 13 Sep 2025 10:13:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758438; cv=none; b=QrlZwXVvI0S2JXX8O0K4cPxyLG9p8SY0FTMbg8o75Pp6KMc127MKAM6TYYoROEP7qUf6s7sYmZGXZ+JxsxSWsvwimx+ND/lelJPRP2G40AWzloSmnIVkt6B+nxW9b6FXhLIvpcgWJNzzRfe7+nJe81eH50fLFZHk7hXHENtojec= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757758438; c=relaxed/simple; bh=F1DxGedyVmvL5QMILi5W2tfKDMHyreDrXh2WSu7hfs8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D9iiM6sZ03grKWDh0ohC5gC1aRmDcH4LdMAxubiJh8AMDUg68vCk++lRzRzLw5R5J/pCkROebeBoN015pQ8mDIHtfU3t/52AyUJDRUJhz2yPN2dEvG6JleUzu/BpOLVri2sd5aFqmF37fvDT1Fm2GoAJ4Hq97ypPIGmCvm3sW0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DQQ5FjgV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DQQ5FjgV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C68E3C4CEF4; Sat, 13 Sep 2025 10:13:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757758438; bh=F1DxGedyVmvL5QMILi5W2tfKDMHyreDrXh2WSu7hfs8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DQQ5FjgVKd3Jpu23xcfWXAhyXGmYcyzoFAZ+vaXeFiCObqH03QIqLWEJLX4kwXetO XgJMv+W3YKyMwzR4iZypPS3mB9dto9gvVv9PP1C8un23/RbK21uz1Xoz9RWWjJHQ68 0qRDYCyWe9t3XhiPGms5XWTTEZxy7unKMjMqjUFqP0jvY26gPnuYrloC0QWmWdJODS fmalaxwWs7ZnfLOMs3sbMnZw43aLEutXHGL4eiuzg8j3qQYOVGu9EioqJl7aBxpcwj Zw41g5e8Wil/BxBSSDOAEp6qrvC7VYvMMR+UqXqYs9F8FSQqBgdhGp/uylS5SpnF0y hTtcl54R22zgw== Received: by wens.tw (Postfix, from userid 1000) id 6E0175FE52; Sat, 13 Sep 2025 18:13:53 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec , Andrew Lunn Subject: [PATCH net-next v6 6/6] arm64: dts: allwinner: t527: orangepi-4a: Enable Ethernet port Date: Sat, 13 Sep 2025 18:13:49 +0800 Message-Id: <20250913101349.3932677-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250913101349.3932677-1-wens@kernel.org> References: <20250913101349.3932677-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Orangepi 4A board, the second Ethernet controller, aka the GMAC200, is connected to an external Motorcomm YT8531 PHY. The PHY uses an external 25MHz crystal, has the SoC's PI15 pin connected to its reset pin, and the PI16 pin for its interrupt pin. Enable it. Acked-by: Jernej Skrabec Reviewed-by: Andrew Lunn Signed-off-by: Chen-Yu Tsai --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 38cd8c7e92da..7afd6e57fe86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -15,6 +15,7 @@ / { compatible =3D "xunlong,orangepi-4a", "allwinner,sun55i-t527"; =20 aliases { + ethernet0 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -95,11 +96,33 @@ &ehci1 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + phy-supply =3D <®_cldo4>; + + tx-internal-delay-ps =3D <0>; + rx-internal-delay-ps =3D <300>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 +&mdio1 { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupts-extended =3D <&pio 8 16 IRQ_TYPE_LEVEL_LOW>; /* PI16 */ + reset-gpios =3D <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5