From nobody Thu Oct 2 17:00:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8FBA20E6F3; Sat, 13 Sep 2025 19:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757791191; cv=none; b=dTaT+/I3UXe5FiNTfDrHIoppwKk+FpU7n3tTCk9/IDaRlmZB+JnbJ8mOKeEOXdcrQOqyDBgXJ3oixnwsoRTYbABSWIQOjav80SAZxdKOVvbQ9ocIDGl2NAjlD5DqTHt7KzhCjt0jYKkB9ZiWjHzwqAJcmb9L2BHYQ6iG80x4NEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757791191; c=relaxed/simple; bh=D2z+oF6F047TpnEznp6oagMdF2PSz/sUfdT88afYQ90=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PFPFiAnxg+gqAm/00QyiTNQKxObuwnqe7RP4XYqvxmoSVfSDMXOrygk1PHuLDqrmAEtX8SuQ4b6jnS516AoH5kcxYLIrzomwLQeMYkqpswiS4Nsat9yXDyFOhpvx9JLMJRs80uDvJIwdHFWOzgDxINbGBu4ypUdrL1SJNxoXWd0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A72VPpGF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A72VPpGF" Received: by smtp.kernel.org (Postfix) with ESMTPS id 70800C4CEF8; Sat, 13 Sep 2025 19:19:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757791191; bh=D2z+oF6F047TpnEznp6oagMdF2PSz/sUfdT88afYQ90=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=A72VPpGFVghpgMn2T0yPgyZ0n1JTlXbIFH/A2hfK9K2eYi/6+Bv397UIKmvY8LDPb nN27ItFGO4oKidqKlGp3E/zouaIYdnM41Z3oDK6Ks1mtqpIWFhRwBGNKpBBgb7VVhg MspRzi9SoI3edPMR96Ti6m3yTeWaUbajFKUsWr9EWTqAHjlq8oDc33lJpwyJg5Wo+G KweZYHOZMQSIlEPw6W1Ddj43pD+OXIHjWlV9B4OQ3TMPVbhvhbpWp9qforKtWSRmbF g9lWVlnyxc6OQhmjS7PJF3hpCGdlojRSh2xbGc6q2sACsSKGFswJ2qL3nYYS5LwtIE MjpM3BGyma7rA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F954CAC58E; Sat, 13 Sep 2025 19:19:51 +0000 (UTC) From: David Heidelberg via B4 Relay Date: Sat, 13 Sep 2025 21:19:47 +0200 Subject: [PATCH v6 1/3] drm: panel: nt36672a: Make some command sequences optional Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250913-nt35596s-v6-1-b5deb05e04af@ixit.cz> References: <20250913-nt35596s-v6-0-b5deb05e04af@ixit.cz> In-Reply-To: <20250913-nt35596s-v6-0-b5deb05e04af@ixit.cz> To: Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Molly Sophia , Arnaud Ferraris , David Heidelberg X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2103; i=david@ixit.cz; h=from:subject:message-id; bh=QTYZEo7wDH4JK80WKEmXRMnm9sUlw16EBzi/obT5zQ0=; b=kA0DAAgBYAI/xNNJIHIByyZiAGjFw9Wiz6mWj07JiHm6qevg86j9McXDcPlt/chYi0NaAMDNR YkCMwQAAQgAHRYhBNd6Cc/u3Cu9U6cEdGACP8TTSSByBQJoxcPVAAoJEGACP8TTSSByOs0P/21U TZd6OHLvr3BU1Xdty/CGUydc1FZm6ai45xC1u3qU/2A8e62YzTdw2IzimQ7sOdBpMRy1Zzyco2d Njsnf9kVicuAKt96lmxmxqrbXAUiOpZy/nczu+HpsBwp/5ElvQtBfMdCodH0gXqXK3OTlkR84Ou xBGh2BmubM5Habr1Oz/hG4scz99+tbsK2wmYM3V+PactnIqK9F32E+2vOhYjPOUkTs3SQRaap4H GJi8g8IJiB9CmdCHde9lG5sZ6EaCkBvXb6RYyt3l+PEsqhlT7IsWPLddLX4rkDqsuV9nrTiCnRv J5gTt4NNa2DF6Wts6lmn45LYa1GS+pcJWkq54n8/wcO1AuBZeblHjo3KgPi518LsRp/2Ka0/88M 26tY5RLn/JJc0RQCUOhLMB1+YLILkYDx/Iz9H+JulJq2Mv53NFpOxAxylg7lXby7mMTTwy29mUz pL8vB04bbgzUTHssVbT/TkoG3aZia6Zh0ZZc/J9p9LjGJaFOmZ1N1GYeCqrnNZZu5oLxGpMzTMQ RIPqETejk8aPGN4oT3k5dDwZMWsPnuKU86Nf3aEVo5QDAXUzC+S86KLD4Z5MBPD4F3Td9DQrCIB BbEECYECD7i2xpjlgiIoDpgj/g6vldfR7q0uVWOikwpJismepvj3lr0MDa3swORiLT3zGsRlKHt 6Dvhx X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Molly Sophia Preparation for the follow-up nt35596s support, where not all sequences are provided. Signed-off-by: Molly Sophia Signed-off-by: Arnaud Ferraris Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 27 ++++++++++++++--------= ---- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index 29e1f6aea48060384f4639999174b67097a6c8a7..f7518ec469176a4e2d4f2b03f8e= 77f03511a12a7 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -117,12 +117,13 @@ static int nt36672a_panel_unprepare(struct drm_panel = *panel) struct nt36672a_panel *pinfo =3D to_nt36672a_panel(panel); int ret; =20 - /* send off cmds */ - ret =3D nt36672a_send_cmds(panel, pinfo->desc->off_cmds, - pinfo->desc->num_off_cmds); - - if (ret < 0) - dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret); + if (pinfo->desc->num_off_cmds !=3D 0) { + /* send off cmds if present */ + ret =3D nt36672a_send_cmds(panel, pinfo->desc->off_cmds, + pinfo->desc->num_off_cmds); + if (ret < 0) + dev_err(panel->dev, "failed to send DCS off cmds: %d\n", ret); + } =20 ret =3D mipi_dsi_dcs_set_display_off(pinfo->link); if (ret < 0) @@ -200,13 +201,15 @@ static int nt36672a_panel_prepare(struct drm_panel *p= anel) goto poweroff; } =20 - /* Send rest of the init cmds */ - err =3D nt36672a_send_cmds(panel, pinfo->desc->on_cmds_2, - pinfo->desc->num_on_cmds_2); + if (pinfo->desc->num_on_cmds_2 !=3D 0) { + /* Send rest of the init cmds if present */ + err =3D nt36672a_send_cmds(panel, pinfo->desc->on_cmds_2, + pinfo->desc->num_on_cmds_2); =20 - if (err < 0) { - dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err); - goto poweroff; + if (err < 0) { + dev_err(panel->dev, "failed to send DCS Init 2nd Code: %d\n", err); + goto poweroff; + } } =20 msleep(120); --=20 2.51.0 From nobody Thu Oct 2 17:00:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0719023D7EB; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250913-nt35596s-v6-2-b5deb05e04af@ixit.cz> References: <20250913-nt35596s-v6-0-b5deb05e04af@ixit.cz> In-Reply-To: <20250913-nt35596s-v6-0-b5deb05e04af@ixit.cz> To: Sumit Semwal , Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Molly Sophia , Arnaud Ferraris , David Heidelberg X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10371; i=david@ixit.cz; h=from:subject:message-id; bh=j3PCObGJSVW2oB63WGDlOgJWuhYG0NWr/z6v3GHZ1/E=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBoxcPWN7CVdvMB7k67qfNaP0KyT7VfdY1JLHKQf sR6fq/GpWqJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaMXD1gAKCRBgAj/E00kg crvED/0dqAaaPQ0YcGik9l9+NnouQr1RpWV95zWl+Sosre7TCekGyMzttRKIgkEO0kfNnCROG4m ExfD4AELHndHtrFtbZfS8ZNwtJCp71LDiscAtha/3kD/au/VVx+JCxVTc1SpOO3kppJdWMBzaAz u0xANFdyTTSDfN3vKYbHipHd5pKv8cfVGTX+sTJmQI3k2KN8AjqrHvdQJUZuJAL0WrbjgEBhBKu bKrlrp3EiT9x+puYIl2R0SLEhcB75ANIhpjq8U+9YUYJ8Vu/d2ej0NvEbblv5sqt/GXY9r1GiOJ hIjHoVuYbv9AEDlVTJBF5XuYFFdYu8gXpVenzKuKLlIzLyF9oEaCIeOkOcOqrJrWd5qMrqGA7I/ Bl3dQQXeWh4PAsd/RV+5D+eP3j+4HFvNBOgV2xPBQZ/CQ56FUy9HOw8UKaKx3ajYFPMBeEjkIkw QPMC+YkpqMtwDJ3mSyDV6lOvq+Y7tGC4eNKNKJFTpk/sVpVsTY5IAJQ2QD/CgqI29HoGhPH9B47 YQjMwHSrDi/vR0fEDn1wOZ6Hh7iNTA1RIOkD6ygI8KJ99DUM0B1gp/35XFOjOhMVn5blVGPw7qG OKdkz1Hb2Gj/cN3FMrliuQH73IF91BOwHlSbtCtOkJr5WHXEDnYx+sOTmhQJJpwcHrx5eM0jgEp ouofuOVyO0GXhWQ== X-Developer-Key: i=david@ixit.cz; a=openpgp; fpr=D77A09CFEEDC2BBD53A7047460023FC4D3492072 X-Endpoint-Received: by B4 Relay for david@ixit.cz/default with auth_id=355 X-Original-From: David Heidelberg Reply-To: david@ixit.cz From: Molly Sophia Novatek NT35596s is a generic DSI IC that drives command and video mode panels. Currently add support for the LCD panel from JDI connected with this IC, as found on Xiaomi Mi Mix 2S phones. Signed-off-by: Molly Sophia Signed-off-by: Arnaud Ferraris Signed-off-by: David Heidelberg --- drivers/gpu/drm/panel/Kconfig | 7 +- drivers/gpu/drm/panel/panel-novatek-nt36672a.c | 225 +++++++++++++++++++++= +++- 2 files changed, 222 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 407c5f6a268b2ec66e5d0eddae26b3368e4cb2cb..dd2ea9f87292a5a99ae91b14b3f= 0d197c4db944f 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -521,14 +521,15 @@ config DRM_PANEL_NOVATEK_NT36523 Boe panels used in Xiaomi Mi Pad 5 and 5 Pro tablets. =20 config DRM_PANEL_NOVATEK_NT36672A - tristate "Novatek NT36672A DSI panel" + tristate "Novatek NT36672A/NT35596S DSI panel" depends on OF depends on DRM_MIPI_DSI depends on BACKLIGHT_CLASS_DEVICE help Say Y here if you want to enable support for the panels built - around the Novatek NT36672A display controller, such as some - Tianma panels used in a few Xiaomi Poco F1 mobile phones. + around the Novatek NT36672A or NT35596S display controller, such + as some Tianma panels used in a few Xiaomi Poco F1 mobile phones + or the JDI panels used in Xiaomi Mi Mix2S mobile phones. =20 config DRM_PANEL_NOVATEK_NT36672E tristate "Novatek NT36672E DSI panel" diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c b/drivers/gpu/d= rm/panel/panel-novatek-nt36672a.c index f7518ec469176a4e2d4f2b03f8e77f03511a12a7..a0271ca5feeb125a9d57b3b1ac4= 7a7933cf06226 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36672a.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672a.c @@ -3,13 +3,16 @@ * Copyright (C) 2020 Linaro Ltd * Author: Sumit Semwal * - * This driver is for the DSI interface to panels using the NT36672A displ= ay driver IC - * from Novatek. - * Currently supported are the Tianma FHD+ panels found in some Xiaomi pho= nes, including - * some variants of the Poco F1 phone. + * Copyright (C) 2022 Molly Sophia * - * Panels using the Novatek NT37762A IC should add appropriate configurati= on per-panel and - * use this driver. + * This driver is for the DSI interface to panels using the NT36672A/NT355= 96S + * display driver IC from Novatek. + * Currently supported are the Tianma FHD+ panels found in some Xiaomi pho= nes, + * including some variants of the Poco F1 phone, and the JDI FHD+ panels f= ound + * in Xiaomi Mi Mix 2S phones. + * + * Panels using the Novatek NT37762A or NT35596S IC should add appropriate + * configuration per-panel and use this driver. */ =20 #include @@ -591,6 +594,212 @@ static const struct nt36672a_panel_desc tianma_fhd_vi= deo_panel_desc =3D { .num_off_cmds =3D ARRAY_SIZE(tianma_fhd_video_off_cmds), }; =20 +static const struct nt36672a_panel_cmd jdi_nt35596s_video_on_cmds[] =3D { + { .data =3D { 0xff, 0x24 } }, + { .data =3D { 0x9d, 0x34 } }, + { .data =3D { 0xfb, 0x01 } }, + { .data =3D { 0xc4, 0x25 } }, + { .data =3D { 0xd1, 0x08 } }, + { .data =3D { 0xd2, 0x84 } }, + { .data =3D { 0xff, 0x26 } }, + { .data =3D { 0xfb, 0x01 } }, + { .data =3D { 0x03, 0x1c } }, + { .data =3D { 0x3b, 0x08 } }, + { .data =3D { 0x6b, 0x08 } }, + { .data =3D { 0x97, 0x08 } }, + { .data =3D { 0xc5, 0x08 } }, + { .data =3D { 0xfb, 0x01 } }, + { .data =3D { 0xff, 0x23 } }, + { .data =3D { 0xfb, 0x01 } }, + { .data =3D { 0x01, 0x84 } }, + { .data =3D { 0x05, 0x2d } }, + { .data =3D { 0x06, 0x00 } }, + { .data =3D { 0x33, 0x07 } }, + { .data =3D { 0x21, 0xee } }, + { .data =3D { 0x22, 0xed } }, + { .data =3D { 0x23, 0xea } }, + { .data =3D { 0x24, 0xe8 } }, + { .data =3D { 0x25, 0xe5 } }, + { .data =3D { 0x26, 0xe2 } }, + { .data =3D { 0x27, 0xde } }, + { .data =3D { 0x28, 0xbb } }, + { .data =3D { 0x29, 0x87 } }, + { .data =3D { 0x2a, 0x77 } }, + { .data =3D { 0x32, 0x0c } }, + { .data =3D { 0x13, 0x3f } }, + { .data =3D { 0x14, 0x34 } }, + { .data =3D { 0x15, 0x2a } }, + { .data =3D { 0x16, 0x25 } }, + { .data =3D { 0x17, 0x9d } }, + { .data =3D { 0x18, 0x9a } }, + { .data =3D { 0x19, 0x97 } }, + { .data =3D { 0x1a, 0x94 } }, + { .data =3D { 0x1b, 0x91 } }, + { .data =3D { 0x1c, 0x8e } }, + { .data =3D { 0x1d, 0x8b } }, + { .data =3D { 0x1e, 0x89 } }, + { .data =3D { 0x1f, 0x86 } }, + { .data =3D { 0x20, 0x83 } }, + { .data =3D { 0xff, 0x22 } }, + { .data =3D { 0x00, 0x0a } }, + { .data =3D { 0x01, 0x43 } }, + { .data =3D { 0x02, 0x5b } }, + { .data =3D { 0x03, 0x6a } }, + { .data =3D { 0x04, 0x7a } }, + { .data =3D { 0x05, 0x82 } }, + { .data =3D { 0x06, 0x85 } }, + { .data =3D { 0x07, 0x80 } }, + { .data =3D { 0x08, 0x7c } }, + { .data =3D { 0x09, 0x7c } }, + { .data =3D { 0x0a, 0x74 } }, + { .data =3D { 0x0b, 0x71 } }, + { .data =3D { 0x0c, 0x6e } }, + { .data =3D { 0x0d, 0x68 } }, + { .data =3D { 0x0e, 0x65 } }, + { .data =3D { 0x0f, 0x5c } }, + { .data =3D { 0x10, 0x32 } }, + { .data =3D { 0x11, 0x18 } }, + { .data =3D { 0x12, 0x00 } }, + { .data =3D { 0x13, 0x00 } }, + { .data =3D { 0x1a, 0x00 } }, + { .data =3D { 0x1b, 0x00 } }, + { .data =3D { 0x1c, 0x00 } }, + { .data =3D { 0x1d, 0x00 } }, + { .data =3D { 0x1e, 0x00 } }, + { .data =3D { 0x1f, 0x00 } }, + { .data =3D { 0x20, 0x00 } }, + { .data =3D { 0x21, 0x00 } }, + { .data =3D { 0x22, 0x00 } }, + { .data =3D { 0x23, 0x00 } }, + { .data =3D { 0x24, 0x00 } }, + { .data =3D { 0x25, 0x00 } }, + { .data =3D { 0x26, 0x00 } }, + { .data =3D { 0x27, 0x00 } }, + { .data =3D { 0x28, 0x00 } }, + { .data =3D { 0x29, 0x00 } }, + { .data =3D { 0x2a, 0x00 } }, + { .data =3D { 0x2b, 0x00 } }, + { .data =3D { 0x2f, 0x00 } }, + { .data =3D { 0x30, 0x00 } }, + { .data =3D { 0x31, 0x00 } }, + { .data =3D { 0x32, 0x0c } }, + { .data =3D { 0x33, 0x0c } }, + { .data =3D { 0x34, 0x0c } }, + { .data =3D { 0x35, 0x0b } }, + { .data =3D { 0x36, 0x09 } }, + { .data =3D { 0x37, 0x09 } }, + { .data =3D { 0x38, 0x08 } }, + { .data =3D { 0x39, 0x05 } }, + { .data =3D { 0x3a, 0x03 } }, + { .data =3D { 0x3b, 0x00 } }, + { .data =3D { 0x3f, 0x00 } }, + { .data =3D { 0x40, 0x00 } }, + { .data =3D { 0x41, 0x00 } }, + { .data =3D { 0x42, 0x00 } }, + { .data =3D { 0x43, 0x00 } }, + { .data =3D { 0x44, 0x00 } }, + { .data =3D { 0x45, 0x00 } }, + { .data =3D { 0x46, 0x00 } }, + { .data =3D { 0x47, 0x00 } }, + { .data =3D { 0x48, 0x00 } }, + { .data =3D { 0x49, 0x03 } }, + { .data =3D { 0x4a, 0x06 } }, + { .data =3D { 0x4b, 0x07 } }, + { .data =3D { 0x4c, 0x07 } }, + { .data =3D { 0x53, 0x01 } }, + { .data =3D { 0x54, 0x01 } }, + { .data =3D { 0x55, 0x89 } }, + { .data =3D { 0x56, 0x00 } }, + { .data =3D { 0x58, 0x00 } }, + { .data =3D { 0x68, 0x00 } }, + { .data =3D { 0x84, 0xff } }, + { .data =3D { 0x85, 0xff } }, + { .data =3D { 0x86, 0x03 } }, + { .data =3D { 0x87, 0x00 } }, + { .data =3D { 0x88, 0x00 } }, + { .data =3D { 0xa2, 0x20 } }, + { .data =3D { 0xa9, 0x01 } }, + { .data =3D { 0xaa, 0x12 } }, + { .data =3D { 0xab, 0x13 } }, + { .data =3D { 0xac, 0x0a } }, + { .data =3D { 0xad, 0x74 } }, + { .data =3D { 0xaf, 0x33 } }, + { .data =3D { 0xb0, 0x03 } }, + { .data =3D { 0xb1, 0x14 } }, + { .data =3D { 0xb2, 0x42 } }, + { .data =3D { 0xb3, 0x40 } }, + { .data =3D { 0xb4, 0xa5 } }, + { .data =3D { 0xb6, 0x44 } }, + { .data =3D { 0xb7, 0x04 } }, + { .data =3D { 0xb8, 0x14 } }, + { .data =3D { 0xb9, 0x42 } }, + { .data =3D { 0xba, 0x40 } }, + { .data =3D { 0xbb, 0xa5 } }, + { .data =3D { 0xbd, 0x44 } }, + { .data =3D { 0xbe, 0x04 } }, + { .data =3D { 0xbf, 0x00 } }, + { .data =3D { 0xc0, 0x75 } }, + { .data =3D { 0xc1, 0x6a } }, + { .data =3D { 0xc2, 0xa5 } }, + { .data =3D { 0xc4, 0x22 } }, + { .data =3D { 0xc5, 0x02 } }, + { .data =3D { 0xc6, 0x00 } }, + { .data =3D { 0xc7, 0x95 } }, + { .data =3D { 0xc8, 0x8a } }, + { .data =3D { 0xc9, 0xa5 } }, + { .data =3D { 0xcb, 0x22 } }, + { .data =3D { 0xcc, 0x02 } }, + { .data =3D { 0xcd, 0x00 } }, + { .data =3D { 0xce, 0xb5 } }, + { .data =3D { 0xcf, 0xaa } }, + { .data =3D { 0xd0, 0xa5 } }, + { .data =3D { 0xd2, 0x22 } }, + { .data =3D { 0xd3, 0x02 } }, + { .data =3D { 0xfb, 0x01 } }, + { .data =3D { 0xff, 0x10 } }, + { .data =3D { 0x26, 0x02 } }, + { .data =3D { 0x35, 0x00 } }, + { .data =3D { 0x51, 0xff } }, + { .data =3D { 0x53, 0x24 } }, + { .data =3D { 0x55, 0x00 } }, + { .data =3D { 0xb0, 0x00 } }, +}; + +static const struct drm_display_mode jdi_nt35596s_video_panel_mode =3D { + .clock =3D (1080 + 16 + 28 + 40) * (2160 + 7 + 4 + 24) * 60 / 1000, + + .hdisplay =3D 1080, + .hsync_start =3D 1080 + 16, + .hsync_end =3D 1080 + 16 + 28, + .htotal =3D 1080 + 16 + 28 + 40, + + .vdisplay =3D 2160, + .vsync_start =3D 2160 + 7, + .vsync_end =3D 2160 + 7 + 4, + .vtotal =3D 2160 + 7 + 4 + 24, + + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct nt36672a_panel_desc jdi_nt35596s_video_panel_desc =3D { + .display_mode =3D &jdi_nt35596s_video_panel_mode, + + .width_mm =3D 68, + .height_mm =3D 136, + + .mode_flags =3D MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_CLOCK_NON_CONTINUOUS | + MIPI_DSI_MODE_VIDEO_BURST, + .format =3D MIPI_DSI_FMT_RGB888, + .lanes =3D 4, + .on_cmds_1 =3D jdi_nt35596s_video_on_cmds, + .num_on_cmds_1 =3D ARRAY_SIZE(jdi_nt35596s_video_on_cmds), + .on_cmds_2 =3D NULL, + .num_on_cmds_2 =3D 0, + .off_cmds =3D NULL, + .num_off_cmds =3D 0, +}; + static int nt36672a_panel_add(struct nt36672a_panel *pinfo) { struct device *dev =3D &pinfo->link->dev; @@ -668,6 +877,7 @@ static void nt36672a_panel_remove(struct mipi_dsi_devic= e *dsi) =20 static const struct of_device_id tianma_fhd_video_of_match[] =3D { { .compatible =3D "tianma,fhd-video", .data =3D &tianma_fhd_video_panel_d= esc }, + { .compatible =3D "jdi,fhd-nt35596s", .data =3D &jdi_nt35596s_video_panel= _desc }, { }, }; MODULE_DEVICE_TABLE(of, tianma_fhd_video_of_match); @@ -683,5 +893,6 @@ static struct mipi_dsi_driver nt36672a_panel_driver =3D= { module_mipi_dsi_driver(nt36672a_panel_driver); =20 MODULE_AUTHOR("Sumit Semwal "); -MODULE_DESCRIPTION("NOVATEK NT36672A based MIPI-DSI LCD panel driver"); +MODULE_AUTHOR("Molly Sophia "); +MODULE_DESCRIPTION("NOVATEK NT36672A/NT35596S based MIPI-DSI LCD panel dri= ver"); MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 17:00:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0711E23D7E7; Sat, 13 Sep 2025 19:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757791192; cv=none; b=qqdmWUXoohetHFQvfgsKg+9IRq9AJ/EtRrrsiYB5HcOq2/mN4No348lIqbGBXdafdbI48NgOtLLelCIvvMAsE2UWjhLZBJhksNDEc+yy6yiGx4X0292cq8cLRHHgO1CmmKSer61QQCu+AiE+g9TF7J3WMkMWr+adr6+L0uehI5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757791192; c=relaxed/simple; bh=GqkoZ7KBwzs7dRpuLzIvS/Z61jcctzBt4EJ6Zi6zhmc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: 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Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Molly Sophia , Arnaud Ferraris , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1713; i=david@ixit.cz; h=from:subject:message-id; bh=lFoP3Jmjexe60vWrVFSdH2SLqrIeKo/VFBht7BKKVLc=; b=owEBbQKS/ZANAwAIAWACP8TTSSByAcsmYgBoxcPWenKVF1BK8oEurKoF2JGZ9fs17xjEBq+ad nLmW22lVKGJAjMEAAEIAB0WIQTXegnP7twrvVOnBHRgAj/E00kgcgUCaMXD1gAKCRBgAj/E00kg ckPSD/0apPokMVlQ7NkcKcqNNKRt7eEHs4tDWTXJIK7FXwLs0StRKtIg70lfdXdy3JCMhEOogEM OMZXA3Cyts0ez2Jg392TkgFk6P7Xaux4ia8v/1LzS/ckjqNRgQtbdHiAlXkCtcm0PnO+mTlUBUX PQPuJx8kSnYnKv4TDWRKKj1KpV2ACOPAYaaaY9wC60D6EgIrq6Qt/97jZPNRptlZpjNLmGD8B0f hn+U1OAGucge0s1O/z/xMyFpEwL8P5T26vfykwxuzmaaGw3qFNELC+WPmiH80ZljZtzHTy3UGi+ 4sWruE8Y5JO2xrLCzSKffjyJ1ciBageAJudf8bC6MUsTkojpnnY0hhKuNAynL6Z0LltT7iZe/S4 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Signed-off-by: Molly Sophia Signed-off-by: Arnaud Ferraris Acked-by: Krzysztof Kozlowski --- .../bindings/display/panel/novatek,nt36672a.yaml | 21 ++++++++++++++---= ---- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt3667= 2a.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.= yaml index 800a2f0a4dad98954ef60c3bb04d8eb2243cae7a..d7036ab46382f7b6200cc263ba7= e93856386919f 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml @@ -20,14 +20,21 @@ allOf: =20 properties: compatible: - items: - - enum: - - tianma,fhd-video - - const: novatek,nt36672a + oneOf: + - items: + - enum: + - jdi,fhd-nt35596s + - const: novatek,nt35596s + + - items: + - enum: + - tianma,fhd-video + - const: novatek,nt36672a + description: This indicates the panel manufacturer of the panel that is - in turn using the NT36672A panel driver. This compatible string - determines how the NT36672A panel driver is configured for the indic= ated - panel. The novatek,nt36672a compatible shall always be provided as a= fallback. + in turn using the NT36672A or the NT35596S panel driver. This compat= ible + string determines how the panel driver is configured for the indicat= ed + panel. =20 reg: maxItems: 1 --=20 2.51.0