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charset="utf-8" From: Nihal Kumar Gupta Add device tree bindings for the CCI controller on the Qualcomm QCS8300 SoC. Introduce the "qcom,qcs8300-cci" compatible string. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Bryan O'Donoghue --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 1687b069e032..edd2e77d717b 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,7 @@ properties: =20 - items: - enum: + - qcom,qcs8300-cci - qcom,sc7280-cci - qcom,sc8280xp-cci - qcom,sdm670-cci @@ -223,6 +224,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-cci - qcom,sm8550-cci - qcom,sm8650-cci - qcom,x1e80100-cci --=20 2.25.1 From nobody Thu Oct 2 18:21:35 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EED4E30F7F7; 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charset="utf-8" From: Nihal Kumar Gupta Add support for three Camera Control Interface (CCI) controllers on the Qualcomm QCS8300 SoC. Configure clocks, power domains, pinctrl states and two I2C buses (i2c0, i2c1) with 1 MHz frequency. Nodes are added in a disabled state by default. Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 309 ++++++++++++++++++++++++++ 1 file changed, 309 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index a248e269d72d..a69719e291ea 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4681,6 +4681,123 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac13000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac13000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_i2c0_default &cci0_i2c1_default>; + pinctrl-1 =3D <&cci0_i2c0_sleep &cci0_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac14000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac14000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_i2c0_default &cci1_i2c1_default>; + pinctrl-1 =3D <&cci1_i2c0_sleep &cci1_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci2_i2c0_default &cci2_i2c1_default>; + pinctrl-1 =3D <&cci2_i2c0_sleep &cci2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ac78000 { compatible =3D "qcom,qcs8300-camss"; =20 @@ -4975,6 +5092,198 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cci0_i2c0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_i2c0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_i2c1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_i2c1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_i2c0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_i2c1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_i2c0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_i2c0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_i2c1_default: cci2-1-default-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_i2c1_sleep: cci2-1-sleep-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; function =3D "hs0_mi2s"; --=20 2.25.1 From nobody Thu Oct 2 18:21:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 607473164CA; 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charset="utf-8" From: Nihal Kumar Gupta Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/monaco-evk-camera-imx577.dtso | 96 +++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5b52f9e4e5f3..1c32c54ed841 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs :=3D monaco-evk.dtb monaco-evk-camera-imx577= .dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-camera-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/= arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 000000000000..2237f0fc4a14 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam1_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 74 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + clock-lanes =3D <7>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 =3D <&cci1_i2c0_default>; + pinctrl-1 =3D <&cci1_i2c0_sleep>; + + status =3D "okay"; +}; + +&cci1_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam1_default>; + pinctrl-names =3D "default"; + + clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + avdd-supply =3D <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + clock-lanes =3D <7>; + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins =3D "gpio68"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + ldo-avdd-pins { + pins =3D "gpio74"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.25.1