From nobody Thu Oct 2 18:15:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91FCF30FF37 for ; Fri, 12 Sep 2025 13:14:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682862; cv=none; b=FtbjjfgmErMQIG0nTnXFX4HlrygfAk11xzX+L5OxO1OAELa64PQAx7q6/yN1P/OKEZfmy3od/v+30RYCuLbswKesTpt38QP5BKWToALKjIhCESAyHWcm25O9W1adU2bIh6UQ0hxErLbRS24kLsJb9kNFZc3x44qx4BUgjHj0zkw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682862; c=relaxed/simple; bh=sMRpYWfL2QXkyxeUkmqjU+F4i4TUrlhjQ0pljHjIbto=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ee9hyRBamXcS3zC4CQWRGd0BD3FOU/DHDxYZKN+IFIJ+c56TJRc1HQsJuFv+aeCR75fCyy+RS1bsDmrksSB1HQq8Zf0VZjxyGjtdlWPJIyFPmcM6ZYl7FZuyAYhI4nDGjbbPb3suUbyUgjXxOOOk+TifqNW3oIDk6ApwEOwrIX0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RG8Q2ps8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RG8Q2ps8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CACB3C4CEF4; Fri, 12 Sep 2025 13:14:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757682861; bh=sMRpYWfL2QXkyxeUkmqjU+F4i4TUrlhjQ0pljHjIbto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RG8Q2ps8m5l+jmHpCj2pwjEKjkw3pA/gj8dK3aTvtr3N+AI/Usby5OSzX1q+2jLfn i8fIvuuwOcVX/AbeVPgAcAMrlhJ9anN3ubzrtlx30LQriLPJO7EovC6Wcs0em3X4Mq 0DPZQbgr6TbzFOLT9/PGxorAN8AnRnZaDGNadUNWrI5N79HRf6GXleAM5UgWKDeeWp WOHzImqjStXNkMPr4YtZtCznsd/iXsHZf2jnkaXUZ11slCvvJu2yAYPKtZVTfxeTj0 zxLPKrc3lEZ9MOvr6ZoNdgrSh+HxfbaqLGsAiYVfBgts1ouRQf93iZhQpfBxvPcxy6 ZuHYcBCtB8Zqg== From: srini@kernel.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Ciprian Costea , Dan Carpenter , "Rob Herring (Arm)" , Srinivas Kandagatla Subject: [PATCH 1/5] dt-bindings: nvmem: Add the nxp,s32g-ocotp yaml file Date: Fri, 12 Sep 2025 14:14:11 +0100 Message-ID: <20250912131415.303407-2-srini@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250912131415.303407-1-srini@kernel.org> References: <20250912131415.303407-1-srini@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ciprian Costea Add bindings to expose the On Chip One-Time Programmable Controller (OCOTP) for the NXP s32g chipset. There are three versions of this chip but they're compatible so we can fall back to the nxp,s32g2-ocotp compatible. Signed-off-by: Ciprian Costea Signed-off-by: Dan Carpenter Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-= nvmem.yaml diff --git a/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.y= aml b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml new file mode 100644 index 000000000000..8d46e7d28da6 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/nxp,s32g-ocotp-nvmem.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/nxp,s32g-ocotp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G OCOTP NVMEM driver + +maintainers: + - Ciprian Costea + +description: + The drivers provides an interface to access One Time + Programmable memory pages, such as TMU fuse values. + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-ocotp + - items: + - enum: + - nxp,s32g3-ocotp + - nxp,s32r45-ocotp + - const: nxp,s32g2-ocotp + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: nvmem.yaml# + +examples: + - | + nvmem@400a4000 { + compatible =3D "nxp,s32g2-ocotp"; + reg =3D <0x400a4000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; --=20 2.50.0 From nobody Thu Oct 2 18:15:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC2DB30EF6F for ; Fri, 12 Sep 2025 13:14:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682862; cv=none; b=AHpvme6V32spXueyS5XGJO2S//IzsLSiub3o8mAnsITGTQWF89q0NlzL27GG2YnhD/4xW0MO+PLK+xNeY9TJ9TTtAFhJKfqO+S8xEL6M4O1t+a/45kPThNr/46m3gEi+JSvOBsMMbV5n+iBA7V81ziqkX6gX7Q8NWOHr9mX1ZEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682862; c=relaxed/simple; bh=dtE14Fa4wJ/Kt4AIRcRYWLc08n/p9dqAZ4JSBaWkMjc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=At6k89QpJuk1/UQfeqSnIKP/4uHQfi5hvKoUHXSfHPEvJR29lVy8FRG+K69fU4Cxl4aYPJPqSfp87MRaL4yook+xALZVy+AqqZKFZx0C1AdC/8VPi1vSx9RgfUXJiv3Bnn0j3ydIQhtu7zG9K0YdisqAN4uuov5VKa2jEgpvFAU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UEo4wIyd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UEo4wIyd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 675E8C4CEF9; Fri, 12 Sep 2025 13:14:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757682862; bh=dtE14Fa4wJ/Kt4AIRcRYWLc08n/p9dqAZ4JSBaWkMjc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UEo4wIydRzv6eaGFG3LrIurIEihRq6u0haUjxC/+EEekRSOUZciJSZ5drdVXfNXgy MHqS0S7rrFBFeU0LZeF8SzdodMnhGEvDaQ3OBaCm2is7/x6aUySlphM4cTNJPlzvIw pwlxhautlaiqMYPDYCSbiivS9KABTEyC0/ynLKVcGWnnrzjbHx351rFI/U+UGF3Lpm ldvKJqX1lXHS+Mht4sOwVV4HiqzbEEP1dePGofMjvFAe8HWAorCn42uKsslSR6C+NL 5jEKgL3PAbE/e6u5yTDA8s2W0fPn7Xvke6pIFR1vVSOPbTIn60BAzh1NoTRYSzaqYS aTzbl/vIZBmFQ== From: srini@kernel.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Ciprian Costea , Ghennadi Procopciuc , Larisa Grigore , Dan Carpenter , Srinivas Kandagatla Subject: [PATCH 2/5] nvmem: s32g-ocotp: Add driver for S32G OCOTP Date: Fri, 12 Sep 2025 14:14:12 +0100 Message-ID: <20250912131415.303407-3-srini@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250912131415.303407-1-srini@kernel.org> References: <20250912131415.303407-1-srini@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ciprian Costea Provide access to the On Chip One-Time Programmable Controller (OCOTP) pages on the NXP S32G platform. Signed-off-by: Ciprian Costea Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Signed-off-by: Dan Carpenter Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 10 ++++ drivers/nvmem/Makefile | 2 + drivers/nvmem/s32g-ocotp-nvmem.c | 100 +++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 drivers/nvmem/s32g-ocotp-nvmem.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index edd811444ce5..f3b8ffa77528 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -240,6 +240,16 @@ config NVMEM_NINTENDO_OTP This driver can also be built as a module. If so, the module will be called nvmem-nintendo-otp. =20 +config NVMEM_S32G_OCOTP + tristate "S32G SoC OCOTP support" + depends on ARCH_S32 + help + This is a driver for the 'OCOTP' peripheral available on S32G + platforms. + + If you say Y here, you will get support for the One Time + Programmable memory pages. + config NVMEM_QCOM_QFPROM tristate "QCOM QFPROM Support" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 2021d59688db..5634945f8196 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -79,6 +79,8 @@ obj-$(CONFIG_NVMEM_SUNPLUS_OCOTP) +=3D nvmem_sunplus_ocot= p.o nvmem_sunplus_ocotp-y :=3D sunplus-ocotp.o obj-$(CONFIG_NVMEM_SUNXI_SID) +=3D nvmem_sunxi_sid.o nvmem_sunxi_sid-y :=3D sunxi_sid.o +obj-$(CONFIG_NVMEM_S32G_OCOTP) +=3D nvmem-s32g-ocotp-nvmem.o +nvmem-s32g-ocotp-nvmem-y :=3D s32g-ocotp-nvmem.o obj-$(CONFIG_NVMEM_U_BOOT_ENV) +=3D nvmem_u-boot-env.o nvmem_u-boot-env-y :=3D u-boot-env.o obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) +=3D nvmem-uniphier-efuse.o diff --git a/drivers/nvmem/s32g-ocotp-nvmem.c b/drivers/nvmem/s32g-ocotp-nv= mem.c new file mode 100644 index 000000000000..119871ab3a94 --- /dev/null +++ b/drivers/nvmem/s32g-ocotp-nvmem.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +struct s32g_ocotp_priv { + struct device *dev; + void __iomem *base; +}; + +static int s32g_ocotp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct s32g_ocotp_priv *s32g_data =3D context; + u32 *dst =3D val; + + while (bytes >=3D sizeof(u32)) { + *dst++ =3D ioread32(s32g_data->base + offset); + + bytes -=3D sizeof(u32); + offset +=3D sizeof(u32); + } + + return 0; +} + +static struct nvmem_keepout s32g_keepouts[] =3D { + { .start =3D 0, .end =3D 520 }, + { .start =3D 540, .end =3D 564 }, + { .start =3D 596, .end =3D 664 }, + { .start =3D 668, .end =3D 676 }, + { .start =3D 684, .end =3D 732 }, + { .start =3D 744, .end =3D 864 }, + { .start =3D 908, .end =3D 924 }, + { .start =3D 928, .end =3D 936 }, + { .start =3D 948, .end =3D 964 }, + { .start =3D 968, .end =3D 976 }, + { .start =3D 984, .end =3D 1012 }, +}; + +static struct nvmem_config s32g_ocotp_nvmem_config =3D { + .name =3D "s32g-ocotp", + .add_legacy_fixed_of_cells =3D true, + .read_only =3D true, + .word_size =3D 4, + .reg_read =3D s32g_ocotp_read, + .keepout =3D s32g_keepouts, + .nkeepout =3D ARRAY_SIZE(s32g_keepouts), +}; + +static const struct of_device_id ocotp_of_match[] =3D { + { .compatible =3D "nxp,s32g2-ocotp" }, + { /* sentinel */ } +}; + +static int s32g_ocotp_probe(struct platform_device *pdev) +{ + struct s32g_ocotp_priv *s32g_data; + struct device *dev =3D &pdev->dev; + struct nvmem_device *nvmem; + struct resource *res; + + s32g_data =3D devm_kzalloc(dev, sizeof(*s32g_data), GFP_KERNEL); + if (!s32g_data) + return -ENOMEM; + + s32g_data->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(s32g_data->base)) + return dev_err_probe(dev, PTR_ERR(s32g_data->base), + "Cannot map OCOTP device.\n"); + + s32g_data->dev =3D dev; + s32g_ocotp_nvmem_config.dev =3D dev; + s32g_ocotp_nvmem_config.priv =3D s32g_data; + s32g_ocotp_nvmem_config.size =3D resource_size(res); + + nvmem =3D devm_nvmem_register(dev, &s32g_ocotp_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static struct platform_driver s32g_ocotp_driver =3D { + .probe =3D s32g_ocotp_probe, + .driver =3D { + .name =3D "s32g-ocotp", + .of_match_table =3D ocotp_of_match, + }, +}; +module_platform_driver(s32g_ocotp_driver); +MODULE_AUTHOR("NXP"); +MODULE_DESCRIPTION("S32G OCOTP driver"); +MODULE_LICENSE("GPL"); --=20 2.50.0 From nobody Thu Oct 2 18:15:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2B4D3126D1 for ; Fri, 12 Sep 2025 13:14:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682864; cv=none; b=Ee6HIWD1/ZGXbV9g1nuLTS4QzzA9tuznPnQqGEIHNNGb6d0i5/h3E4CbgFjq6VFWwQcycS9H4of1Hjk72DQaPV/eE0zszdXjp/3nHXKs2ZJuMb5RMducSgirfQy2k+wQy7m9THvWqEGmTcYB/tRWfpqk79AIY7e818tw1SjdFQY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682864; c=relaxed/simple; bh=7tcgIQOfiYiITg2uIpeiX/xHBaG3Z0kgPGNyIDQAn7M=; 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charset="utf-8" From: Michael Walle The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/layouts/kontron,sl28-vpd.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-v= pd.yaml b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.= yaml index c713e23819f1..afd1919c6b1c 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml @@ -19,7 +19,12 @@ select: false =20 properties: compatible: - const: kontron,sl28-vpd + oneOf: + - items: + - enum: + - kontron,sa67-vpd + - const: kontron,sl28-vpd + - const: kontron,sl28-vpd =20 serial-number: type: object --=20 2.50.0 From nobody Thu Oct 2 18:15:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 082513128D4 for ; Fri, 12 Sep 2025 13:14:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682866; cv=none; b=hnCiKoMqyw3CdQTo/C50c2UxUq1rz5NLmNQrvJu2F8nFdNQNvTV7UuY+m1TbIOyLGVUlq8FPHA9bbG3/kZxu1V5LoPAsXou6WkLNotbPqrNhoKo2CHWfp/59Xc34iaRUBWWmX7e3ElJNSVHcfRgtXaR+ydHRdgtTw/s73nZZsTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757682866; c=relaxed/simple; bh=pkC7ern/uN8BEg2zJ6EAKz3XbhIClZBy4AFcKmwVBFc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GEhNgAQq81jDNMHH9GmXPU9F897VXuADuC1C+4d4Ytpj9ro1bo4Fra99U0vM9UK4jIzXEb+YcXTM9wLlyrJmFqqFY2atEY8mKo9TP/kE76+ukPhVZT+HHvHR/bioI2YzMvokawTNvGxq6F35fcKgnpgW0lzANcA/2G9Wn8wyP90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lBhOGBiF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lBhOGBiF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95EF6C4CEF4; Fri, 12 Sep 2025 13:14:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757682865; bh=pkC7ern/uN8BEg2zJ6EAKz3XbhIClZBy4AFcKmwVBFc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lBhOGBiFup7kX5OzCs2mMLhATqqkzww5s5ShL839g0VDEzZ6VZ+lxoEcv4A7NYXa9 v+78ZNKBVGvXL7512lK5Q5Sa41/iueRaopnHzGy6moWLh3s3KPR512VLXRJbwtMIWu 4h6Ue4Q2Jl5yi3c1gkHn4SHbEvAWZISL/p63YT/tQ9VIHv+fGZFnoCIZg1+apYEX4J OQZZjqhm4YcsEUki8AYDxp5X1GidjBqYhybFk2eITHbbfgChKrLM3dL4FMYfDbVnuV Qmd1szwcNY0YC9epIJBi2t0QJs+WEisgHIMuO3wuA7j9fO1i1V1O2JVGIhgPaudLGh KDmQI7rkgypFQ== From: srini@kernel.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Christian Marangi , "Rob Herring (Arm)" , Srinivas Kandagatla Subject: [PATCH 4/5] dt-bindings: nvmem: Document support for Airoha AN8855 Switch EFUSE Date: Fri, 12 Sep 2025 14:14:14 +0100 Message-ID: <20250912131415.303407-5-srini@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250912131415.303407-1-srini@kernel.org> References: <20250912131415.303407-1-srini@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christian Marangi Document support for Airoha AN8855 Switch EFUSE used to calibrate internal PHYs and store additional configuration info. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) Signed-off-by: Srinivas Kandagatla --- .../bindings/nvmem/airoha,an8855-efuse.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/airoha,an8855-e= fuse.yaml diff --git a/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.ya= ml b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml new file mode 100644 index 000000000000..9802d9ea2176 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/airoha,an8855-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8855 Switch EFUSE + +maintainers: + - Christian Marangi + +description: + Airoha AN8855 EFUSE used to calibrate internal PHYs and store additional + configuration info. + +$ref: nvmem.yaml# + +properties: + compatible: + const: airoha,an8855-efuse + + '#nvmem-cell-cells': + const: 0 + +required: + - compatible + - '#nvmem-cell-cells' + +unevaluatedProperties: false + +examples: + - | + efuse { + compatible =3D "airoha,an8855-efuse"; + + #nvmem-cell-cells =3D <0>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + shift_sel_port0_tx_a: shift-sel-port0-tx-a@c { + reg =3D <0xc 0x4>; + }; + + shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 { + reg =3D <0x10 0x4>; + }; + + shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 { + reg =3D <0x14 0x4>; + }; + + shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 { + reg =3D <0x18 0x4>; + }; + + shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c { + reg =3D <0x1c 0x4>; + }; + + shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 { + reg =3D <0x20 0x4>; + }; + + shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 { + reg =3D <0x24 0x4>; + }; + + shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 { + reg =3D <0x28 0x4>; + }; + + shift_sel_port2_tx_a: shift-sel-port2-tx-a@2c { + reg =3D <0x2c 0x4>; + }; + + shift_sel_port2_tx_b: shift-sel-port2-tx-b@30 { + reg =3D <0x30 0x4>; + }; + + shift_sel_port2_tx_c: shift-sel-port2-tx-c@34 { + reg =3D <0x34 0x4>; + }; + + shift_sel_port2_tx_d: shift-sel-port2-tx-d@38 { + reg =3D <0x38 0x4>; + }; + + shift_sel_port3_tx_a: shift-sel-port3-tx-a@4c { + reg =3D <0x4c 0x4>; + }; + + shift_sel_port3_tx_b: shift-sel-port3-tx-b@50 { + reg =3D <0x50 0x4>; + }; + + shift_sel_port3_tx_c: shift-sel-port3-tx-c@54 { + reg =3D <0x54 0x4>; + }; + + shift_sel_port3_tx_d: shift-sel-port3-tx-d@58 { + reg =3D <0x58 0x4>; + }; + + shift_sel_port4_tx_a: shift-sel-port4-tx-a@5c { + reg =3D <0x5c 0x4>; + }; + + shift_sel_port4_tx_b: shift-sel-port4-tx-b@60 { + reg =3D <0x60 0x4>; + }; + + shift_sel_port4_tx_c: shift-sel-port4-tx-c@64 { + reg =3D <0x64 0x4>; + }; + + shift_sel_port4_tx_d: shift-sel-port4-tx-d@68 { + reg =3D <0x68 0x4>; + }; + }; + }; --=20 2.50.0 From nobody Thu Oct 2 18:15:53 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59EBD3112C1 for ; Fri, 12 Sep 2025 13:14:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 12 Sep 2025 13:14:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757682866; bh=4jt0WH+ib9lMrNTRLeJ7mkZWBV7AKrfXxg/X9EzV/nY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aZgusYffgwKndLCNjm033DHZPfxGStzMCI1RSzh4XssDJMSpnL11eMGeoZBVO3XCT 2zyazLtQJAXCk5multFrJozbGP5lB9Aq4GCVNyN8dp4sNDx1djFMyUJUIPkj3fzGkp Y8NYNOTl40Sz+JLnUD4WOxrVGr6EUCfnQ3yXYqJSZk0Po1xTjGWUEIzRVtft1pE3SA a2cevqr41+O6v2+wQtyXnKTT8yAWxYgar8+k+sh4vUww0C0Tdf8f3Iv77wuT4bhWrJ UvkGWCRAudn8ttRJQ2k935mDvKZDeuCjK1hoK1D3Hp0ZvV2pa0onYQIckN1Oo45JFD lXVoOo1cQzLgw== From: srini@kernel.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Christian Marangi , Srinivas Kandagatla Subject: [PATCH 5/5] nvmem: an8855: Add support for Airoha AN8855 Switch EFUSE Date: Fri, 12 Sep 2025 14:14:15 +0100 Message-ID: <20250912131415.303407-6-srini@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250912131415.303407-1-srini@kernel.org> References: <20250912131415.303407-1-srini@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christian Marangi Add support for Airoha AN8855 Switch EFUSE. These EFUSE might be used for calibration data for the internal switch PHYs. Signed-off-by: Christian Marangi Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/Kconfig | 11 ++++++ drivers/nvmem/Makefile | 2 ++ drivers/nvmem/an8855-efuse.c | 68 ++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 drivers/nvmem/an8855-efuse.c diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index f3b8ffa77528..e0d88d3199c1 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -28,6 +28,17 @@ source "drivers/nvmem/layouts/Kconfig" =20 # Devices =20 +config NVMEM_AN8855_EFUSE + tristate "Airoha AN8855 eFuse support" + depends on MFD_AIROHA_AN8855 || COMPILE_TEST + help + Say y here to enable support for reading eFuses on Airoha AN8855 + Switch. These are e.g. used to store factory programmed + calibration data required for the PHY. + + This driver can also be built as a module. If so, the module will + be called nvmem-an8855-efuse. + config NVMEM_APPLE_EFUSES tristate "Apple eFuse support" depends on ARCH_APPLE || COMPILE_TEST diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index 5634945f8196..70a4464dcb1e 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -10,6 +10,8 @@ nvmem_layouts-y :=3D layouts.o obj-y +=3D layouts/ =20 # Devices +obj-$(CONFIG_NVMEM_AN8855_EFUSE) +=3D nvmem-an8855-efuse.o +nvmem-an8855-efuse-y :=3D an8855-efuse.o obj-$(CONFIG_NVMEM_APPLE_EFUSES) +=3D nvmem-apple-efuses.o nvmem-apple-efuses-y :=3D apple-efuses.o obj-$(CONFIG_NVMEM_APPLE_SPMI) +=3D apple_nvmem_spmi.o diff --git a/drivers/nvmem/an8855-efuse.c b/drivers/nvmem/an8855-efuse.c new file mode 100644 index 000000000000..d1afde6f623f --- /dev/null +++ b/drivers/nvmem/an8855-efuse.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Airoha AN8855 Switch EFUSE Driver + */ + +#include +#include +#include +#include +#include + +#define AN8855_EFUSE_CELL 50 + +#define AN8855_EFUSE_DATA0 0x1000a500 +#define AN8855_EFUSE_R50O GENMASK(30, 24) + +static int an8855_efuse_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct regmap *regmap =3D context; + + return regmap_bulk_read(regmap, AN8855_EFUSE_DATA0 + offset, + val, bytes / sizeof(u32)); +} + +static int an8855_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_config an8855_nvmem_config =3D { + .name =3D "an8855-efuse", + .size =3D AN8855_EFUSE_CELL * sizeof(u32), + .stride =3D sizeof(u32), + .word_size =3D sizeof(u32), + .reg_read =3D an8855_efuse_read, + }; + struct device *dev =3D &pdev->dev; + struct nvmem_device *nvmem; + struct regmap *regmap; + + /* Assign NVMEM priv to MFD regmap */ + regmap =3D dev_get_regmap(dev->parent, NULL); + if (!regmap) + return -ENOENT; + + an8855_nvmem_config.priv =3D regmap; + an8855_nvmem_config.dev =3D dev; + nvmem =3D devm_nvmem_register(dev, &an8855_nvmem_config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id an8855_efuse_of_match[] =3D { + { .compatible =3D "airoha,an8855-efuse", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, an8855_efuse_of_match); + +static struct platform_driver an8855_efuse_driver =3D { + .probe =3D an8855_efuse_probe, + .driver =3D { + .name =3D "an8855-efuse", + .of_match_table =3D an8855_efuse_of_match, + }, +}; +module_platform_driver(an8855_efuse_driver); + +MODULE_AUTHOR("Christian Marangi "); +MODULE_DESCRIPTION("Driver for AN8855 Switch EFUSE"); +MODULE_LICENSE("GPL"); --=20 2.50.0