From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEA653090D4; Fri, 12 Sep 2025 12:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678891; cv=none; b=n2HyaMe3RBdv8Q9y4ax//cYyHCd55F4B9UzRrXRzg1b2Kj8vgWgSiZtfnyAszuv/Bgk1zYRF6TJEeQcOmaQE/dx4LvADp/T5CLnyowvKYj3ZCQv+h98ynyPvErE/uISu7ohY3EuducbfDkO4R20eD0cf1eLkB/07XscM3IU2yv8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678891; c=relaxed/simple; bh=RUMJQPe0AYRmGCrjxRqp1GqAC9UdgedOdf0x5X2StKE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ibYliJwmuSCMK2E4TvAs6WtGEe+DIuzKWKo2S0GHMaKUL7WGQll45lfw3m8KNZnbxe35ecLW4ArK7y8qeEdFEzjt71hhDaA0frYG8sOAdBKCVrc4G8gnccExlL1vkRg2zq9M22S1dPjxof6V4+9Qb3NRtwNBiNh8agZv9oz2xIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=EZXtch7D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EZXtch7D" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0AEC0C4CEF7; Fri, 12 Sep 2025 12:08:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678890; bh=RUMJQPe0AYRmGCrjxRqp1GqAC9UdgedOdf0x5X2StKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EZXtch7DbphlH/t0FUjTLyGq9EMaAxNe+J1sx3DWDGZ9ubttXK5+YMTdgkyOI7KHH lvalM7RY65xJH05mFl0oD0St2juX5M0DJ1lutJmodklbXwvrpXjuz7YxZ+v+xTS5it D3v9y/TmzvsSSEujL8jedaXh23v2ojSxE/8BFASKOVwgUqcUxf8XgKWbvz2hLTisn5 inttQTmQLflz7CtiW1+H6lvBP91E3h5EinHJjtz9y05pMWhS2wVFfBdujugQoSLyu0 YSZA5DyXT/xfGxK3nh0uCHbVUpbVZkvlygc++lnmHC4SW8sG6hoidj00gVXtmL9IzV wwcY+ynyhvoIg== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis , Krzysztof Kozlowski Subject: [PATCH v2 1/7] dt-bindings: arm: ti: Add Kontron SMARC-sAM67 module Date: Fri, 12 Sep 2025 14:07:39 +0200 Message-Id: <20250912120745.2295115-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for the AM67 based Kontron SMARC-sAM67 module. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..af41f1541850 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -181,6 +181,7 @@ properties: items: - enum: - beagle,am67a-beagley-ai + - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s =20 --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC85B30648B; Fri, 12 Sep 2025 12:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678898; cv=none; b=L3Tcjum7mplSihuEfMGTxsijYDFNNKI8aB2Dz+NqCrpetWJt2aUvwAKv0LJY75waaEsIxIC30J/131rR2Jc0v8t4xk6RUXuxsfP5qPUfXfQpjfcuIZW3Ahw/elIHuKIu1LbAi6PO4LTWK5LeB+2L8zB/63c7r2dmc2XIsNJcKcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678898; c=relaxed/simple; bh=06h87KlWkV1Qdl8fM2aLPrnGF5NItjF1URPRbQmcu/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EX2N0HWaas9im1hbD/z4l79sFMpOLONGDUhSXUTkLz2ouxVwy5u6xF5ETZKG0IIDMkQ3Kxsv+3AA+AvJWtu6/bd09umPJu9w9C8+vMU3EXs18S7/bRHJoqva03VkLqWU3/jyScRsNAEX0meQdRYtUGyWCklnzoID1x1sXhGDTfU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V//8tx61; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V//8tx61" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1193AC4CEFA; Fri, 12 Sep 2025 12:08:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678894; bh=06h87KlWkV1Qdl8fM2aLPrnGF5NItjF1URPRbQmcu/I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V//8tx61ZUc+/50eULoGX5XwUqhDag5NjuiYO0FollJVZYf/Nw5EKE/1U7lE2eL0J R/VVRGWQ69KNy5sm64TdlY+RD3oNYCflvgtz2mmCtMhnq5i0OMdUzn12zMGJCLYSaq X66W1i4IEO3n1PFWtiiJqvNAHHfetXE+SBmoaIsW/WmQeGbBC3I38Z2jZg5jsbDZTx CDx6nms0XGniOtq6MSJV3vuXI9z4YjNt6JbPj/fohIILDqy+4A4CsfzNWpyojqzkjC lDi13wflcTW2iyVGZwacuU5tnZt2tK9lvgsti8MOhAkn6raJ87s3mYpSnfjqqSPmHm R3k2L8Xwoj2bQ== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis Subject: [PATCH v2 2/7] dt-bindings: mfd: tps6594: allow gpio-line-names Date: Fri, 12 Sep 2025 14:07:40 +0200 Message-Id: <20250912120745.2295115-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Setting the signal names in the device tree was already possible, but it will lead to a warning. Allow the gpio-line-names property to fix that. Signed-off-by: Michael Walle Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mfd/ti,tps6594.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Docume= ntation/devicetree/bindings/mfd/ti,tps6594.yaml index a48cb00afe43..ca17fbdea691 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -41,6 +41,7 @@ properties: system-power-controller: true =20 gpio-controller: true + gpio-line-names: true =20 '#gpio-cells': const: 2 --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8170D31D395; Fri, 12 Sep 2025 12:08:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678899; cv=none; b=Bs+dmb9XwBJ1M+GfKKbuk82kQPthmoUa0nRNU9ikXrrqiBkI8/xz+SzmRZT6MjIjdtcYrc7zkDBuv3BASGBitfCHJUCMlwimRMBC9spWauXYsIgmSx0ylgp25mWWD3tw6ShIYnNXfBHYqGfQdRfEEoIz+/weo/PD0VbgYlycYi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678899; c=relaxed/simple; bh=8kgki4o/54ZDhA5cisnpk/YP5jHL+lna07Q2A1oJF9M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ptZxn88Q1NrCpy5UbltojFayT8IhIe8S9SCOwrB88RsjdrTu59ArV2N4wUr5xDiQmV1/1B4Ck6q8AmHGCpv+xWMiqSkdvtF+iRbqSxxV7W+sBbBSb3PeK9Bi6itmvlphvw0yy6KWPnxoAjEk8v7kbEmh5HIBuvlHWSA8ZHUDU8g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tY9VnU/O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tY9VnU/O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DF6C6C4CEF1; Fri, 12 Sep 2025 12:08:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678899; bh=8kgki4o/54ZDhA5cisnpk/YP5jHL+lna07Q2A1oJF9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tY9VnU/OCiJDz8pKqp8avhOw8JkUXjPIXJd80vKHc0S+EVC1UlW2RJijCc3jZ7+nD RpIXqdThHa+RiZ/6x9OJrXqfAP88QqVsfRvkuM7CLXae4igD1fT568Gc3q1DKcHhUq +c9+ZepDsRDD/4o5css6sbGU2BRP0s3YLbZEglltyy6htq/MUf2ObRAf+pQacZAIe8 B8DLaGSeEUycnQGFhcS3SuYTwPnsq/bJ+65ZOKz0Za54KQnyIJslQbCFthVz964zNL X1zIxLKZn+zyONUJJEzDRX4X7ItzfiPaCLq54pUyv25tlJ6Ni/93PuHDkRJ+pKyD9n 7FsGvlwDRk2Xg== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis Subject: [PATCH v2 3/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 Date: Fri, 12 Sep 2025 14:07:41 +0200 Message-Id: <20250912120745.2295115-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree support for the Kontron SMARC-sAM67 module, which is based on a TI AM67A SoC. The module features: * Quad-core AM67A94 at 1.4GHz with 8 GiB RAM * 64 GiB eMMC, 4 MiB SPI flash for failsafe booting * Dedicated RTC * Multiple interfaces: 4x UART, 2x USB 2.0/USB 3.2, 2x GBE, QSPI, 7x I2C, * Display support: 2x LVDS, 1x DSI (*), 1x DP (*) * Camera support: 4x CSI (*) * Onboard microcontroller for boot control, failsafe booting and external watchdog (*) not yet supported by the kernel There is a base device tree and overlays which will add optional features. At the moment there is one full featured variant of that board whose device tree is generated during build by merging all the device tree overlays. Signed-off-by: Michael Walle --- arch/arm64/boot/dts/ti/Makefile | 6 + .../dts/ti/k3-am67a-kontron-sa67-base.dts | 1073 +++++++++++++++++ .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso | 26 + .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso | 31 + 4 files changed, 1136 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index aad9177930e6..7047d3421783 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,7 +133,13 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo =20 # Boards with J722s SoC +k3-am67a-kontron-sa67-dtbs :=3D k3-am67a-kontron-sa67-base.dtb \ + k3-am67a-kontron-sa67-rtc-rv8263.dtbo k3-am67a-kontron-sa67-gbe1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-base.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-gbe1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-rtc-rv8263.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/a= rm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts new file mode 100644 index 000000000000..5755df689752 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -0,0 +1,1073 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Kontron SMARC-sAM67 module + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-j722s.dtsi" +#include "k3-serdes.h" + +/ { + compatible =3D "kontron,sa67", "ti,j722s"; + model =3D "Kontron SMARC-sAM67"; + + aliases { + serial0 =3D &mcu_uart0; + serial1 =3D &main_uart0; + serial2 =3D &main_uart5; + serial3 =3D &wkup_uart0; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + rtc0 =3D &wkup_rtc0; + }; + + lcd0_backlight: backlight-1 { + compatible =3D "pwm-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd0_backlight_pins_default>; + pwms =3D <&epwm1 0 50000 0>; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + lcd1_backlight: backlight-2 { + compatible =3D "pwm-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd1_backlight_pins_default>; + pwms =3D <&epwm1 1 50000 0>; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&main_gpio1 18 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + connector-1 { + compatible =3D "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb0_connector_pins_default>; + type =3D "micro"; + id-gpios =3D <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + vbus-supply =3D <&vcc_usb0_vbus>; + + port { + usb0_connector: endpoint { + remote-endpoint =3D <&usb0_hc>; + }; + }; + + }; + + memory@80000000 { + /* Filled in by bootloader */ + reg =3D <0x00000000 0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000000 0x00000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x10000000>; + alignment =3D <0x2000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + }; + + vin_5p0: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V0_5V25_IN"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s5: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_S5"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_1p8_s5: regulator-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V8_S5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s0: regulator-4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_S0"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s5>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios =3D <&tps652g1 1 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_s0: regulator-5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "SDIO_PWR_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_sd_s0_pins_default>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_vio_s0: regulator-6 { + compatible =3D "regulator-gpio"; + regulator-name =3D "V_3V3_1V8_SD_S0"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_sd_vio_s0_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s0>; + regulator-boot-on; + enable-gpios =3D <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states =3D <3300000 0x0>, + <1800000 0x1>; + bootph-all; + }; + + vcc_3p3_cam_s0: regulator-7 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_CAM_S0"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_cam_s0_pins_default>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s5>; + enable-active-high; + interrupts-extended =3D <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; + bootph-all; + }; + + vcc_1p1_s0: regulator-8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V1_S0"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_1p1_s3>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + /* shared with V_0V75_0V85_CORE_S0 */ + gpios =3D <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_0p85_vcore_s0: regulator-9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_0V75_0V85_CORE_S0"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios =3D <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_lcd0_panel: regulator-10 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LCD0_VDD_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_lcd0_panel_pins_default>; + enable-active-high; + gpios =3D <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd1_panel: regulator-11 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LCD1_VDD_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_lcd1_panel_pins_default>; + enable-active-high; + gpios =3D <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vcc_usb0_vbus: regulator-12 { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB0_EN_OC#"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_usb0_vbus_pins_default>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpios =3D <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + }; +}; + +&audio_refclk0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_refclk0_pins_default>; + status =3D "disabled"; +}; + +&audio_refclk1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_refclk1_pins_default>; + status =3D "disabled"; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cpsw3g_pins_default>, <&rgmii1_pins_default>, + <&rgmii2_pins_default>; + status =3D "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cpsw3g_mdio_pins_default>; + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cpsw_port1 { + phy-connection-type =3D "rgmii-id"; + phy-handle =3D <&phy0>; + nvmem-cells =3D <&base_mac_address 0>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; +}; + +&main_gpio0 { + gpio-line-names =3D + "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", + "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", + "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", + "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", + "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", + "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", + "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", + "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", + "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", + "SLEEP#", "LID#"; + + bootph-all; + status =3D "okay"; +}; + +&main_gpio1 { + gpio-line-names =3D + "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", + "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", + "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", + "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", + "USB0_DRVVBUS", "USB1_DRVVBUS"; + + bootph-all; + status =3D "okay"; +}; + +/* I2C_LOCAL */ +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <100000>; + bootph-all; + status =3D "okay"; + + tps652g1: pmic@44 { + compatible =3D "ti,tps652g1"; + reg =3D <0x44>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", + "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupts-extended =3D <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; + + buck1-supply =3D <&vin_5p0>; + buck2-supply =3D <&vin_5p0>; + buck3-supply =3D <&vin_5p0>; + buck4-supply =3D <&vin_5p0>; + ldo1-supply =3D <&vin_5p0>; + ldo2-supply =3D <&vin_5p0>; + ldo3-supply =3D <&vin_5p0>; + + bootph-all; + + regulators { + vcc_0p85_s0: buck1 { + regulator-name =3D "V_0V85_S0"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p1_s3: buck2 { + regulator-name =3D "V_1V1_S3"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s0: buck3 { + regulator-name =3D "V_1V8_S0"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p2_s0: buck4 { + regulator-name =3D "V_1V2_S0"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_vda_pll_s0: ldo1 { + regulator-name =3D "V_1V8_VDA_PLL_S0"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s3: ldo2 { + regulator-name =3D "V_1V8_S3"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_ret_s5: ldo3 { + regulator-name =3D "V_1V8_RET_S5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rtc: rtc@51 { + compatible =3D "microcrystal,rv8263"; + reg =3D <0x51>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_pins_default>; + interrupts-extended =3D <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/* I2C_CAM */ +&main_i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c2_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c_mux_pins_default>; + + vdd-supply =3D <&vcc_1p8_s0>; + reset-gpios =3D <&main_gpio0 10 GPIO_ACTIVE_LOW>; + + i2c_cam0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c_cam1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + i2c_cam2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + i2c_cam3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; +}; + +/* I2C_LCD */ +&main_i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c3_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&main_pmx0 { + audio_refclk0_pins_default: audio-refclk0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK= 0 */ + >; + }; + + audio_refclk1_pins_default: audio-refclk1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 = */ + >; + }; + + cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + cpsw3g_pins_default: cpsw3g-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_C= OMP */ + >; + }; + + edp_bridge_pins_default: edp-bridge-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ + J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + i2c_mux_pins_default: i2c-mux-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ + >; + }; + + lcd0_backlight_pins_default: lcd0-backlight-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ + J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ + >; + }; + + lcd1_backlight_pins_default: lcd1-backlight-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ + J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ + J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ + J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ + J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ + >; + bootph-all; + }; + + main_uart5_pins_default: main-uart5-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ + J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ + J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ + J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ + >; + }; + + mcasp0_pins_default: mcasp0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ + J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ + J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ + J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ + >; + }; + + mcasp2_pins_default: mcasp2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ + J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ + J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ + J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ + >; + }; + + oldi0_pins_default: oldi0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ + J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ + J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ + J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ + J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ + J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ + J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ + J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ + J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ + J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ + >; + }; + + oldi1_pins_default: oldi1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ + J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ + J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ + J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ + J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ + J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ + J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ + J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ + J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ + J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ + J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ + J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + >; + bootph-all; + }; + + pcie0_rc_pins_default: pcie0-rc-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ + J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ + J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ + J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ + J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ + J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ + J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ + J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ + J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ + J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ + J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ + J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ + J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ + >; + }; + + rtc_pins_default: rtc-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ + >; + }; + + sdhci1_pins_default: sdhci1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ + >; + bootph-all; + }; + + usb0_connector_pins_default: usb0-connector-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ + >; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; + + vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ + >; + bootph-all; + }; + + vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ + >; + bootph-all; + }; + + vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ + >; + }; + + vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ + >; + }; + + vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ + >; + }; +}; + +/* SER1 */ +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* SER2 */ +&main_uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart5_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* I2S0 */ +&mcasp0 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp0_pins_default>; + op-mode =3D <0>; /* I2S */ + tdm-slots =3D <2>; + serial-dir =3D <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* I2S2 */ +&mcasp2 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp2_pins_default>; + op-mode =3D <0>; /* I2S */ + tdm-slots =3D <2>; + serial-dir =3D <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* CAN0 */ +&mcu_mcan0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + status =3D "okay"; +}; + +/* CAN1 */ +&mcu_mcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + status =3D "okay"; +}; + +&mcu_gpio0 { + gpio-line-names =3D + "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", + "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; +}; + +/* I2C_GP */ +&mcu_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_i2c0_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + + /* SMARC Module EEPROM */ + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + pagesize =3D <32>; + vcc-supply =3D <&vcc_1p8_s0>; + }; +}; + +&mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ + J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ + J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ + J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ + J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ + J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ + >; + bootph-all; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ + J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ + J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ + J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ + J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ + >; + }; +}; + +/* SPI0 */ +&mcu_spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_spi0_pins_default>; +}; + +/* SER0 */ +&mcu_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* QSPI0 */ +&ospi0 { + pinctrl-0 =3D <&ospi0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <104000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + m25p,fast-read; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <3>; + vcc-supply =3D <&vcc_1p8_s0>; + bootph-all; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + reg =3D <0x000000 0x400000>; + label =3D "failsafe bootloader"; + read-only; + }; + }; + + otp-1 { + compatible =3D "user-otp"; + + nvmem-layout { + compatible =3D "kontron,sa67-vpd", "kontron,sl28-vpd"; + + serial_number: serial-number { + }; + + base_mac_address: base-mac-address { + #nvmem-cell-cells =3D <1>; + }; + }; + }; + }; +}; + +&pcie0_rc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_rc_pins_default>; + + /* + * This is low active, but the driver itself is broken and already + * inverts the logic. + */ + reset-gpios =3D <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie>; + phy-names =3D "pcie-phy"; + status =3D "okay"; +}; + +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm =3D <50>; + status =3D "okay"; +}; + +/* SDIO */ +&sdhci1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdhci1_pins_default>; + vmmc-supply =3D <&vcc_3p3_sd_s0>; + vqmmc-supply =3D <&vcc_3p3_sd_vio_s0>; + bootph-all; + cd-gpios =3D <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms =3D <100>; + ti,fails-without-test-cd; + ti,driver-strength-ohm =3D <50>; + status =3D "okay"; +}; + +&serdes_ln_ctrl { + idle-states =3D , + ; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&serdes_wiz1 { + status =3D "okay"; +}; + +&serdes0 { + serdes0_usb3: phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + resets =3D <&serdes_wiz0 1>; + cdns,num-lanes =3D <1>; + cdns,phy-type =3D ; + }; +}; + +&serdes1 { + serdes1_pcie: phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + resets =3D <&serdes_wiz1 1>; + cdns,num-lanes =3D <1>; + cdns,phy-type =3D ; + }; +}; + +&usb0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "peripheral"; + status =3D "okay"; + + port { + usb0_hc: endpoint { + remote-endpoint =3D <&usb0_connector>; + }; + }; +}; + +&usb1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb1_pins_default>; + + dr_mode =3D "host"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb3>; + phy-names =3D "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; + status =3D "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status =3D "okay"; +}; + +/* I2C_PM */ +&wkup_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_i2c0_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +/* SER3 */ +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; + status =3D "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/= arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso new file mode 100644 index 000000000000..5dfb0b8f10d2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Second ethernet port GBE1. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +&cpsw3g_mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cpsw_port2 { + phy-connection-type =3D "rgmii-id"; + phy-handle =3D <&phy1>; + nvmem-cells =3D <&base_mac_address 1>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b= /arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso new file mode 100644 index 000000000000..0a3e9f614c4c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Microcrystal RV8263 RTC variant. + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + aliases { + rtc0 =3D "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */ + rtc1 =3D "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */ + }; +}; + +&main_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + rtc: rtc@51 { + compatible =3D "microcrystal,rv8263"; + reg =3D <0x51>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_pins_default>; + interrupts-extended =3D <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFF0130648B; Fri, 12 Sep 2025 12:08:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678903; cv=none; b=hptH/xeCcMGgUhWnLy6f+xhUcgz6/kAFWVM/Ps7dQ2zdAcGxnblcSghWamaerLtVxt3xcyFYfQkfxTfLVE9IdR9ELHFkd677l8U0CL+TWxcf7hJQ+E3uVecCytNQ8mlJtIeUFJIHHNJbHJY/NxuGuxe7Ws8paPTULheMs7ORk+M= ARC-Message-Signature: i=1; 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b=c8HLletFv8+PYS3mud5TlJ74kQnGGkI9mA0vhirZjyr3LjhNOJqVksvR6M7zyZjdZ SYQvUVzc0Hh67Lc+6p420KQVyrMhYDgF3aiu+vG2CV0CegTMrbr9XRj+Jz54zrbXRf RHoSgpiFD3uiyAiBrh3+ePi+efbbDRe9OjRr9bb6okSpkGvi8g8NacL9KcQdCkveOb klnBk3/YuanWt5sX+aj6UwHmGQxt1JBBp+lcZkbxKishmGXxyR9uaTc6HA6AC8fekS kJIghL3cEnZPpLQQyi5zpBCvQKcrWiYjXPANjUorED64ArvrKxP1lMsPX1fxeDCAp+ fzDGhvYDQxbjw== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis , Krzysztof Kozlowski Subject: [PATCH v2 4/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Date: Fri, 12 Sep 2025 14:07:42 +0200 Message-Id: <20250912120745.2295115-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Kontron SMARC-sAM67 module features an on-board house keeping uC. It is designed to be compatible with the older sl28cpld implementation, but has different sensors, like voltage and temperature monitoring. Add a new compatible for that board. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon= .yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 5803a1770cad..966b221b6caa 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -16,6 +16,7 @@ description: | properties: compatible: enum: + - kontron,sa67mcu-hwmon - kontron,sl28cpld-fan =20 reg: --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F40C31DDB4; Fri, 12 Sep 2025 12:08:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678907; cv=none; b=Vgu5ysAGhJU/LzWtpVXuM1FbL9sWyvPgAdtSMEJauu1uawhXSlk7/6U9xnvCXkSgBYsUoXdHQZnqpJa3J6Me9Tb5wumX97BnGsbAqBFyVP53f9qE/1ttoqPUaMQsraRUdakay6s4Dh2bTQsHxIuN0v4QM0umfaEtGF2iFwMHbJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678907; c=relaxed/simple; bh=be+bUwk0HwrL17vqiPMMJhD52aY5E7ndhs1cUU5HK6Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sic0mzzMC1gPqWv+YEmEmzoaW9kgg+w6qTbuHD9iVrPawA51mgO/FO87RfnDKjmChlxJXy1sQwabeJ8Och26hxB9OQzhtU1Tv7NatzEzIjRbYaOV+CrITrSfTtmbljNkB4/+WYgAlX0XnqZ59rLsE5Rqw8t+OIpwgvVfZRvcZVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VnO+Zw+v; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VnO+Zw+v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BEC21C4CEF9; Fri, 12 Sep 2025 12:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678907; bh=be+bUwk0HwrL17vqiPMMJhD52aY5E7ndhs1cUU5HK6Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VnO+Zw+vEeP2fK22pSjN3uy6nADz7y2IRjKwkvi4geRwoqcPOklI4xhf5362H6wSk oRRj5PfC3Z+k1P8gLptL44nLQAavAVqPJyokURmtahqFKXkE9NZ+18ZrV6jGRWGGIp 5P2DPPROwqIX57gAOPKn2aTyDHKHb3BhRlfToES99CXMIP33Nq/+F9m359MSfPNiL3 0Cg4sZIgWcbdFgXEEL0q+eh/+FY4ipZ2sCkXUzngH76Pt5k/9jaf5xVhvRDkyk4GCw U3WMKC3lkMHf36hDUEqgKrW2P/lsfzwvu9XyQBKIgF1Nl60bC16GEeNoDs8MWinlpC +qd/B7BHuf/4A== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis , Krzysztof Kozlowski Subject: [PATCH v2 5/7] dt-bindings: watchdog: add SMARC-sAM67 support Date: Fri, 12 Sep 2025 14:07:43 +0200 Message-Id: <20250912120745.2295115-6-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMARC-sAM67 board has an on-board uC which has the same register interface as the older CPLD implementation on the SMARC-sAL28 board. Although the MCU emulates the same behavior, be prepared for any quirks and add a board specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski Reviewed-by: Guenter Roeck --- .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wd= t.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.ya= ml index 872a8471ef65..0821ba0e84a3 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,7 +18,12 @@ allOf: =20 properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt =20 reg: maxItems: 1 --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CF483043A0; Fri, 12 Sep 2025 12:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678911; cv=none; b=ioz6Cbe+Nm5tzjH3iQeTwaZXIH5oIAFXjtMAhczufIUiXJ6Ndi8qar+T5fZrvV0mRdnuTfkbaV9e8ef56wClstJBgL0ousVAeyn7fJUGnQxbgDLFINmA1Kx8p3CPP9CsnWOwAjIDmrOaOJiM9lqCPqPQr1XMhI7jKUPFDAfKIYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757678911; c=relaxed/simple; bh=iI6wf8clG2A4L9G78U+CNoUvgKXBC0/MOjNwTHPB0Gs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GngGCitVwo24TrA7r88Y7VYYXIfD/E+ce5/IFqNAQ0Gg3mGF6hhgnygWOLa83t0e1IrLQ2X6IJs6SP83fUf6Jpx4Ep0OzQSwDpRjJo5IrmeMgqOauCG+HFH1nAS2lITuHrr57aPgQVbcMfmYDMmWMBxe6Wgc9N8LdGN782anbN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uLOJ00Qp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uLOJ00Qp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B88A8C4CEFA; Fri, 12 Sep 2025 12:08:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678911; bh=iI6wf8clG2A4L9G78U+CNoUvgKXBC0/MOjNwTHPB0Gs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uLOJ00Qp9BNgR8N8Cm7WfGNe+psOP5/2weFvZ7v84ELpmeO7UxQZDBXMqkqAe2M1R 2YuCcTG5uXLUuP2+Nl/N/n1nmVlZXBCY4oq/nqhPowJcwmxssvilwddo5/wckbcpaK 24V+gvcgIz0bRssm9siL1p6p97AFq+O9YXgOztps6gGYVknmlV002BwCstEs4/eeiD FwMz1v3chCn7+zqwJUkZBmbZG1E+d7dB7FIdfOIQjQdX+hN4EivwoiK/GAExBVNzyW fNYjw+tTsUE+tUGQzhdDShpe3UdIIsXo9L8ZdA5wc73I4osc4gpgMZhuOVfzxCA19e 13VBuTF7GPCNA== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis Subject: [PATCH v2 6/7] hwmon: add SMARC-sAM67 support Date: Fri, 12 Sep 2025 14:07:44 +0200 Message-Id: <20250912120745.2295115-7-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new driver for the Kontron SMARC-sAM67 board management controller. It has two voltage sensors and one temperature sensor. Signed-off-by: Michael Walle --- Documentation/hwmon/sa67.rst | 41 +++++++++ MAINTAINERS | 1 + drivers/hwmon/Kconfig | 10 +++ drivers/hwmon/Makefile | 1 + drivers/hwmon/sa67mcu-hwmon.c | 161 ++++++++++++++++++++++++++++++++++ 5 files changed, 214 insertions(+) create mode 100644 Documentation/hwmon/sa67.rst create mode 100644 drivers/hwmon/sa67mcu-hwmon.c diff --git a/Documentation/hwmon/sa67.rst b/Documentation/hwmon/sa67.rst new file mode 100644 index 000000000000..029c7c169b7f --- /dev/null +++ b/Documentation/hwmon/sa67.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +Kernel driver sa67mcu +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Supported chips: + + * Kontron sa67mcu + + Prefix: 'sa67mcu' + + Datasheet: not available + +Authors: Michael Walle + +Description +----------- + +The sa67mcu is a board management controller which also exposes a hardware +monitoring controller. + +The controller has two voltage and one temperature sensor. The values are +hold in two 8 bit registers to form one 16 bit value. Reading the lower by= te +will also capture the high byte to make the access atomic. The unit of the +volatge sensors are 1mV and the unit of the temperature sensor is 0.1degC. + +Sysfs entries +------------- + +The following attributes are supported. + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +in0_label "VDDIN" +in0_input Measured VDDIN voltage. + +in1_label "VDD_RTC" +in1_input Measured VDD_RTC voltage. + +temp1_input MCU temperature. Roughly the board temperature. +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + diff --git a/MAINTAINERS b/MAINTAINERS index fa7f80bd7b2f..69fcd5c077ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23489,6 +23489,7 @@ F: Documentation/devicetree/bindings/interrupt-cont= roller/kontron,sl28cpld-intc. F: Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml F: Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml F: drivers/gpio/gpio-sl28cpld.c +F: drivers/hwmon/sa67mcu-hwmon.c F: drivers/hwmon/sl28cpld-hwmon.c F: drivers/irqchip/irq-sl28cpld.c F: drivers/pwm/pwm-sl28cpld.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index d6769288a76e..c2f288ebdf44 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1905,6 +1905,16 @@ config SENSORS_RASPBERRYPI_HWMON This driver can also be built as a module. If so, the module will be called raspberrypi-hwmon. =20 +config SENSORS_SA67MCU + tristate "Kontron sa67mcu hardware monitoring driver" + depends on MFD_SL28CPLD || COMPILE_TEST + help + If you say yes here you get support for the voltage and temperature + monitor of the sa67 board management controller. + + This driver can also be built as a module. If so, the module + will be called sa67mcu-hwmon. + config SENSORS_SL28CPLD tristate "Kontron sl28cpld hardware monitoring driver" depends on MFD_SL28CPLD || COMPILE_TEST diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 051981eb8a50..2956898776bb 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -197,6 +197,7 @@ obj-$(CONFIG_SENSORS_PT5161L) +=3D pt5161l.o obj-$(CONFIG_SENSORS_PWM_FAN) +=3D pwm-fan.o obj-$(CONFIG_SENSORS_QNAP_MCU_HWMON) +=3D qnap-mcu-hwmon.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) +=3D raspberrypi-hwmon.o +obj-$(CONFIG_SENSORS_SA67MCU) +=3D sa67mcu-hwmon.o obj-$(CONFIG_SENSORS_SBTSI) +=3D sbtsi_temp.o obj-$(CONFIG_SENSORS_SBRMI) +=3D sbrmi.o obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+=3D sch56xx-common.o diff --git a/drivers/hwmon/sa67mcu-hwmon.c b/drivers/hwmon/sa67mcu-hwmon.c new file mode 100644 index 000000000000..22f703b7b256 --- /dev/null +++ b/drivers/hwmon/sa67mcu-hwmon.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * sl67mcu hardware monitoring driver + * + * Copyright 2025 Kontron Europe GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SA67MCU_VOLTAGE(n) (0x00 + ((n) * 2)) +#define SA67MCU_TEMP(n) (0x04 + ((n) * 2)) + +struct sa67mcu_hwmon { + struct regmap *regmap; + u32 offset; +}; + +static int sa67mcu_hwmon_read(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, long *input) +{ + struct sa67mcu_hwmon *hwmon =3D dev_get_drvdata(dev); + unsigned int offset; + u8 reg[2]; + int ret; + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + offset =3D hwmon->offset + SA67MCU_VOLTAGE(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + offset =3D hwmon->offset + SA67MCU_TEMP(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + default: + return -EOPNOTSUPP; + } + + /* Reading the low byte will capture the value */ + ret =3D regmap_bulk_read(hwmon->regmap, offset, reg, ARRAY_SIZE(reg)); + if (ret) + return ret; + + *input =3D reg[1] << 8 | reg[0]; + + /* Temperatures are s16 and in 0.1degC steps. */ + if (type =3D=3D hwmon_temp) + *input =3D sign_extend32(*input, 15) * 100; + + return 0; +} + +static const struct hwmon_channel_info * const sa67mcu_hwmon_info[] =3D { + HWMON_CHANNEL_INFO(in, + HWMON_I_INPUT | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), + NULL +}; + +static const char *const sa67mcu_hwmon_in_labels[] =3D { + "VDDIN", + "VDD_RTC", +}; + +static int sa67mcu_hwmon_read_string(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, const char **str) +{ + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_label: + *str =3D sa67mcu_hwmon_in_labels[channel]; + return 0; + default: + return -EOPNOTSUPP; + } + default: + return -EOPNOTSUPP; + } +} + +static const struct hwmon_ops sa67mcu_hwmon_ops =3D { + .visible =3D 0444, + .read =3D sa67mcu_hwmon_read, + .read_string =3D sa67mcu_hwmon_read_string, +}; + +static const struct hwmon_chip_info sa67mcu_hwmon_chip_info =3D { + .ops =3D &sa67mcu_hwmon_ops, + .info =3D sa67mcu_hwmon_info, +}; + +static int sa67mcu_hwmon_probe(struct platform_device *pdev) +{ + struct sa67mcu_hwmon *hwmon; + struct device *hwmon_dev; + int ret; + + if (!pdev->dev.parent) + return -ENODEV; + + hwmon =3D devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL); + if (!hwmon) + return -ENOMEM; + + hwmon->regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + if (!hwmon->regmap) + return -ENODEV; + + ret =3D device_property_read_u32(&pdev->dev, "reg", &hwmon->offset); + if (ret) + return -EINVAL; + + hwmon_dev =3D devm_hwmon_device_register_with_info(&pdev->dev, + "sa67mcu_hwmon", hwmon, + &sa67mcu_hwmon_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + dev_err(&pdev->dev, "failed to register as hwmon device"); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static const struct of_device_id sa67mcu_hwmon_of_match[] =3D { + { .compatible =3D "kontron,sa67mcu-hwmon", }, + {} +}; +MODULE_DEVICE_TABLE(of, sa67mcu_hwmon_of_match); + +static struct platform_driver sa67mcu_hwmon_driver =3D { + .probe =3D sa67mcu_hwmon_probe, + .driver =3D { + .name =3D "sa67mcu-hwmon", + .of_match_table =3D sa67mcu_hwmon_of_match, + }, +}; +module_platform_driver(sa67mcu_hwmon_driver); + +MODULE_DESCRIPTION("sa67mcu Hardware Monitoring Driver"); +MODULE_AUTHOR("Michael Walle "); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Thu Oct 2 19:27:11 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B287301470; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pFpDf6/v" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C488C4CEF9; Fri, 12 Sep 2025 12:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757678914; bh=Y/xLnOvWrgoYia/dvIuxe9JbBGwmEs4sMATELVf8sII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pFpDf6/vXJKgu9C+t3HaXigUZGGBHOlHz7Kt1tfBpNYo90CyPwsvXk+ZKnv5g0nxS OEJk14rnhZ2TgDVEYoZkasfjHCIpcF+JuivMSG2AlLHE5l4cCe0ntilyyr41pJOni7 LLUGQq1slpPr+CVVcHeGDtCNW2dPHPNrh+fD5xzCLa6VnXGLKyXHpin28SWfVFPRgy 1n7m8BYhTZZW1VGOuiIpNHGgbTNwE5DYdzpsNI//IbvH79GZsl2mhzwHgXoy1WBDDn jbOS0Qnw6yvTTqW970lC51W87bWq9YQ9BexK+7WL9eoK12wmbV7q4J3FrouB6gLqKm SwBh7DI8SCRSQ== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org, Andrew Davis Subject: [PATCH v2 7/7] arm64: dts: ti: sa67: add on-board management controller node Date: Fri, 12 Sep 2025 14:07:45 +0200 Message-Id: <20250912120745.2295115-8-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250912120745.2295115-1-mwalle@kernel.org> References: <20250912120745.2295115-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the node for the onboard management controller which has a watchdog and hardware monitoring. Signed-off-by: Michael Walle --- .../boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/a= rm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 5755df689752..7f05df9111ea 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -416,6 +416,24 @@ vcc_1p8_ret_s5: ldo3 { }; }; =20 + system-controller@4a { + compatible =3D "kontron,sa67mcu", "kontron,sl28cpld"; + reg =3D <0x4a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + watchdog@4 { + compatible =3D "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt"; + reg =3D <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@8 { + compatible =3D "kontron,sa67mcu-hwmon"; + reg =3D <0x8>; + }; + }; + rtc: rtc@51 { compatible =3D "microcrystal,rv8263"; reg =3D <0x51>; --=20 2.39.5