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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7607cd329sm6197316f8f.31.2025.09.12.03.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Sep 2025 03:47:36 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Marc Kleine-Budde , Vincent Mailhol , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-can@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 3/7] can: rcar_canfd: Move enabling of RAM clk from probe() Date: Fri, 12 Sep 2025 11:47:21 +0100 Message-ID: <20250912104733.173281-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912104733.173281-1-biju.das.jz@bp.renesas.com> References: <20250912104733.173281-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RAM clk needs to be enabled in resume for proper operation in STR mode for RZ/G3E SoC. This change also result in less power consumption. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- v2: * New patch. --- drivers/net/can/rcar/rcar_canfd.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 460bb62bbd08..da469595be74 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -468,6 +468,7 @@ struct rcar_canfd_global { struct platform_device *pdev; /* Respective platform device */ struct clk *clkp; /* Peripheral clock */ struct clk *can_clk; /* fCAN clock */ + struct clk *clk_ram; /* Clock RAM */ unsigned long channels_mask; /* Enabled channels mask */ bool extclk; /* CANFD or Ext clock */ bool fdmode; /* CAN FD or Classical CAN only mode */ @@ -1975,7 +1976,6 @@ static int rcar_canfd_probe(struct platform_device *p= dev) u32 rule_entry =3D 0; bool fdmode =3D true; /* CAN FD only mode - default */ char name[9] =3D "channelX"; - struct clk *clk_ram; int i; =20 info =3D of_device_get_match_data(dev); @@ -2065,10 +2065,10 @@ static int rcar_canfd_probe(struct platform_device = *pdev) gpriv->extclk =3D gpriv->info->external_clk; } =20 - clk_ram =3D devm_clk_get_optional_enabled(dev, "ram_clk"); - if (IS_ERR(clk_ram)) - return dev_err_probe(dev, PTR_ERR(clk_ram), - "cannot get enabled ram clock\n"); + gpriv->clk_ram =3D devm_clk_get_optional(dev, "ram_clk"); + if (IS_ERR(gpriv->clk_ram)) + return dev_err_probe(dev, PTR_ERR(gpriv->clk_ram), + "cannot get ram clock\n"); =20 addr =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(addr)) { @@ -2134,10 +2134,18 @@ static int rcar_canfd_probe(struct platform_device = *pdev) goto fail_reset; } =20 + /* Enable RAM clock */ + err =3D clk_prepare_enable(gpriv->clk_ram); + if (err) { + dev_err(dev, "failed to enable RAM clock: %pe\n", + ERR_PTR(err)); + goto fail_clk; + } + err =3D rcar_canfd_reset_controller(gpriv); if (err) { dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err)); - goto fail_clk; + goto fail_ram_clk; } =20 /* Controller in Global reset & Channel reset mode */ @@ -2189,6 +2197,8 @@ static int rcar_canfd_probe(struct platform_device *p= dev) rcar_canfd_channel_remove(gpriv, ch); fail_mode: rcar_canfd_disable_global_interrupts(gpriv); +fail_ram_clk: + clk_disable_unprepare(gpriv->clk_ram); fail_clk: clk_disable_unprepare(gpriv->clkp); fail_reset: @@ -2213,6 +2223,7 @@ static void rcar_canfd_remove(struct platform_device = *pdev) =20 /* Enter global sleep mode */ rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR); + clk_disable_unprepare(gpriv->clk_ram); clk_disable_unprepare(gpriv->clkp); reset_control_assert(gpriv->rstc2); reset_control_assert(gpriv->rstc1); --=20 2.43.0