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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a36dc461sm4066564a12.23.2025.09.12.02.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Sep 2025 02:20:22 -0700 (PDT) From: a0282524688@gmail.com To: tmyu0@nuvoton.com, lee@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, andi.shyti@kernel.org, mkl@pengutronix.de, mailhol.vincent@wanadoo.fr, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, wim@linux-watchdog.org, linux@roeck-us.net, jdelvare@suse.com, alexandre.belloni@bootlin.com Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-rtc@vger.kernel.org, linux-usb@vger.kernel.org, Ming Yu , Bartosz Golaszewski Subject: [PATCH RESEND v14 2/7] gpio: Add Nuvoton NCT6694 GPIO support Date: Fri, 12 Sep 2025 17:19:47 +0800 Message-Id: <20250912091952.1169369-3-a0282524688@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250912091952.1169369-1-a0282524688@gmail.com> References: <20250912091952.1169369-1-a0282524688@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ming Yu This driver supports GPIO and IRQ functionality for NCT6694 MFD device based on USB interface. Reviewed-by: Linus Walleij Acked-by: Bartosz Golaszewski Signed-off-by: Ming Yu --- Changes since version 13: Changes since version 12: - Implement IDA in MFD driver to handle per-device IDs - Use same email address in the signature Changes since version 11: - Use platform_device's id to replace IDA Changes since version 10: - Implement IDA to allocate id Changes since version 9: - Add devm_add_action_or_reset() to dispose irq mapping Changes since version 8: - Modify the signed-off-by with my work address - Add irq_dispose_mapping() in the error handling path and in the remove function Changes since version 7: - Add error handling for devm_mutex_init() Changes since version 6: Changes since version 5: - Modify the module name and the driver name consistently Changes since version 4: - Modify arguments in read/write function to a pointer to cmd_header - Modify all callers that call the read/write function Changes since version 3: - Modify array buffer to structure - Fix defines and comments - Add header and use BIT macro - Modify mutex_init() to devm_mutex_init() Changes since version 2: - Add MODULE_ALIAS() - Modify gpio line names be a local variable in gpio-nct6694.c - Drop unnecessary platform_get_drvdata() in gpio-nct6694.c Changes since version 1: - Add each driver's command structure - Fix platform driver registration - Drop unnecessary header - Add gpio line names MAINTAINERS | 1 + drivers/gpio/Kconfig | 12 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-nct6694.c | 499 ++++++++++++++++++++++++++++++++++++ 4 files changed, 513 insertions(+) create mode 100644 drivers/gpio/gpio-nct6694.c diff --git a/MAINTAINERS b/MAINTAINERS index a8a05872d077..e340d1934394 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18085,6 +18085,7 @@ F: include/uapi/linux/nubus.h NUVOTON NCT6694 MFD DRIVER M: Ming Yu S: Supported +F: drivers/gpio/gpio-nct6694.c F: drivers/mfd/nct6694.c F: include/linux/mfd/nct6694.h =20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e43abb322fa6..1e0b1f5190a1 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1522,6 +1522,18 @@ config GPIO_MAX77759 This driver can also be built as a module. If so, the module will be called gpio-max77759. =20 +config GPIO_NCT6694 + tristate "Nuvoton NCT6694 GPIO controller support" + depends on MFD_NCT6694 + select GENERIC_IRQ_CHIP + select GPIOLIB_IRQCHIP + help + This driver supports 8 GPIO pins per bank that can all be interrupt + sources. + + This driver can also be built as a module. If so, the module will be + called gpio-nct6694. + config GPIO_PALMAS tristate "TI PALMAS series PMICs GPIO" depends on MFD_PALMAS diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 379f55e9ed1e..f3e837fccdd2 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -128,6 +128,7 @@ obj-$(CONFIG_GPIO_MT7621) +=3D gpio-mt7621.o obj-$(CONFIG_GPIO_MVEBU) +=3D gpio-mvebu.o obj-$(CONFIG_GPIO_MXC) +=3D gpio-mxc.o obj-$(CONFIG_GPIO_MXS) +=3D gpio-mxs.o +obj-$(CONFIG_GPIO_NCT6694) +=3D gpio-nct6694.o obj-$(CONFIG_GPIO_NOMADIK) +=3D gpio-nomadik.o obj-$(CONFIG_GPIO_NPCM_SGPIO) +=3D gpio-npcm-sgpio.o obj-$(CONFIG_GPIO_OCTEON) +=3D gpio-octeon.o diff --git a/drivers/gpio/gpio-nct6694.c b/drivers/gpio/gpio-nct6694.c new file mode 100644 index 000000000000..a8607f0d9915 --- /dev/null +++ b/drivers/gpio/gpio-nct6694.c @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NCT6694 GPIO controller driver based on USB interface. + * + * Copyright (C) 2025 Nuvoton Technology Corp. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * USB command module type for NCT6694 GPIO controller. + * This defines the module type used for communication with the NCT6694 + * GPIO controller over the USB interface. + */ +#define NCT6694_GPIO_MOD 0xFF + +#define NCT6694_GPIO_VER 0x90 +#define NCT6694_GPIO_VALID 0x110 +#define NCT6694_GPI_DATA 0x120 +#define NCT6694_GPO_DIR 0x170 +#define NCT6694_GPO_TYPE 0x180 +#define NCT6694_GPO_DATA 0x190 + +#define NCT6694_GPI_STS 0x130 +#define NCT6694_GPI_CLR 0x140 +#define NCT6694_GPI_FALLING 0x150 +#define NCT6694_GPI_RISING 0x160 + +#define NCT6694_NR_GPIO 8 + +struct nct6694_gpio_data { + struct nct6694 *nct6694; + struct gpio_chip gpio; + struct mutex lock; + /* Protect irq operation */ + struct mutex irq_lock; + + unsigned char reg_val; + unsigned char irq_trig_falling; + unsigned char irq_trig_rising; + + /* Current gpio group */ + unsigned char group; + int irq; +}; + +static int nct6694_get_direction(struct gpio_chip *gpio, unsigned int offs= et) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + const struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_DIR + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + return !(BIT(offset) & data->reg_val); +} + +static int nct6694_direction_input(struct gpio_chip *gpio, unsigned int of= fset) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + const struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_DIR + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + data->reg_val &=3D ~BIT(offset); + + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); +} + +static int nct6694_direction_output(struct gpio_chip *gpio, + unsigned int offset, int val) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_DIR + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + /* Set direction to output */ + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + data->reg_val |=3D BIT(offset); + ret =3D nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + /* Then set output level */ + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPO_DATA + data->group); + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + if (val) + data->reg_val |=3D BIT(offset); + else + data->reg_val &=3D ~BIT(offset); + + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); +} + +static int nct6694_get_value(struct gpio_chip *gpio, unsigned int offset) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_DIR + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + if (BIT(offset) & data->reg_val) { + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPO_DATA + data->group); + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + return !!(BIT(offset) & data->reg_val); + } + + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPI_DATA + data->group); + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + return !!(BIT(offset) & data->reg_val); +} + +static int nct6694_set_value(struct gpio_chip *gpio, unsigned int offset, + int val) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + const struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_DATA + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + if (val) + data->reg_val |=3D BIT(offset); + else + data->reg_val &=3D ~BIT(offset); + + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); +} + +static int nct6694_set_config(struct gpio_chip *gpio, unsigned int offset, + unsigned long config) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + const struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPO_TYPE + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + switch (pinconf_to_config_param(config)) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + data->reg_val |=3D BIT(offset); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + data->reg_val &=3D ~BIT(offset); + break; + default: + return -ENOTSUPP; + } + + return nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); +} + +static int nct6694_init_valid_mask(struct gpio_chip *gpio, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + const struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPIO_VALID + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret < 0) + return ret; + + *valid_mask =3D data->reg_val; + + return ret; +} + +static irqreturn_t nct6694_irq_handler(int irq, void *priv) +{ + struct nct6694_gpio_data *data =3D priv; + struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPI_STS + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + unsigned char status; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->reg_val); + if (ret) + return IRQ_NONE; + + status =3D data->reg_val; + + while (status) { + int bit =3D __ffs(status); + + data->reg_val =3D BIT(bit); + handle_nested_irq(irq_find_mapping(data->gpio.irq.domain, bit)); + status &=3D ~BIT(bit); + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPI_CLR + data->group); + nct6694_write_msg(data->nct6694, &cmd_hd, &data->reg_val); + } + + return IRQ_HANDLED; +} + +static int nct6694_get_irq_trig(struct nct6694_gpio_data *data) +{ + struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPI_FALLING + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + int ret; + + guard(mutex)(&data->lock); + + ret =3D nct6694_read_msg(data->nct6694, &cmd_hd, &data->irq_trig_falling); + if (ret) + return ret; + + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPI_RISING + data->group); + return nct6694_read_msg(data->nct6694, &cmd_hd, &data->irq_trig_rising); +} + +static void nct6694_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gpio =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + gpiochip_disable_irq(gpio, hwirq); +} + +static void nct6694_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gpio =3D irq_data_get_irq_chip_data(d); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + gpiochip_enable_irq(gpio, hwirq); +} + +static int nct6694_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gpio =3D irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + + guard(mutex)(&data->lock); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + data->irq_trig_rising |=3D BIT(hwirq); + break; + + case IRQ_TYPE_EDGE_FALLING: + data->irq_trig_falling |=3D BIT(hwirq); + break; + + case IRQ_TYPE_EDGE_BOTH: + data->irq_trig_rising |=3D BIT(hwirq); + data->irq_trig_falling |=3D BIT(hwirq); + break; + + default: + return -ENOTSUPP; + } + + return 0; +} + +static void nct6694_irq_bus_lock(struct irq_data *d) +{ + struct gpio_chip *gpio =3D irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + + mutex_lock(&data->irq_lock); +} + +static void nct6694_irq_bus_sync_unlock(struct irq_data *d) +{ + struct gpio_chip *gpio =3D irq_data_get_irq_chip_data(d); + struct nct6694_gpio_data *data =3D gpiochip_get_data(gpio); + struct nct6694_cmd_header cmd_hd =3D { + .mod =3D NCT6694_GPIO_MOD, + .offset =3D cpu_to_le16(NCT6694_GPI_FALLING + data->group), + .len =3D cpu_to_le16(sizeof(data->reg_val)) + }; + + scoped_guard(mutex, &data->lock) { + nct6694_write_msg(data->nct6694, &cmd_hd, &data->irq_trig_falling); + + cmd_hd.offset =3D cpu_to_le16(NCT6694_GPI_RISING + data->group); + nct6694_write_msg(data->nct6694, &cmd_hd, &data->irq_trig_rising); + } + + mutex_unlock(&data->irq_lock); +} + +static const struct irq_chip nct6694_irq_chip =3D { + .name =3D "gpio-nct6694", + .irq_mask =3D nct6694_irq_mask, + .irq_unmask =3D nct6694_irq_unmask, + .irq_set_type =3D nct6694_irq_set_type, + .irq_bus_lock =3D nct6694_irq_bus_lock, + .irq_bus_sync_unlock =3D nct6694_irq_bus_sync_unlock, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static void nct6694_irq_dispose_mapping(void *d) +{ + struct nct6694_gpio_data *data =3D d; + + irq_dispose_mapping(data->irq); +} + +static void nct6694_gpio_ida_free(void *d) +{ + struct nct6694_gpio_data *data =3D d; + struct nct6694 *nct6694 =3D data->nct6694; + + ida_free(&nct6694->gpio_ida, data->group); +} + +static int nct6694_gpio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct nct6694 *nct6694 =3D dev_get_drvdata(dev->parent); + struct nct6694_gpio_data *data; + struct gpio_irq_chip *girq; + int ret, i; + char **names; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->nct6694 =3D nct6694; + + ret =3D ida_alloc(&nct6694->gpio_ida, GFP_KERNEL); + if (ret < 0) + return ret; + data->group =3D ret; + + ret =3D devm_add_action_or_reset(dev, nct6694_gpio_ida_free, data); + if (ret) + return ret; + + names =3D devm_kcalloc(dev, NCT6694_NR_GPIO, sizeof(char *), + GFP_KERNEL); + if (!names) + return -ENOMEM; + + for (i =3D 0; i < NCT6694_NR_GPIO; i++) { + names[i] =3D devm_kasprintf(dev, GFP_KERNEL, "GPIO%X%d", + data->group, i); + if (!names[i]) + return -ENOMEM; + } + + data->irq =3D irq_create_mapping(nct6694->domain, + NCT6694_IRQ_GPIO0 + data->group); + if (!data->irq) + return -EINVAL; + + ret =3D devm_add_action_or_reset(dev, nct6694_irq_dispose_mapping, data); + if (ret) + return ret; + + data->gpio.names =3D (const char * const*)names; + data->gpio.label =3D pdev->name; + data->gpio.direction_input =3D nct6694_direction_input; + data->gpio.get =3D nct6694_get_value; + data->gpio.direction_output =3D nct6694_direction_output; + data->gpio.set =3D nct6694_set_value; + data->gpio.get_direction =3D nct6694_get_direction; + data->gpio.set_config =3D nct6694_set_config; + data->gpio.init_valid_mask =3D nct6694_init_valid_mask; + data->gpio.base =3D -1; + data->gpio.can_sleep =3D false; + data->gpio.owner =3D THIS_MODULE; + data->gpio.ngpio =3D NCT6694_NR_GPIO; + + platform_set_drvdata(pdev, data); + + ret =3D devm_mutex_init(dev, &data->lock); + if (ret) + return ret; + + ret =3D devm_mutex_init(dev, &data->irq_lock); + if (ret) + return ret; + + ret =3D nct6694_get_irq_trig(data); + if (ret) { + dev_err_probe(dev, ret, "Failed to get irq trigger type\n"); + return ret; + } + + girq =3D &data->gpio.irq; + gpio_irq_chip_set_chip(girq, &nct6694_irq_chip); + girq->parent_handler =3D NULL; + girq->num_parents =3D 0; + girq->parents =3D NULL; + girq->default_type =3D IRQ_TYPE_NONE; + girq->handler =3D handle_level_irq; + girq->threaded =3D true; + + ret =3D devm_request_threaded_irq(dev, data->irq, NULL, nct6694_irq_handl= er, + IRQF_ONESHOT | IRQF_SHARED, + "gpio-nct6694", data); + if (ret) { + dev_err_probe(dev, ret, "Failed to request irq\n"); + return ret; + } + + return devm_gpiochip_add_data(dev, &data->gpio, data); +} + +static struct platform_driver nct6694_gpio_driver =3D { + .driver =3D { + .name =3D "nct6694-gpio", + }, + .probe =3D nct6694_gpio_probe, +}; + +module_platform_driver(nct6694_gpio_driver); + +MODULE_DESCRIPTION("USB-GPIO controller driver for NCT6694"); +MODULE_AUTHOR("Ming Yu "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:nct6694-gpio"); --=20 2.34.1