From nobody Thu Oct 2 19:28:03 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0924432F768; Fri, 12 Sep 2025 18:38:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757702295; cv=pass; b=I7sjq5jEBORM3hr7KpQLQzP3uJUueeJ0ZdtBnlUlVgj8Rj9njTI+LlYKH8Qp7gjnrcBWvChPZQxhGnzgOT3h98ACA98+Rlvxx2AlYrWXteePxLsEFJ9pF6BoCpFC3U83duLrAYoigtdrMMVucyWIG/83D0TpC/YbFTUHxiM5Q94= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757702295; c=relaxed/simple; bh=xpX6nc0zR9r9FFaiUroEPgMJYTBdN/zREbiJIaG5aQo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QyN3hnHDKqn5jGepYouIsVh1FjxaDFSspib/MgzGK2lA4Wj1a30iuRdWkyj2Sz9qUWVZ4vcM14QAz3gw9c4LO0p/KSOIF2nqoMmbCyUakfKcyFfZQeWN4c2SCOdUvwyEOaYbmnZY7o8cmpaA+P13q1GNF2eit5NNYpgu7R6x0G8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=PFDyDR20; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="PFDyDR20" ARC-Seal: i=1; a=rsa-sha256; t=1757702262; cv=none; d=zohomail.com; s=zohoarc; b=byJeH/qvrKSq0hRdY3YAxb4YuVStbP8Q8VjieV/qNRDppLSnEK62wmkr53+MnMm4UxAvZtcGVL7utDj44rhO3ZR9+Di5/tb7FKkxb2zjqo8Jj5wn1ojzQEVIvW97jmdJL4L2t9CDl7UYbFnJq98yWy9VEEjWxr/zmbIkOilQX1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1757702262; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=RM1CPtpcM7iofFgJi6EoZwd3D3Y67w7Up4uLm6O8Je4=; b=khTz1fGFOTVAy89miF0ilU82wfp3RnCPCikZlA+QkbOukt/skJOOXsObFcpolr1Nnlmj7pS7PZe0MGoHnbnmB7HZUNrWqq8sjZfpm2iTAnehdNVJ2Vi/2pVl40+E1qVHdoWFy0ujnopjNLJD6WLzJRpb2bFLv6aaaE6SU8q3zJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1757702262; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=RM1CPtpcM7iofFgJi6EoZwd3D3Y67w7Up4uLm6O8Je4=; b=PFDyDR206u30J3avNJ3Hwa4+fmfWyq6mBbycW/ult5ii31XcdDrpgc1d5sLYAe5A ED0AJv7KMjsSXpoQ4NkWawG/A+LoMKdMbz2pHmrniKUy0aNtzywn50ZHAw4AgYCHFh6 1gR5r1dMQvBXNifWNlzscfG5lTrdFW5nlGjfjpj0= Received: by mx.zohomail.com with SMTPS id 1757702259914663.1005178250432; Fri, 12 Sep 2025 11:37:39 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 12 Sep 2025 20:37:01 +0200 Subject: [PATCH v2 02/10] dt-bindings: devfreq: add mt8196-gpufreq binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-mt8196-gpufreq-v2-2-779a8a3729d9@collabora.com> References: <20250912-mt8196-gpufreq-v2-0-779a8a3729d9@collabora.com> In-Reply-To: <20250912-mt8196-gpufreq-v2-0-779a8a3729d9@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On the MediaTek MT8196 SoC, the GPU has its power and frequency dynamically controlled by an embedded special-purpose MCU. This MCU is in charge of powering up the GPU silicon. It also provides us with a list of available OPPs at runtime, and is fully in control of all the regulator and clock fiddling it takes to reach a certain level of performance. It's also in charge of enforcing limits on power draw or temperature. Add a binding for this device in the devfreq subdirectory, where it seems to fit in best considering its tasks. Signed-off-by: Nicolas Frattaroli --- .../bindings/devfreq/mediatek,mt8196-gpufreq.yaml | 113 +++++++++++++++++= ++++ 1 file changed, 113 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpuf= req.yaml b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufre= q.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9d9efd4e70f1ef7ae446c833c15= 144beb9641b16 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Performance Controller + +maintainers: + - Nicolas Frattaroli + +description: | + A special-purpose embedded MCU to control power and frequency of GPU dev= ices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^performance-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw_revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: mfgpll + - const: mfgpll_sc0 + - const: mfgpll_sc1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + + "#performance-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + gpufreq: performance-controller@4b09fd00 { + compatible =3D "mediatek,mt8196-gpufreq"; + reg =3D <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names =3D "gpr", "rpc", "hw_revision"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names =3D "eb", "mfgpll", "mfgpll_sc0", + "mfgpll_sc1"; + mboxes =3D <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names =3D "fast-dvfs-event", "gpufreq", "sleep", "timer", "fh= ctl", + "ccf", "fast-dvfs"; + shmem =3D <&gpufreq_shmem>; + #performance-domain-cells =3D <0>; + }; --=20 2.51.0