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Fri, 12 Sep 2025 12:10:09 -0700 (PDT) From: David Lechner Date: Fri, 12 Sep 2025 14:09:30 -0500 Subject: [PATCH v2 1/4] iio: adc: ad7173: rename ad7173_chan_spec_ext_info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-iio-adc-ad7137-add-filter-support-v2-1-bd32dfa3d761@baylibre.com> References: <20250912-iio-adc-ad7137-add-filter-support-v2-0-bd32dfa3d761@baylibre.com> In-Reply-To: <20250912-iio-adc-ad7137-add-filter-support-v2-0-bd32dfa3d761@baylibre.com> To: Michael Hennerich , Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1245; i=dlechner@baylibre.com; h=from:subject:message-id; bh=fidggILI+vKbI25x1Wtgqu1lihcFxBqH8ZEXbL7BQds=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBoxG/1lUlrPPP8W1TAfdKeuU8DdejGrulcQ3EAT 4szO0uy0ZmJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaMRv9QAKCRDCzCAB/wGP wN2QB/9nT/LD50wLxVl1M98uEau9N5qeN438D7LcuxDPdBuQIt4/i7av1AvPqqHOgp67con+BPk 3rgaPzvC84STUXwI6SEs82GRQSmP8ZRL6uTlC1phHaKoKzGxTWGPQa3WnVE6T4HENtp6QxYGpxJ HBvQ69/9/kLY1NzuvlHg0R8n3vfMelkR6tQSzBNOs5JHTNmwlr2aFk0To+lXkuKPvKj1tr3epaf WAT6EyBRUpXOPZBDCVT3zxzkzyGofkYiKtmzcFfGMKZXgdwwh1l+GX6Jq13p/PpXA73a5L9jako +eoSxFTULP9c7q9yFkJ06fWF7ChJgdL8uy2rt775JDzb6A4g X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Rename ad7173_calibsys_ext_info[] to ad7173_chan_spec_ext_info[]. This array is not limited to calibration attributes, so the name should be more generic. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner --- drivers/iio/adc/ad7173.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/ad7173.c b/drivers/iio/adc/ad7173.c index 0dbbdd7d2b9a7a8e5a3908e27d7155f002ce271b..df586cb8f09ccc6d1647c66fdb9= f147c0b4694b8 100644 --- a/drivers/iio/adc/ad7173.c +++ b/drivers/iio/adc/ad7173.c @@ -369,7 +369,7 @@ static const struct iio_enum ad7173_syscalib_mode_enum = =3D { .get =3D ad7173_get_syscalib_mode }; =20 -static const struct iio_chan_spec_ext_info ad7173_calibsys_ext_info[] =3D { +static const struct iio_chan_spec_ext_info ad7173_chan_spec_ext_info[] =3D= { { .name =3D "sys_calibration", .write =3D ad7173_write_syscalib, @@ -1399,7 +1399,7 @@ static const struct iio_chan_spec ad7173_channel_temp= late =3D { .storagebits =3D 32, .endianness =3D IIO_BE, }, - .ext_info =3D ad7173_calibsys_ext_info, + .ext_info =3D ad7173_chan_spec_ext_info, }; =20 static const struct iio_chan_spec ad7173_temp_iio_channel_template =3D { --=20 2.43.0 From nobody Thu Oct 2 18:17:40 2025 Received: from mail-oa1-f54.google.com (mail-oa1-f54.google.com [209.85.160.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78315334723 for ; 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Fri, 12 Sep 2025 12:10:10 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:1d00:fdf1:f11e:e330:d3c1]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7524986c872sm1172564a34.15.2025.09.12.12.10.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Sep 2025 12:10:10 -0700 (PDT) From: David Lechner Date: Fri, 12 Sep 2025 14:09:31 -0500 Subject: [PATCH v2 2/4] iio: adc: ad7173: rename odr field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-iio-adc-ad7137-add-filter-support-v2-2-bd32dfa3d761@baylibre.com> References: <20250912-iio-adc-ad7137-add-filter-support-v2-0-bd32dfa3d761@baylibre.com> In-Reply-To: <20250912-iio-adc-ad7137-add-filter-support-v2-0-bd32dfa3d761@baylibre.com> To: Michael Hennerich , Jonathan Cameron , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, David Lechner X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3394; i=dlechner@baylibre.com; h=from:subject:message-id; bh=v0NAW7Y8Tgsq4aoIScefhPV46tEnXeycoysRScmk0Ec=; b=owEBbQGS/pANAwAKAcLMIAH/AY/AAcsmYgBoxG/8/RmUXg0ZY9kb6HJ+04aymbzF6MgReJoOd mxl9Et7JhCJATMEAAEKAB0WIQTsGNmeYg6D1pzYaJjCzCAB/wGPwAUCaMRv/AAKCRDCzCAB/wGP wEK6B/9XK4C0R9w7TaO5OCYGHStxfDUkSTiahti8qnURv+f38LAF6wW8pa/2Aa+lrAL3ucWnDF3 8SQ/8hSVRsp2BwqNuV/E4w9jodb/+8Fww+IQ47pWh/hzaE3gDpsWM3S2pl2nVDmsbPsXDstmvas rFUeOJT83UQBEkbVZOla2p3W0DCak23ezrH+IzE8Kj7qauWahHbtCLBGqVGeXFNk3rv7trbqtAe jC9yeU/tn59wrxQZyTFQe0FlLNP4JBHQZ8zif2vJ8Z+IbCLI8Bwtmrat+MUaRa8adLLs9UxAdf2 b6X1lYCDYaqWDE9KU8K4Rbx1nsBlqJfsGEuk/W4mAlSQX3jY X-Developer-Key: i=dlechner@baylibre.com; a=openpgp; fpr=8A73D82A6A1F509907F373881F8AF88C82F77C03 Rename odr to sinc5_odr_index in the channel setup structure. In a following commit, we will be adding a separate odr field for when the sinc3 filter is used instead so having sinc5 in the name will help avoid confusion. And _index makes it more clear that this is an index of the sinc5_data_rates array and not the output data rate itself. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner --- drivers/iio/adc/ad7173.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/iio/adc/ad7173.c b/drivers/iio/adc/ad7173.c index df586cb8f09ccc6d1647c66fdb9f147c0b4694b8..80734ae25f9df31d846e242ab71= 42251e4ee588d 100644 --- a/drivers/iio/adc/ad7173.c +++ b/drivers/iio/adc/ad7173.c @@ -205,7 +205,7 @@ struct ad7173_channel_config { struct_group(config_props, bool bipolar; bool input_buf; - u8 odr; + u8 sinc5_odr_index; u8 ref_sel; ); }; @@ -582,13 +582,13 @@ static bool ad7173_setup_equal(const struct ad7173_ch= annel_config *cfg1, sizeof(struct { bool bipolar; bool input_buf; - u8 odr; + u8 sinc5_odr_index; u8 ref_sel; })); =20 return cfg1->bipolar =3D=3D cfg2->bipolar && cfg1->input_buf =3D=3D cfg2->input_buf && - cfg1->odr =3D=3D cfg2->odr && + cfg1->sinc5_odr_index =3D=3D cfg2->sinc5_odr_index && cfg1->ref_sel =3D=3D cfg2->ref_sel; } =20 @@ -650,7 +650,7 @@ static int ad7173_load_config(struct ad7173_state *st, return ret; =20 return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, - AD7173_FILTER_ODR0_MASK & cfg->odr); + AD7173_FILTER_ODR0_MASK & cfg->sinc5_odr_index); } =20 static int ad7173_config_channel(struct ad7173_state *st, int addr) @@ -1183,7 +1183,7 @@ static int ad7173_read_raw(struct iio_dev *indio_dev, return -EINVAL; } case IIO_CHAN_INFO_SAMP_FREQ: - reg =3D st->channels[chan->address].cfg.odr; + reg =3D st->channels[chan->address].cfg.sinc5_odr_index; =20 *val =3D st->info->sinc5_data_rates[reg] / MILLI; *val2 =3D (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI); @@ -1229,7 +1229,7 @@ static int ad7173_write_raw(struct iio_dev *indio_dev, break; =20 cfg =3D &st->channels[chan->address].cfg; - cfg->odr =3D i; + cfg->sinc5_odr_index =3D i; cfg->live =3D false; break; =20 @@ -1655,7 +1655,7 @@ static int ad7173_fw_parse_channel_config(struct iio_= dev *indio_dev) chan_st_priv->cfg.bipolar =3D false; chan_st_priv->cfg.input_buf =3D st->info->has_input_buf; chan_st_priv->cfg.ref_sel =3D AD7173_SETUP_REF_SEL_INT_REF; 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This family of chips by default uses a sinc5+sinc1 filter. There are also optional post-filters that can be added in this configuration for various 50/60Hz rejection purposes. The sinc3 filter doesn't have any post-filters and handles the output data rate (ODR) a bit differently. Here, we've opted to use SINC3_MAPx to get the maximum possible sampling frequencies with the SINC3 filter. Adding support consists of adding the filter_type and filter_type_available attributes, making the sampling_frequency attribute aware of the filter type, and programming the filter parameters when we configure the channel of the ADC for reading a sample. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner --- drivers/iio/adc/ad7173.c | 186 +++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 181 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/ad7173.c b/drivers/iio/adc/ad7173.c index 80734ae25f9df31d846e242ab7142251e4ee588d..48947210a1036f0efef04805089= 0db3d260f67ce 100644 --- a/drivers/iio/adc/ad7173.c +++ b/drivers/iio/adc/ad7173.c @@ -8,6 +8,7 @@ * AD7175-8/AD7176-2/AD7177-2 * * Copyright (C) 2015, 2024 Analog Devices, Inc. + * Copyright (C) 2025 BayLibre, SAS */ =20 #include @@ -149,7 +150,12 @@ (pin2) < st->info->num_voltage_in && \ (pin2) >=3D st->info->num_voltage_in_div) =20 -#define AD7173_FILTER_ODR0_MASK GENMASK(5, 0) +#define AD7173_FILTER_SINC3_MAP BIT(15) +#define AD7173_FILTER_SINC3_MAP_DIV GENMASK(14, 0) +#define AD7173_FILTER_ENHFILTEN BIT(11) +#define AD7173_FILTER_ENHFILT_MASK GENMASK(10, 8) +#define AD7173_FILTER_ORDER BIT(6) +#define AD7173_FILTER_ODR_MASK GENMASK(5, 0) #define AD7173_MAX_CONFIGS 8 #define AD4111_OW_DET_THRSH_MV 300 =20 @@ -190,6 +196,15 @@ struct ad7173_device_info { u8 num_gpios; }; =20 +enum ad7173_filter_type { + AD7173_FILTER_SINC3, + AD7173_FILTER_SINC5_SINC1, + AD7173_FILTER_SINC5_SINC1_PF1, + AD7173_FILTER_SINC5_SINC1_PF2, + AD7173_FILTER_SINC5_SINC1_PF3, + AD7173_FILTER_SINC5_SINC1_PF4, +}; + struct ad7173_channel_config { /* Openwire detection threshold */ unsigned int openwire_thrsh_raw; @@ -205,8 +220,10 @@ struct ad7173_channel_config { struct_group(config_props, bool bipolar; bool input_buf; + u16 sinc3_odr_div; u8 sinc5_odr_index; u8 ref_sel; + enum ad7173_filter_type filter_type; ); }; =20 @@ -266,6 +283,24 @@ static const unsigned int ad7175_sinc5_data_rates[] = =3D { 5000, /* 20 */ }; =20 +/** + * ad7173_sinc3_odr_div_from_odr() - Convert ODR to divider value + * @odr_millihz: ODR (sampling_frequency) in milliHz + * Returns: Divider value for SINC3 filter to pass. + */ +static u16 ad7173_sinc3_odr_div_from_odr(u32 odr_millihz) +{ + /* + * Divider is f_MOD (1 MHz) / 32 / ODR. ODR freq is in milliHz, so + * we need to convert f_MOD to the same units. When SING_CYC=3D1 or + * multiple channels are enabled (currently always the case), there + * is an additional factor of 3. + */ + u32 div =3D DIV_ROUND_CLOSEST(MEGA * MILLI, odr_millihz * 32 * 3); + /* Avoid divide by 0 and limit to register field size. */ + return clamp(div, 1U, AD7173_FILTER_SINC3_MAP_DIV); +} + static unsigned int ad4111_current_channel_config[] =3D { /* Ain sel: pos neg */ 0x1E8, /* 15:IIN0+ 8:IIN0=E2=88=92 */ @@ -369,6 +404,47 @@ static const struct iio_enum ad7173_syscalib_mode_enum= =3D { .get =3D ad7173_get_syscalib_mode }; =20 +static const char * const ad7173_filter_types_str[] =3D { + [AD7173_FILTER_SINC3] =3D "sinc3", + [AD7173_FILTER_SINC5_SINC1] =3D "sinc5+sinc1", + [AD7173_FILTER_SINC5_SINC1_PF1] =3D "sinc5+sinc1+pf1", + [AD7173_FILTER_SINC5_SINC1_PF2] =3D "sinc5+sinc1+pf2", + [AD7173_FILTER_SINC5_SINC1_PF3] =3D "sinc5+sinc1+pf3", + [AD7173_FILTER_SINC5_SINC1_PF4] =3D "sinc5+sinc1+pf4", +}; + +static int ad7173_set_filter_type(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int val) +{ + struct ad7173_state *st =3D iio_priv(indio_dev); + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + st->channels[chan->address].cfg.filter_type =3D val; + st->channels[chan->address].cfg.live =3D false; + + iio_device_release_direct(indio_dev); + + return 0; +} + +static int ad7173_get_filter_type(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad7173_state *st =3D iio_priv(indio_dev); + + return st->channels[chan->address].cfg.filter_type; +} + +static const struct iio_enum ad7173_filter_type_enum =3D { + .items =3D ad7173_filter_types_str, + .num_items =3D ARRAY_SIZE(ad7173_filter_types_str), + .set =3D ad7173_set_filter_type, + .get =3D ad7173_get_filter_type, +}; + static const struct iio_chan_spec_ext_info ad7173_chan_spec_ext_info[] =3D= { { .name =3D "sys_calibration", @@ -379,6 +455,16 @@ static const struct iio_chan_spec_ext_info ad7173_chan= _spec_ext_info[] =3D { &ad7173_syscalib_mode_enum), IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, &ad7173_syscalib_mode_enum), + IIO_ENUM("filter_type", IIO_SEPARATE, &ad7173_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, + &ad7173_filter_type_enum), + { } +}; + +static const struct iio_chan_spec_ext_info ad7173_temp_chan_spec_ext_info[= ] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad7173_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE, + &ad7173_filter_type_enum), { } }; =20 @@ -582,14 +668,18 @@ static bool ad7173_setup_equal(const struct ad7173_ch= annel_config *cfg1, sizeof(struct { bool bipolar; bool input_buf; + u16 sinc3_odr_div; u8 sinc5_odr_index; u8 ref_sel; + enum ad7173_filter_type filter_type; })); =20 return cfg1->bipolar =3D=3D cfg2->bipolar && cfg1->input_buf =3D=3D cfg2->input_buf && + cfg1->sinc3_odr_div =3D=3D cfg2->sinc3_odr_div && cfg1->sinc5_odr_index =3D=3D cfg2->sinc5_odr_index && - cfg1->ref_sel =3D=3D cfg2->ref_sel; + cfg1->ref_sel =3D=3D cfg2->ref_sel && + cfg1->filter_type =3D=3D cfg2->filter_type; } =20 static struct ad7173_channel_config * @@ -630,6 +720,7 @@ static int ad7173_load_config(struct ad7173_state *st, { unsigned int config; int free_cfg_slot, ret; + u8 post_filter_enable, post_filter_select; =20 free_cfg_slot =3D ida_alloc_range(&st->cfg_slots_status, 0, st->info->num_configs - 1, GFP_KERNEL); @@ -649,8 +740,49 @@ static int ad7173_load_config(struct ad7173_state *st, if (ret) return ret; =20 + /* + * When SINC3_MAP flag is enabled, the rest of the register has a + * different meaning. We are using this option to allow the most + * possible sampling frequencies with SINC3 filter. + */ + if (cfg->filter_type =3D=3D AD7173_FILTER_SINC3) + return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, + FIELD_PREP(AD7173_FILTER_SINC3_MAP, 1) | + FIELD_PREP(AD7173_FILTER_SINC3_MAP_DIV, + cfg->sinc3_odr_div)); + + switch (cfg->filter_type) { + case AD7173_FILTER_SINC5_SINC1_PF1: + post_filter_enable =3D 1; + post_filter_select =3D 2; + break; + case AD7173_FILTER_SINC5_SINC1_PF2: + post_filter_enable =3D 1; + post_filter_select =3D 3; + break; + case AD7173_FILTER_SINC5_SINC1_PF3: + post_filter_enable =3D 1; + post_filter_select =3D 5; + break; + case AD7173_FILTER_SINC5_SINC1_PF4: + post_filter_enable =3D 1; + post_filter_select =3D 6; + break; + default: + post_filter_enable =3D 0; + post_filter_select =3D 0; + break; + } + return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2, - AD7173_FILTER_ODR0_MASK & cfg->sinc5_odr_index); + FIELD_PREP(AD7173_FILTER_SINC3_MAP, 0) | + FIELD_PREP(AD7173_FILTER_ENHFILT_MASK, + post_filter_enable) | + FIELD_PREP(AD7173_FILTER_ENHFILTEN, + post_filter_select) | + FIELD_PREP(AD7173_FILTER_ORDER, 0) | + FIELD_PREP(AD7173_FILTER_ODR_MASK, + cfg->sinc5_odr_index)); } =20 static int ad7173_config_channel(struct ad7173_state *st, int addr) @@ -1183,6 +1315,13 @@ static int ad7173_read_raw(struct iio_dev *indio_dev, return -EINVAL; } case IIO_CHAN_INFO_SAMP_FREQ: + if (st->channels[chan->address].cfg.filter_type =3D=3D AD7173_FILTER_SIN= C3) { + /* Inverse operation of ad7173_sinc3_odr_div_from_odr() */ + *val =3D MEGA; + *val2 =3D 3 * 32 * st->channels[chan->address].cfg.sinc3_odr_div; + return IIO_VAL_FRACTIONAL; + } + reg =3D st->channels[chan->address].cfg.sinc5_odr_index; =20 *val =3D st->info->sinc5_data_rates[reg] / MILLI; @@ -1221,6 +1360,10 @@ static int ad7173_write_raw(struct iio_dev *indio_de= v, * * This will cause the reading of CH1 to be actually done once every * 200.16ms, an effective rate of 4.99sps. + * + * Both the sinc5 and sinc3 rates are set here so that if the filter + * type is changed, the requested rate will still be set (aside from + * rounding differences). */ case IIO_CHAN_INFO_SAMP_FREQ: freq =3D val * MILLI + val2 / MILLI; @@ -1230,6 +1373,7 @@ static int ad7173_write_raw(struct iio_dev *indio_dev, =20 cfg =3D &st->channels[chan->address].cfg; cfg->sinc5_odr_index =3D i; + cfg->sinc3_odr_div =3D ad7173_sinc3_odr_div_from_odr(freq); cfg->live =3D false; break; =20 @@ -1246,17 +1390,40 @@ static int ad7173_update_scan_mode(struct iio_dev *= indio_dev, const unsigned long *scan_mask) { struct ad7173_state *st =3D iio_priv(indio_dev); + u16 sinc3_count =3D 0; + u16 sinc3_div =3D 0; int i, j, k, ret; =20 for (i =3D 0; i < indio_dev->num_channels; i++) { - if (test_bit(i, scan_mask)) + const struct ad7173_channel_config *cfg =3D &st->channels[i].cfg; + + if (test_bit(i, scan_mask)) { + if (cfg->filter_type =3D=3D AD7173_FILTER_SINC3) { + sinc3_count++; + + if (sinc3_div =3D=3D 0) { + sinc3_div =3D cfg->sinc3_odr_div; + } else if (sinc3_div !=3D cfg->sinc3_odr_div) { + dev_err(&st->sd.spi->dev, + "All enabled channels must have the same sampling_frequency for sinc= 3 filter_type\n"); + return -EINVAL; + } + } + ret =3D ad7173_set_channel(&st->sd, i); - else + } else { ret =3D ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0); + } if (ret < 0) return ret; } =20 + if (sinc3_count && sinc3_count < bitmap_weight(scan_mask, indio_dev->num_= channels)) { + dev_err(&st->sd.spi->dev, + "All enabled channels must have sinc3 filter_type\n"); + return -EINVAL; + } + /* * On some chips, there are more channels that setups, so if there were * more unique setups requested than the number of available slots, @@ -1415,6 +1582,7 @@ static const struct iio_chan_spec ad7173_temp_iio_cha= nnel_template =3D { .storagebits =3D 32, .endianness =3D IIO_BE, }, + .ext_info =3D ad7173_temp_chan_spec_ext_info, }; =20 static void ad7173_disable_regulators(void *data) @@ -1655,7 +1823,11 @@ static int ad7173_fw_parse_channel_config(struct iio= _dev *indio_dev) chan_st_priv->cfg.bipolar =3D false; chan_st_priv->cfg.input_buf =3D st->info->has_input_buf; chan_st_priv->cfg.ref_sel =3D AD7173_SETUP_REF_SEL_INT_REF; + chan_st_priv->cfg.sinc3_odr_div =3D ad7173_sinc3_odr_div_from_odr( + st->info->sinc5_data_rates[st->info->odr_start_value] + ); chan_st_priv->cfg.sinc5_odr_index =3D st->info->odr_start_value; + chan_st_priv->cfg.filter_type =3D AD7173_FILTER_SINC5_SINC1; chan_st_priv->cfg.openwire_comp_chan =3D -1; st->adc_mode |=3D AD7173_ADC_MODE_REF_EN; if (st->info->data_reg_only_16bit) @@ -1727,7 +1899,11 @@ static int ad7173_fw_parse_channel_config(struct iio= _dev *indio_dev) chan->scan_index =3D chan_index; chan->channel =3D ain[0]; chan_st_priv->cfg.input_buf =3D st->info->has_input_buf; + chan_st_priv->cfg.sinc3_odr_div =3D ad7173_sinc3_odr_div_from_odr( + st->info->sinc5_data_rates[st->info->odr_start_value] + ); chan_st_priv->cfg.sinc5_odr_index =3D st->info->odr_start_value; + chan_st_priv->cfg.filter_type =3D AD7173_FILTER_SINC5_SINC1; chan_st_priv->cfg.openwire_comp_chan =3D -1; =20 chan_st_priv->cfg.bipolar =3D fwnode_property_read_bool(child, "bipolar"= ); --=20 2.43.0 From nobody Thu Oct 2 18:17:40 2025 Received: from mail-oa1-f51.google.com (mail-oa1-f51.google.com [209.85.160.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776B83375AB for ; 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These chips have a few filter types that haven't been seen before in other drivers. Reviewed-by: Nuno S=C3=A1 Signed-off-by: David Lechner --- Documentation/ABI/testing/sysfs-bus-iio | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index 2fb2cea4b19249743398b1ff0b538b03ced0340b..845dd20aab78e5c7afbeb26ba04= c295a28aaafa2 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -2296,6 +2296,11 @@ Description: performance * "sinc5+avg" - Sinc5 + averaging by 4. * "sinc5+pf1" - Sinc5 + device specific Post Filter 1. + * "sinc5+sinc1" - Sinc5 + Sinc1. + * "sinc5+sinc1+pf1" - Sinc5 + Sinc1 + device specific Post Filter 1. + * "sinc5+sinc1+pf2" - Sinc5 + Sinc1 + device specific Post Filter 2. + * "sinc5+sinc1+pf3" - Sinc5 + Sinc1 + device specific Post Filter 3. + * "sinc5+sinc1+pf4" - Sinc5 + Sinc1 + device specific Post Filter 4. * "wideband" - filter with wideband low ripple passband and sharp transition band. =20 --=20 2.43.0