From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4112E301003; Fri, 12 Sep 2025 11:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676127; cv=none; b=pU7YOo45u7+VehxBEZT21mcUdd3wwGZY4OK0V7J85z05OY9s5RJWEm6J8TRMoksuYTIPuh8GrUqZBq5U+8fP+CjHDu6ut4gijJzpBhwp/qdiskiF4010HjtDYmhGQjmDzuWZDq8UnzDwLMylz8J8cvwTcQnKP4oM1cGe/jm043U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676127; c=relaxed/simple; bh=a7v6V+1etb8iiKXRjxUma/LMQuFjf/rSgVqbyq2ZhUg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M/Wcorl+Ko7tgf9cBOe8DsIUUeJS7wOUBhfATXVfnqwOcl6N8+SXeFeRJmDyUFh5D0krR5+7NOrIjSol2GCH8KmUhRsJL8lmUauGpax4WOqc8EhnARkKnuyrlUNncH4LDs2cpRJ2zX1bxANZB/EVQAX5i25PK6LmiR/DWITAze4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cuzy0Pok; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cuzy0Pok" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A234BC4CEF4; Fri, 12 Sep 2025 11:22:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757676126; bh=a7v6V+1etb8iiKXRjxUma/LMQuFjf/rSgVqbyq2ZhUg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Cuzy0Pok0pnKc3GOM8TfILUvN3zFNGTU81T85egu9IGbnz9wAD5TY+L8HQX0VDM7j ESRr0Fs1JEsxFppMDmtchO/4boSTPNNYTGzNmkWRZO5qd88yBlFX6pJcbeL6m3XpNW jfNmyncqV8AtfB4pg3LZ4Y8KQoiLXuyfXZEva3SiccJlSn4t+4umlSggt0aRiPsNBU pIaepVEGZ4caj0HdyFB+c4qfibVe3KBZecmA2SrG4O23NsAoanfmMpNpvLTsxI05mF euoVVXdLwF913xFQit2vdVvu1tjOMlV2Gpf4AQTaNzPFqljsMW3ZrlCgTMjtZRJw7C h1WXntA8WOu8A== From: Mark Brown Date: Fri, 12 Sep 2025 10:25:27 +0100 Subject: [PATCH v16 1/6] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-1-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=905; i=broonie@kernel.org; h=from:subject:message-id; bh=a7v6V+1etb8iiKXRjxUma/LMQuFjf/rSgVqbyq2ZhUg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJUhkh3JG/R0IYWg4xGHGXuPOIYtANMJtlNz GPNwWcl1t6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCVAAKCRAk1otyXVSH 0PtDB/99Zwm9Uj+D9vpqCwCG8A/mNEwCm8ll+dZs/C1WO8VuKkHRz3lQ7BCu/JNDC21jxnMGNX2 jNsYKkbVoIc1xhbggK84VQ+7733IRrQszs29I/vQML/rFjJCWgULRVDDegp3PxvfsTokwmsszj1 CWhVkaz8KxJtiFzd00LjQNe1uC7EEjfb7vwQZsjjAfJAZ3i9k0mpCdMsaRfSNVDbcc0NhlKZSW/ L3o0f7xJmMr05I0Q1Jk9tf5gviEfAepl1WOQIh9wMXPodqfj4I7pn0V96ZBV00G1KI66v4ydpw5 QMtgL4KrMF9wPxpcZ8vuwC/GHsRdP6FFom4YtRxAPcom4SaN X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. This is the first disabling of instruction traps, use x2 to store the value to be written. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 46033027510c..d174f405c44a 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -353,6 +353,11 @@ orr x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK orr x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK =20 + /* Disable traps of GCS instructions at EL1 */ + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK + .Lskip_gce_fgt_\@: =20 .Lset_fgt_\@: --=20 2.47.2 From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7F1D301468; Fri, 12 Sep 2025 11:22:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676129; cv=none; b=tTjJJ3kf2FuwF6p1CixwahJwN/niuN+ypOPsnfsNAa9wHKm7Y2PGMPusOjc1BqLG0V+kvZUeq69LNGKULgvzxVjSnUr4bZ7vWGxZnOA2Xq+wAmzgaETX+s9MiZHqP4WFM5jSAMB71HqXC2Q/MtjfpzsU18e87aTXl8V08Z21YQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676129; c=relaxed/simple; bh=2LP+NrUkvocLWMiaZqIiOZn5s9SWKLGthIDqKvxSRUE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JRE3bZi015CgfJLd4E6M/w6Yacsou3zA3y2IbJwlctfEITKyyQSjOcl1kxDgjHBAZCzE2+iMzCa+p5SkE5lSWwEsz2yoFriqIkrdoQVVrd7NDDqkIidu6D3Q/0Y2CTCY/12BseYkFPJd/koPcIE+17QXHASROIjhRb69XH2J3/g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CZXNzR7a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CZXNzR7a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4702AC4CEF1; Fri, 12 Sep 2025 11:22:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757676129; bh=2LP+NrUkvocLWMiaZqIiOZn5s9SWKLGthIDqKvxSRUE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CZXNzR7aw3amJzeBkhK/+v3UKMHKrKwB0vvcCho61AQUlJmu778NWBzKiNneckXD7 xbcPff+HN0sdIGvx48lyQuoGa96IhTYzN5rBz1hPfWXJOF2UUo2ZRGJiRMmw9Cys9g C5eYigs7hJl9VFiMffvEdINEMCWk3QRK8by2Sk81bAi39w8s+etUYkRR0e29UICqpn Y6YoE7yXdI1yWScIfiUCPAQn59IYVDTmnhn4kX+Nsd6Uo4fddSNXXjfhg7yFTSSZMV QMinxi71Uwjjrj+gnXqaI2efLeNRItJ/P3K+AwlimRHYD7p+hB4H3f1zA7mExSBDS/ XhBcUkPsl/Qig== From: Mark Brown Date: Fri, 12 Sep 2025 10:25:28 +0100 Subject: [PATCH v16 2/6] KVM: arm64: Manage GCS access and registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-2-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=10443; i=broonie@kernel.org; h=from:subject:message-id; bh=2LP+NrUkvocLWMiaZqIiOZn5s9SWKLGthIDqKvxSRUE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJV9xmTbNM/GgtGTPoGmoqbpfkD7eDgK4f4o /kl0n+KBeeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCVQAKCRAk1otyXVSH 0CWsB/4kh38JbA51qKAoNvmX8x+JxXLriljaT08E8u//ySZ8nK+hN/FhImhSdLEbt7EuZ7/EYTy ZpMw+63cczXNkIdmfO/pVzshGE9zx00y5z0PexJiGBrRPammyH4SJ0hN6UHdfnuKFu6oMm8X9xl 53eoM2DDNrBZJXce/gGh6IBuK4EFbxYhtJBuLg15DVFW5GkqNIxJw8T4ydzMY6FdrnA05zY1JwQ Ln8YimK6kKAxzUYAQqfHxVEECVHQ1NTVLKqxep0gOxEgMx0rHgJgjivhL9SoBqmmxSn1qbMRQDq DQMwyeHTMq3fTmE8b1wm0kEmR/fCGZDKV4hv69DMHsLH0D4h X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS introduces a number of system registers, on systems with GCS we need to context switch them and expose them to VMMs to allow guests to use GCS. In order to allow guests to use GCS we also need to configure HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and CHKFEAT will report GCS as disabled. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 3 +++ arch/arm64/include/asm/kvm_host.h | 14 ++++++++++++++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++= ++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 10 ++++++++++ arch/arm64/kvm/sys_regs.c | 30 ++++++++++++++++++++++++++= +++ 6 files changed, 90 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index fa8a08a1ccd5..9ab1e7616854 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -672,6 +672,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) =20 if (kvm_has_sctlr2(kvm)) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_SCTLR2En; + + if (kvm_has_gcs(kvm)) + vcpu->arch.hcrx_el2 |=3D HCRX_EL2_GCSEn; } } #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 2f2394cce24e..22a3fa9d97aa 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -480,6 +480,10 @@ enum vcpu_sysreg { =20 POR_EL0, /* Permission Overlay Register 0 (EL0) */ =20 + /* Guarded Control Stack registers */ + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ + /* FP/SIMD/SVE */ SVCR, FPMR, @@ -502,6 +506,8 @@ enum vcpu_sysreg { PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ PIR_EL2, /* Permission Indirection Register 1 (EL2) */ POR_EL2, /* Permission Overlay Register 2 (EL2) */ + GCSCR_EL2, /* Guarded Control Stack Control Register (EL2) */ + GCSPR_EL2, /* Guarded Control Stack Pointer Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -571,6 +577,10 @@ enum vcpu_sysreg { VNCR(VDISR_EL2), VNCR(VSESR_EL2), =20 + /* Guarded Control Stack registers */ + VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */ + VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */ + VNCR(HFGRTR_EL2), VNCR(HFGWTR_EL2), VNCR(HFGITR_EL2), @@ -1697,6 +1707,10 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_gcs(k) \ + (system_supports_gcs() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP)) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index f6ec500ad3fa..e9fac6218d44 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -95,6 +95,8 @@ #define VNCR_PMSIRR_EL1 0x840 #define VNCR_PMSLATFR_EL1 0x848 #define VNCR_TRFCR_EL1 0x880 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 #define VNCR_MPAMVPMV_EL2 0x938 diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index a17cbe7582de..053d7b3c5104 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -17,6 +17,7 @@ #include =20 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt); =20 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) { @@ -67,6 +68,11 @@ static inline void __sysreg_save_user_state(struct kvm_c= pu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL0) =3D read_sysreg_s(SYS_GCSPR_EL0); + ctxt_sys_reg(ctxt, GCSCRE0_EL1) =3D read_sysreg_s(SYS_GCSCRE0_EL1); + } } =20 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) @@ -131,6 +137,17 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_cont= ext *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!cpus_have_final_cap(ARM64_HAS_GCS)) + return false; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP); +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); @@ -144,6 +161,10 @@ static inline void __sysreg_save_el1_state(struct kvm_= cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { ctxt_sys_reg(ctxt, PIR_EL1) =3D read_sysreg_el1(SYS_PIR); ctxt_sys_reg(ctxt, PIRE0_EL1) =3D read_sysreg_el1(SYS_PIRE0); + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL1) =3D read_sysreg_el1(SYS_GCSPR); + ctxt_sys_reg(ctxt, GCSCR_EL1) =3D read_sysreg_el1(SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) @@ -206,6 +227,11 @@ static inline void __sysreg_restore_user_state(struct = kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_gcs(ctxt)) { + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), + SYS_GCSCRE0_EL1); + } } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, @@ -239,6 +265,11 @@ static inline void __sysreg_restore_el1_state(struct k= vm_cpu_context *ctxt, if (ctxt_has_s1pie(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); + + if (ctxt_has_gcs(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index f28c6cf4fe1b..e63b473d66d1 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -61,6 +61,11 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vc= pu) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, POR_EL2, read_sysreg_el1(SYS_POR)); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + __vcpu_assign_sys_reg(vcpu, GCSCR_EL2, read_sysreg_el1(SYS_GCSCR)); + __vcpu_assign_sys_reg(vcpu, GCSPR_EL2, read_sysreg_el1(SYS_GCSPR)); + } } =20 /* @@ -133,6 +138,11 @@ static void __sysreg_restore_vel2_state(struct kvm_vcp= u *vcpu) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) write_sysreg_el1(__vcpu_sys_reg(vcpu, POR_EL2), SYS_POR); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSCR_EL2), SYS_GCSCR); + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSPR_EL2), SYS_GCSPR); + } } =20 write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 82ffb3b3b3cf..03fb2dce0b80 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -138,6 +138,8 @@ static bool get_el2_to_el1_mapping(unsigned int reg, MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL ); MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); @@ -2654,6 +2656,21 @@ static unsigned int s1pie_el2_visibility(const struc= t kvm_vcpu *vcpu, return __el2_visibility(vcpu, rd, s1pie_visibility); } =20 +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + if (kvm_has_gcs(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int gcs_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, gcs_visibility); +} + static bool access_mdcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3048,6 +3065,13 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { PTRAUTH_KEY(APDB), PTRAUTH_KEY(APGA), =20 + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, { SYS_DESC(SYS_ELR_EL1), access_elr}, =20 @@ -3162,6 +3186,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0, + .visibility =3D gcs_visibility }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 @@ -3401,6 +3427,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, vncr_el2_visibility), =20 + EL2_REG_FILTERED(GCSCR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), + EL2_REG_FILTERED(GCSPR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), --=20 2.47.2 From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438BE301475; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-3-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=2696; i=broonie@kernel.org; h=from:subject:message-id; bh=tEz0LD0nUb9QTay3NFwM/E0GFA9eVx39ShtKmUAGyXA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJWddQLOEjGHb/JtftEpYebeUoHJGoEcvoG5 ShkXO/KPI+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCVgAKCRAk1otyXVSH 0H48B/9va91KX7b6kDAmSHI6tUF0WeXt2KY3rbl4XPPR26sekC9rtI55PVJC24OgB3abh1dgipT k56ImZy3+ESiRy+jbdsf2bwErO9SG48BotdjQUD1rikMG6hgmWLE82BgNqxCpSJLgkrZrhzSPXZ uoedrm26OTsxg0s46N9SEj6oicCb8ptm2DTjPJw3otdSEnRAiujowcSyAfbVz+NC/x4/bgyG3Bi Vl3p/Eo8vQ7UbvNR3YAigm/xlXcy8HQulHN28UtvYt82doKvi34pMNr0ZyIOACyu21FN+TsDNI/ UITfqlcprVQuKRIRv1WUTUYp+mWHCdnSRDrJY9jTRYlyZ5tM X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI 0487 R_WTXBY we need to manage PSTATE.EXLOCK when entering an exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64(). Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/hyp/exception.c | 37 ++++++++++++++++++++++++++++++++= ++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi= /asm/ptrace.h index 0f39ba4f3efd..f2fb029fb61a 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -56,6 +56,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000 =20 #define PSR_BTYPE_SHIFT 10 =20 diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 95d186e0bf54..888cea250dc2 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -73,6 +73,38 @@ static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu,= u64 val) vcpu->arch.ctxt.spsr_und =3D val; } =20 +static unsigned long compute_exlock(struct kvm_vcpu *vcpu, + unsigned long mode, + unsigned long target_mode) +{ + u64 gcscr; + + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm))) + return 0; + + /* GCS can't be enabled for 32 bit */ + if (mode & PSR_MODE32_BIT) + return 0; + + /* When taking an exception to a higher EL EXLOCK is cleared. */ + if ((mode | PSR_MODE_THREAD_BIT) !=3D target_mode) + return 0; + + /* + * When taking an exception to the same EL EXLOCK is set to + * the effective value of GCSR_ELx.EXLOCKEN. + */ + if (vcpu_is_el2(vcpu)) + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + if (gcscr & GCSCR_ELx_EXLOCKEN) + return PSR_EXLOCK_BIT; + + return 0; +} + /* * This performs the exception entry at a given EL (@target_mode), stashin= g PC * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTAT= E. @@ -162,6 +194,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, u= nsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. =20 + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 R_WTXBY. + new |=3D compute_exlock(vcpu, mode, target_mode); + new |=3D PSR_D_BIT; new |=3D PSR_A_BIT; new |=3D PSR_I_BIT; --=20 2.47.2 From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF8F43019C1; Fri, 12 Sep 2025 11:22:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676135; cv=none; b=ThcHkUiCkcl1pLIQrK2E5VaFuVoevvf9rgP/FJYwuyCuYflRRKV5zbof4yyrkTS4IEMG8fFNaOoyg7/zbpjFvam5EwAS4vT6n5OS+vYv83l/9rzldrgLk44iaWZza2i7b0UvKj16bi58/IyTMe+4Za7PM5oVBRkc/0J5lKYweo8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676135; c=relaxed/simple; bh=xaVskRKfvaYHjeBh7ZUg/Y9QZVgaF1sqMd02LaZ+I3g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Asiu8PFt3/JtSZgAyIZgb4W7TqXlxxYcMQDo+RT0cpS7HbhcG/i326qBQpwYhoaLwJWVabp5xAivEUCSa8kUJ2leEt8aidS0lWXWJxCJmdNXhqU3QGl1EoVU/BstfxlBmMgw590SxEKeYs7Fbjy5hB8TCwV3P/7STL/0Bnpxu3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lvb/I5NW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lvb/I5NW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89522C4CEF7; Fri, 12 Sep 2025 11:22:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757676134; bh=xaVskRKfvaYHjeBh7ZUg/Y9QZVgaF1sqMd02LaZ+I3g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=lvb/I5NWrp7HtvlplxuWpL2vNGssAA7pBilYGFeo9znUH28bTMemg3VODTUQ+KixA 72S3Fwd3PD340IhxFsPTo36Eh4pbAbBpFnDGRTGPYDTCJL6ve3P040yvjYtnuKTswm HFzzFeTvv956UFQwEq7V+QgqFxyC60+CpUy7uU58cWez5ZToInUtUl6sllDaeh4N3L CSnunXYlowbD6jMyBu+2vZAkotAiPdhwD1EHWwupDGZ+8MgIqU2M3InbVhtHpchobe x66WdnLa1ybUqom7AYwWtbkI2k0e5LyCWwlj+wRMtebuVovqWoo9xnELzWrKYLMfDe KUQmhR5WJKoEg== From: Mark Brown Date: Fri, 12 Sep 2025 10:25:30 +0100 Subject: [PATCH v16 4/6] KVM: arm64: Validate GCS exception lock when emulating ERET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-4-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=2656; i=broonie@kernel.org; h=from:subject:message-id; bh=xaVskRKfvaYHjeBh7ZUg/Y9QZVgaF1sqMd02LaZ+I3g=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJXCR4RyxPnfSQCG7eAvAVupSzVjrtMNwsGJ 6JUwuO6RhmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCVwAKCRAk1otyXVSH 0H5+B/9E8krfa7iOgqbgX6kd63Vmw1Uc5wEELqhQ42KmcIl9iZrDNCGP7GpjV3eHls/O7bCcH9n Rk8SxCyZl/k7lgtDSiyl7Kqtt+r9wvpuZFEDOKWfoIV+yDHHa5zKiEtCedUQyPAU/tBCQ8Er3jf 4QgXevDz+SIuD4yh66FtcZjq53tGrmXAFumQiSRx4IN1cTcU1a8kWwu5Jb1PyJFKTLVlR1P+Nl+ Uc0Gkz3591iMuMXASYuJJuHDLpyo8VwazmAXaf+VmK0xTiBQmAy/e0oGFdyxJtRuEt/8SUdzbzL ZR3xu0yw47Co2/+JqwE7U0TU7ociDovb5/zoSo+Bk6SHfNWi X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI0487 R_TYTWB GCS adds an additional case where an illegal exception return can be generated. If all of: - PSTATE.EXLOCK is 0. - The EL is not being changed by the ERET. - GCSCR_ELx.EXLOCKEN is 1. are true then the return is illegal. Emulate this behaviour when emulating ERET for nested guests. Signed-off-by: Mark Brown --- arch/arm64/kvm/emulate-nested.c | 40 +++++++++++++++++++++++++++++++++++++= ++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 90cb4b7ae0ff..9b02b85eda64 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2632,6 +2632,41 @@ bool forward_debug_exception(struct kvm_vcpu *vcpu) return forward_mdcr_traps(vcpu, MDCR_EL2_TDE); } =20 +/* + * A subset of the pseudocode ELFromSPSR(), validity checks are + * assumed to have been done in code that is not GCS specific. + */ +static inline int exlock_el_from_spsr(u64 spsr) +{ + return FIELD_GET(GENMASK(3, 2), spsr); +} + +/* See IllegalExceptionReturn() pseudocode */ +static bool kvm_check_illegal_exlock_return(struct kvm_vcpu *vcpu, u64 sps= r) +{ + u64 cur_el, target_el; + u64 gcscr; + + if (!kvm_has_gcs(vcpu->kvm)) + return false; + + if (spsr & PSR_EXLOCK_BIT) + return false; + + cur_el =3D exlock_el_from_spsr(vcpu->arch.ctxt.regs.pstate); + target_el =3D exlock_el_from_spsr(spsr); + + if (cur_el !=3D target_el) + return false; + + if (vcpu_is_el2(vcpu)) + gcscr =3D __vcpu_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D __vcpu_sys_reg(vcpu, GCSCR_EL1); + + return gcscr & GCSCR_ELx_EXLOCKEN; +} + static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 s= psr) { u64 mode =3D spsr & PSR_MODE_MASK; @@ -2642,12 +2677,15 @@ static u64 kvm_check_illegal_exception_return(struc= t kvm_vcpu *vcpu, u64 spsr) * - trying to return to an illegal M value * - trying to return to a 32bit EL * - trying to return to EL1 with HCR_EL2.TGE set + * - GCSCR_ELx.EXLOCKEN is 1 and PSTATE.EXLOCK is 0 when attempting + * to return from ELx the same EL. */ if (mode =3D=3D PSR_MODE_EL3t || mode =3D=3D PSR_MODE_EL3h || mode =3D=3D 0b00001 || (mode & BIT(1)) || (spsr & PSR_MODE32_BIT) || (vcpu_el2_tge_is_set(vcpu) && (mode =3D=3D PSR_MODE_EL1t || - mode =3D=3D PSR_MODE_EL1h))) { + mode =3D=3D PSR_MODE_EL1h)) || + kvm_check_illegal_exlock_return(vcpu, spsr)) { /* * The guest is playing with our nerves. Preserve EL, SP, * masks, flags from the existing PSTATE, and set IL. --=20 2.47.2 From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDAC0302754; Fri, 12 Sep 2025 11:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676137; cv=none; b=TuONo+Ji5Fi/vW6I88LlAYrCQrjVeEbVUgcjWOV53w9j+VOoTrVMf8LBgz496Omw/Ty/w3AML+sx7u5kdfBONlN+TdgmGBd7WJVDPQt4zBFqi2TP3NlQ3JJNkiwusR3+R9SmRv5fqUuudZl4DioPBUtpBGM/kT2Pj/Ur95zX8kM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757676137; c=relaxed/simple; bh=IeBrm10npHswatwOwtRAuiaKWaoJBlDnxxV0/8Ycbl8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YNaAat07yumcJCY43gMt7Dy2OVCpijmQJhh7Dv//ZRyQm9SieciZe6f+n/FDePr7QmL596VfZDd0UFwIkx3beAWBEp91xneA00oGulvARO6magaM/bBP3UUr+s08QbSBHLiFrDh/c/ttFII0keGxpiwqdMI81GUFVKrztgpYHOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h7U9Zx/6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h7U9Zx/6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 356F2C4CEFD; Fri, 12 Sep 2025 11:22:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757676137; bh=IeBrm10npHswatwOwtRAuiaKWaoJBlDnxxV0/8Ycbl8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=h7U9Zx/6aHXAM+5tj6gtPPv0G2aF8WwSGMYHqWTwTkFcejHy6ZqvlTQeqkpGpMBkg rEt+ZG2DqRiuxj/oVnUUkrTReuxciNyZqzHqDZHZSJmlnoahTTq3jI6kncqJpHwvLD ZSrFteZwKViocvHRfODMN1DjklciUy/lO01cZfzCtCypTUxjHC4hJHSan4f2JftKW2 xsvUfTo9AdDmB1P5KSwFcYLXxWQMmqVxdXc3UfZp2VoNgsjs0VMcdNn9bRiRhEjfsT czqAnnPYAhS4QN6gao5KI2h/fst2jI6POG0dAiR3MXU33wtNgktbyRymQbeGkvs04X wwFUo0TzoNikw== From: Mark Brown Date: Fri, 12 Sep 2025 10:25:31 +0100 Subject: [PATCH v16 5/6] KVM: arm64: Allow GCS to be enabled for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-5-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=1883; i=broonie@kernel.org; h=from:subject:message-id; bh=IeBrm10npHswatwOwtRAuiaKWaoJBlDnxxV0/8Ycbl8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJYbjs1gu8XoeJOTzmWGxk48gJgJmlcEt1sN LwCLyb43WGJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCWAAKCRAk1otyXVSH 0DPMB/9fvrbX2YUDNAXM4i/lFcz1NafZgkZpthkn7QrwZjcoEKj96jMloLwbl6pBdb3E5fIWVe1 PqCU5ujWX3mUMkpgrumSskfoO7VKMqjfm5GwxEdgY9bRU35oDo2rirXZRyecfQUgqLq1DhObN+q ZAWp0lrURcA2PwCz0om5Plb1b9zv0b2TZZ/HkrjQaLQfXZajz+f+t1EeJcEzKqfgOHfR1zh9+dU fsVZNXsSdG78RUOtsHZfkDYf2iMXoIrYgHhVM977K6cZC7P/m4vpAUujBf1YnmHPZstLLKoTfZ5 kbqadCyXSCm/NLJ8xibHuaCqiIwoi6otcOWdEwlmYk2BWidZ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that required functionality for GCS is in place expose ID_AA64PFR1_EL1.GCS, allowing guests to be given the feature. Signed-off-by: Mark Brown --- arch/arm64/kvm/nested.c | 7 ++++--- arch/arm64/kvm/sys_regs.c | 2 -- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 153b3e11b115..d2d55e18c610 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1459,9 +1459,10 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 va= l) =20 case SYS_ID_AA64PFR1_EL1: /* Only support BTI, SSBS, CSV2_frac */ - val &=3D (ID_AA64PFR1_EL1_BT | - ID_AA64PFR1_EL1_SSBS | - ID_AA64PFR1_EL1_CSV2_frac); + val &=3D (ID_AA64PFR1_EL1_BT | + ID_AA64PFR1_EL1_SSBS | + ID_AA64PFR1_EL1_CSV2_frac | + ID_AA64PFR1_EL1_GCS); break; =20 case SYS_ID_AA64MMFR0_EL1: diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 03fb2dce0b80..60e234422064 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1616,7 +1616,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct k= vm_vcpu *vcpu, val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); - val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); @@ -2953,7 +2952,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | --=20 2.47.2 From nobody Thu Oct 2 19:03:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67CEE302CB2; Fri, 12 Sep 2025 11:22:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Fri, 12 Sep 2025 11:22:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757676140; bh=2Z09lyzr3mlySMGqqjLAI9Q8pohqjxnIJ8nt0XVxnnw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L34ZYKvkzUB5+9nv8Ow5OWUHNFysI8goeM6YczMJs91QTuZ9ENhdQBw/sQZxbcqIA GGj0FoaBJlU+Apn+Ir0QqMi0GIx3V2TWDtYMsJruNdyPq6fOqEbAjx7rcQKsBL4eB1 ZfAJbaAPcf3GMZbfEsEvUk5Jj0DDZ6JTNOecVh3+BDkQLJjcF773MbmzCwCxMjxqhC TG5dd72VwSu7XRSYD0qKQzSZ+du6M4Hsfpq/uXQ/VcdSndSUevVNIBaR6ryzK3pNld NUkps7GD7ZPpazktK1Lm6xQVSu4UeJVJtUF2+0u/5o0BsfelP33i5UfMQcHxmHzpJO uEEFna+EHHPWQ== From: Mark Brown Date: Fri, 12 Sep 2025 10:25:32 +0100 Subject: [PATCH v16 6/6] KVM: selftests: arm64: Add GCS registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250912-arm64-gcs-v16-6-6435e5ec37db@kernel.org> References: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> In-Reply-To: <20250912-arm64-gcs-v16-0-6435e5ec37db@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , Thiago Jung Bauermann X-Mailer: b4 0.15-dev-56183 X-Developer-Signature: v=1; a=openpgp-sha256; l=2417; i=broonie@kernel.org; h=from:subject:message-id; bh=2Z09lyzr3mlySMGqqjLAI9Q8pohqjxnIJ8nt0XVxnnw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBoxAJY4+SLnStXXvVFpBNYWlP1+VGHPxHvlmN6M z611HojkTCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaMQCWAAKCRAk1otyXVSH 0CORB/97WmwBUUlxAL6LjWlqWHp9V44CpCGTC8Lhk6gOOTvNi+TUCs5aGaKAmuFUa6SKHkaOBSF EKWdDn7SfL8jcvcmmZu0fRFASR0rW40r76P/++ZuDCMg1UJhJAtQ8PENu/BIsrwqpjsyVoCsmyJ kTsrJZQkxq5KFPxlIVNtb85ZEaLZEV5IN+y5tLS0jVoN7drGvdySNw56qL+pfuwJTmpzfYRahF+ nkLZR9oDmz6oCZoMui8A5bj0hErIFgI/AHAgYXUULilLRnwZ32rMPmmfSuKzXnt3Gp3A/dWTmHa BJHd3LjzUSlDY50YlZs6fq3uO0Jy5Vi7H7qbcCd9ny+3TQuK X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add these to those validated by get-reg-list. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testi= ng/selftests/kvm/arm64/get-reg-list.c index 011fad95dd02..9bf33064377b 100644 --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c @@ -42,6 +42,12 @@ struct feature_id_reg { static struct feature_id_reg feat_id_regs[] =3D { REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), + REG_FEAT(GCSPR_EL0, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL2, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCRE0_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL2, ID_AA64PFR1_EL1, GCS, IMP), REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), @@ -486,6 +492,9 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ @@ -502,6 +511,7 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ @@ -740,6 +750,8 @@ static __u64 el2_regs[] =3D { SYS_REG(PIRE0_EL2), SYS_REG(PIR_EL2), SYS_REG(POR_EL2), + SYS_REG(GCSPR_EL2), + SYS_REG(GCSCR_EL2), SYS_REG(AMAIR_EL2), SYS_REG(VBAR_EL2), SYS_REG(CONTEXTIDR_EL2), --=20 2.47.2