From nobody Thu Oct 2 19:30:11 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B2D131354D; Fri, 12 Sep 2025 15:41:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757691670; cv=none; b=rPqE0KXhIjEe5uAvhlNYLJ5ucqNnajUP36AXa2zz0LIEVvVzQK+3K3fPpUjcPxSf1WbztIBrKkzV6CQfho+cgz2SrviQKuSZiu0IpfuzKHnzx/pwXAuKcyQ0TAaQMNXZDZ9cEcSnu+AtY78IjbSVoHd77Gz5cYaccf5EA5i49n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757691670; c=relaxed/simple; bh=Z7v519uWdUo89ZiHiNFDw2c32jxqAA9Bj+scBdD1a7g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=A1SeLRldJgXaFOj6sDuz0e+xw1XJzV8/NWJPvoAHaeZjwMiQ4xSC8IiX/BQ956iEb5PLcSDXzzn1+K9l7gWE2vdgXBgfFyReWezlprXvo807chGhzPMmyUV0jkKiN0Uozf4iOGKRrynGavZ3zcDl1PX4IzJaV5+XRJagwYiHeMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=T0QVICwo; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="T0QVICwo" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 58CFeiiZ1062316; Fri, 12 Sep 2025 10:40:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757691644; bh=YhabVYyzSOeYvEJDGB2G48jRn5HpsYcJMnGseYW00zI=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=T0QVICwo9BsStIcsr+8L+wtsPel/6HhuEEcifQMExVVEUII6J3m45Xi2b21U3eduE ZwJ1pAWhILzgtUlfjnUtJ5eWS8vdbfVr35HAuCGuW/YJIaKdharE/F3HRYFpDBC5hE AK849tfXOatVufzINo38Il77hd5WyLH6hvS0zpbI= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 58CFeifP2870515 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 12 Sep 2025 10:40:44 -0500 Received: from DLEE214.ent.ti.com (157.170.170.117) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 12 Sep 2025 10:40:43 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE214.ent.ti.com (157.170.170.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Fri, 12 Sep 2025 10:40:43 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58CFehPP3820088; Fri, 12 Sep 2025 10:40:43 -0500 From: Bryan Brattlof Date: Fri, 12 Sep 2025 10:40:43 -0500 Subject: [PATCH v6 4/4] arm64: dts: ti: k3-am62l: add initial reference board file Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250912-am62lx-v6-4-29d5a6c60512@ti.com> References: <20250912-am62lx-v6-0-29d5a6c60512@ti.com> In-Reply-To: <20250912-am62lx-v6-0-29d5a6c60512@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Andrew Davis , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Tony Lindgren CC: , , , Sascha Hauer , , Bryan Brattlof X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10522; i=bb@ti.com; h=from:subject:message-id; bh=rZENMQ5wn18nV0zmN4TDUC16o97lMtvclVHm5b8BTU4=; b=owNCWmg5MUFZJlNZVMs/hAAAaX///r79yq/sfn/texX//c+v871/961Xbeb/Zu7vrzPH7t+wA RtqB2oAAGgAAANAABkAA0BoGmQGQNNDBAAGCNMjRpoZAep5TQYjRo0w9KIMTJ6hoGjQxDQ0AaDI YQ0AAD1AANGhoNDaBMQ9QaBobSGQ0AYmgaaAaAaaHCaMTIMRiZDTJkAYJoxDQGjQaAAGACMgYhg jQAAANGgGmEAAAAECfIclVR4W7g4gS2FZVADmpgKUBBwGmMhhgLp4iiWoegeDEFj0xK66OSB1AZ 0yAF6YsyRtlpKL6pzu/herhNsEyAgZDZtJaIQRh9VMXENp9EQICjDpytzrB/hWUhQxxdilQ9bU0 LVJhlqk6bp8bmFTm5wZO1kpW0vnDbVGxUCbs1Dys4omCLBsBaFQCVwOf+xwjn25HvM5hHwy2x6O fOBwEe7qoVAT20SYhRPrnhPsvldG4CLaHAMZh5XBkhBOoCsMr0qupgWMTTETz9/lbbfUOT8BYIp xH9AJ6WFRCzOcvVwCaNGZfrREnFD01Jo6vON27L1q0pdAvYDj/sUX1D09+6yZR1MeyE9AUX4FwK GgLIwFkz4CBFuebDW6TvCMj3G/sipf1yAS/tog4afA+R0UiOJdtYHiErcOUGhZjPAEQO7pVDf4u 5IpwoSCpln8IA== X-Developer-Key: i=bb@ti.com; a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea From: Vignesh Raghavendra Add the initial board file for the AM62L3's Evaluation Module. Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes from v1: - switched to non-direct links so TRM updates are automatic - removed current-speed property from main_uart0 - removed empty reserved-memory{} node - removed serial2 from aliases{} node - corrected main_uart0 pinmux Changes from v2: - alphabetized phandles - corrected macros and node names for main_uart0 pinmux node Changes from v3: - added and enabled more nodes that have been validated - added link to data sheet which is now public Changes in v4: - Corrected Copyright year --- arch/arm64/boot/dts/ti/Makefile | 3 + arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 345 +++++++++++++++++++++++++++= ++++ 2 files changed, 348 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index aad9177930e6fc8ade9432a9487e55b53d1e4763..a05cc096b6716e2ab245a8e26ad= 1f5c3a3142632 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -36,6 +36,9 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb # Boards with AM62Dx SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62d2-evm.dtb =20 +# Boards with AM62Lx SoCs +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62l3-evm.dtb + # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62l3-evm.dts new file mode 100644 index 0000000000000000000000000000000000000000..1df76844c1900d4829ee5d5444b= 129e72b479390 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 Evaluation Module + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + * Data Sheet: https://www.ti.com/lit/pdf/sprspa1 + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible =3D "ti,am62l3-evm", "ti,am62l3"; + model =3D "Texas Instruments AM62L3 Evaluation Module"; + + chosen { + stdout-path =3D &uart0; + }; + + memory@80000000 { + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type =3D "memory"; + bootph-all; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + autorepeat; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_button_pins_default>; + + usr: button-usr { + label =3D "User Key"; + linux,code =3D ; + gpios =3D <&gpio0 90 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usr_led_pins_default>; + + led-0 { + label =3D "am62-sk:green:heartbeat"; + gpios =3D <&gpio0 123 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + default-state =3D "on"; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_sys: regulator-1 { + /* output of LM61460-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-2 { + /* TPS22918DBVR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vcc_3v3_sys>; + gpio =3D <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_1v8: regulator-3 { + /* output of TPS6282518DMQ */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&gpio0 { + status =3D "okay"; + bootph-all; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins_default>; + clock-frequency =3D <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible =3D "atmel,24c512"; + reg =3D <0x51>; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + + exp1: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "", "", + "UART1_FET_SEL", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_EN", + "UART1_FET_BUF_EN", "", "", + "", "DSI_GPIO0", "DSI_GPIO1", + "", "BT_UART_WAKE_SOC_3V3", + "USB_TYPEA_OC_INDICATION", "", + "", "WLAN_ALERTn", "", "", + "HDMI_INTn", "TEST_GPIO2", + "MCASP0_FET_EN", "MCASP0_BUF_BT_EN", + "MCASP0_FET_SEL", "DSI_EDID", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <91 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio0_ioexp_intr_pins_default>; + bootph-all; + }; + + exp2: gpio@23 { + compatible =3D "ti,tca6424"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "BT_EN_SOC", "VOUT0_FET_SEL0", + "", "", + "", "", + "", "", + "WL_LT_EN", "EXP_PS_5V0_EN", + "TP45", "TP48", + "TP46", "TP49", + "TP47", "TP50", + "GPIO_QSPI_NAND_RSTn", "GPIO_HDMI_RSTn", + "GPIO_CPSW1_RST", "GPIO_CPSW2_RST", + "", "GPIO_AUD_RSTn", + "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST"; + bootph-all; + }; + +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + typec_pd0: tps658x@3f { + compatible =3D "ti,tps6598x"; + reg =3D <0x3f>; + + connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + self-powered; + data-role =3D "dual"; + power-role =3D "sink"; + + port { + usb_con_hs: endpoint { + remote-endpoint =3D <&usb0_hs_ep>; + }; + }; + }; + }; +}; + +&pmx0 { + gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */ + >; + bootph-all; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + bootph-all; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + bootph-all; + }; + + i2c2_pins_default: i2c2-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01dc, PIN_INPUT_PULLUP, 0) /* (B8) I2C2_SCL */ + AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */ + >; + }; + + mmc0_pins_default: mmc0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0214, PIN_INPUT_PULLUP, 0) /* (D2) MMC0_CMD */ + AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */ + AM62LX_IOPAD(0x0208, PIN_INPUT_PULLUP, 0) /* (D3) MMC0_DAT0 */ + AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */ + AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */ + AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */ + AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */ + AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */ + AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */ + AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */ + >; + bootph-all; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ + >; + bootph-all; + }; + + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + bootph-all; + }; + + usb1_default_pins: usb1-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP,= 0) /* (A5) USB1_DRVVBUS */ + >; + }; + + usr_button_pins_default: usr-button-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */ + >; + }; + + usr_led_pins_default: usr-led-default-pins { + pinctrl-single,pins =3D < + AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */ + >; + }; + +}; + +&sdhci0 { + /* eMMC */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins_default>; + non-removable; + status =3D "okay"; + bootph-all; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins_default>; + vmmc-supply =3D <&vdd_mmc1>; + disable-wp; + status =3D "okay"; + bootph-all; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + bootph-all; +}; + +&usbss0 { + status =3D "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&usbss1 { + status =3D "okay"; + ti,vbus-divider; +}; + +&usb1 { + dr-mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb1_default_pins>; +}; --=20 2.50.1