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ALl of which can be found in the Technical Reference Manual (TRM) located here: https://www.ti.com/lit/pdf/sprujb4 Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- Changes in v4: - Corrected Copyright year - Used 'ranges' property in the fss{} node Changes in v3: - Added more nodes now that the SCMI interface is ready Changes in v1: - switched to non-direct links to TRM updates are automatic - fixed white space indent issues with a few nodes - separated out device tree bindings --- arch/arm64/boot/dts/ti/k3-am62l-main.dtsi | 603 +++++++++++++++++++++++= ++++ arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi | 25 ++ arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi | 141 +++++++ arch/arm64/boot/dts/ti/k3-am62l.dtsi | 120 ++++++ arch/arm64/boot/dts/ti/k3-am62l3.dtsi | 67 +++ arch/arm64/boot/dts/ti/k3-pinctrl.h | 2 + 6 files changed, 958 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62l-main.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..229c34f23d1625e9c38bcf6db96= 2c86eb17b16c1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L main domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + #interrupt-cells =3D <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts =3D ; + + gic_its: msi-controller@1820000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its =3D <0x1000000 0x400000>; + msi-controller; + #msi-cells =3D <1>; + }; + }; + + gpio0: gpio@600000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 34>; + clocks =3D <&scmi_clk 140>; + clock-names =3D "gpio"; + ti,ngpio =3D <126>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + gpio2: gpio@610000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 35>; + clocks =3D <&scmi_clk 141>; + clock-names =3D "gpio"; + ti,ngpio =3D <79>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + timer0: timer@2400000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2400000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 58>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 15>; + ti,timer-pwm; + }; + + timer1: timer@2410000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2410000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 63>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 16>; + ti,timer-pwm; + }; + + timer2: timer@2420000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2420000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 77>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 17>; + ti,timer-pwm; + }; + + timer3: timer@2430000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2430000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 82>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 18>; + ti,timer-pwm; + }; + + uart0: serial@2800000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02800000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 89>; + clocks =3D <&scmi_clk 358>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart1: serial@2810000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02810000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 77>; + clocks =3D <&scmi_clk 312>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart2: serial@2820000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02820000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 78>; + clocks =3D <&scmi_clk 314>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart3: serial@2830000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02830000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 79>; + clocks =3D <&scmi_clk 316>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart4: serial@2840000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02840000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 80>; + clocks =3D <&scmi_clk 318>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart5: serial@2850000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02850000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 81>; + clocks =3D <&scmi_clk 320>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + uart6: serial@2860000 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x02860000 0x00 0x100>; + interrupts =3D ; + power-domains =3D <&scmi_pds 82>; + clocks =3D <&scmi_clk 322>; + clock-names =3D "fclk"; + status =3D "disabled"; + }; + + conf: bus@9000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x00 0x00 0x09000000 0x380000>; + + phy_gmii_sel: phy@1be000 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x1be000 0x8>; + #phy-cells =3D <1>; + }; + + epwm_tbclk: clock-controller@1e9100 { + compatible =3D "ti,am62-epwm-tbclk"; + reg =3D <0x1e9100 0x4>; + #clock-cells =3D <1>; + }; + }; + + usbss0: dwc3-usb@f900000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f900000 0x00 0x800>, + <0x00 0x0f908000 0x00 0x400>; + clocks =3D <&scmi_clk 331>; + clock-names =3D "ref"; + ti,syscon-phy-pll-refclk =3D <&usb_phy_ctrl 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&scmi_pds 95>; + ranges; + status =3D "disabled"; + + usb0: usb@31000000 { + compatible =3D "snps,dwc3"; + reg =3D <0x00 0x31000000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + usbss1: dwc3-usb@f910000 { + compatible =3D "ti,am62-usb"; + reg =3D <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks =3D <&scmi_clk 338>; + clock-names =3D "ref"; + ti,syscon-phy-pll-refclk =3D <&usb_phy_ctrl 0x4>; + #address-cells =3D <2>; + #size-cells =3D <2>; + power-domains =3D <&scmi_pds 96>; + ranges; + status =3D "disabled"; + + usb1: usb@31100000 { + compatible =3D "snps,dwc3"; + reg =3D <0x00 0x31100000 0x00 0x50000>; + interrupts =3D , /* irq.0 */ + ; /* irq.0 */ + interrupt-names =3D "host", "peripheral"; + maximum-speed =3D "high-speed"; + dr_mode =3D "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; + + sdhci1: mmc@fa00000 { + compatible =3D "ti,j721e-sdhci-4bit"; + reg =3D <0x00 0x0fa00000 0x00 0x1000>, + <0x00 0x0fa08000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 26>; + clocks =3D <&scmi_clk 106>, <&scmi_clk 109>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 109>; + bus-width =3D <4>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-legacy =3D <0x0>; + status =3D "disabled"; + }; + + sdhci0: mmc@fa10000 { + compatible =3D "ti,am62-sdhci"; + reg =3D <0x00 0xfa10000 0x00 0x1000>, + <0x00 0xfa18000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 28>; + clocks =3D <&scmi_clk 122>, <&scmi_clk 125>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 125>; + bus-width =3D <8>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,otap-del-sel-mmc-hs =3D <0x0>; + ti,otap-del-sel-hs200 =3D <0x6>; + status =3D "disabled"; + }; + + sdhci2: mmc@fa20000 { + compatible =3D "ti,am62-sdhci"; + reg =3D <0x00 0x0fa20000 0x00 0x1000>, + <0x00 0x0fa28000 0x00 0x400>; + interrupts =3D ; + power-domains =3D <&scmi_pds 27>; + clocks =3D <&scmi_clk 114>, <&scmi_clk 117>; + clock-names =3D "clk_ahb", "clk_xin"; + assigned-clocks =3D <&scmi_clk 117>; + bus-width =3D <4>; + ti,clkbuf-sel =3D <0x7>; + ti,otap-del-sel-legacy =3D <0x0>; + ti,itap-del-sel-legacy =3D <0x0>; + status =3D "disabled"; + }; + + i2c0: i2c@20000000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20000000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 53>; + clocks =3D <&scmi_clk 246>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + i2c1: i2c@20010000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20010000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 54>; + clocks =3D <&scmi_clk 250>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + i2c2: i2c@20020000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20020000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 55>; + clocks =3D <&scmi_clk 254>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + i2c3: i2c@20030000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x20030000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 56>; + clocks =3D <&scmi_clk 258>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + mcan0: can@20701000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 47>; + clocks =3D <&scmi_clk 179>, <&scmi_clk 178>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + mcan1: can@20711000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20711000 0x00 0x200>, + <0x00 0x20718000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 48>; + clocks =3D <&scmi_clk 185>, <&scmi_clk 184>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + mcan2: can@20721000 { + compatible =3D "bosch,m_can"; + reg =3D <0x00 0x20721000 0x00 0x200>, + <0x00 0x20728000 0x00 0x8000>; + reg-names =3D "m_can", "message_ram"; + power-domains =3D <&scmi_pds 49>; + clocks =3D <&scmi_clk 191>, <&scmi_clk 190>; + clock-names =3D "hclk", "cclk"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; + status =3D "disabled"; + }; + + spi0: spi@20100000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x20100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 72>; + clocks =3D <&scmi_clk 299>; + status =3D "disabled"; + }; + + spi1: spi@20110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 73>; + clocks =3D <&scmi_clk 302>; + status =3D "disabled"; + }; + + spi2: spi@20120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 74>; + clocks =3D <&scmi_clk 305>; + status =3D "disabled"; + }; + + spi3: spi@20130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x20130000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 75>; + clocks =3D <&scmi_clk 308>; + status =3D "disabled"; + }; + + epwm0: pwm@23000000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg =3D <0x00 0x23000000 0x00 0x100>; + power-domains =3D <&scmi_pds 40>; + clocks =3D <&epwm_tbclk 0>, <&scmi_clk 164>; + clock-names =3D "tbclk", "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + epwm1: pwm@23010000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg =3D <0x00 0x23010000 0x00 0x100>; + power-domains =3D <&scmi_pds 41>; + clocks =3D <&epwm_tbclk 1>, <&scmi_clk 165>; + clock-names =3D "tbclk", "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + epwm2: pwm@23020000 { + compatible =3D "ti,am64-epwm", "ti,am3352-ehrpwm"; + reg =3D <0x00 0x23020000 0x00 0x100>; + power-domains =3D <&scmi_pds 42>; + clocks =3D <&epwm_tbclk 2>, <&scmi_clk 166>; + clock-names =3D "tbclk", "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + ecap0: pwm@23100000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23100000 0x00 0x100>; + power-domains =3D <&scmi_pds 23>; + clocks =3D <&scmi_clk 99>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + ecap1: pwm@23110000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23110000 0x00 0x100>; + power-domains =3D <&scmi_pds 24>; + clocks =3D <&scmi_clk 100>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + ecap2: pwm@23120000 { + compatible =3D "ti,am3352-ecap"; + reg =3D <0x00 0x23120000 0x00 0x100>; + power-domains =3D <&scmi_pds 25>; + clocks =3D <&scmi_clk 101>; + clock-names =3D "fck"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + eqep0: counter@23200000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23200000 0x00 0x100>; + power-domains =3D <&scmi_pds 29>; + clocks =3D <&scmi_clk 127>; + interrupts =3D ; + status =3D "disabled"; + }; + + eqep1: counter@23210000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23210000 0x00 0x100>; + power-domains =3D <&scmi_pds 30>; + clocks =3D <&scmi_clk 128>; + interrupts =3D ; + status =3D "disabled"; + }; + + eqep2: counter@23220000 { + compatible =3D "ti,am62-eqep"; + reg =3D <0x00 0x23220000 0x00 0x100>; + power-domains =3D <&scmi_pds 31>; + clocks =3D <&scmi_clk 129>; + interrupts =3D ; + status =3D "disabled"; + }; + + elm0: ecc@25010000 { + compatible =3D "ti,am64-elm"; + reg =3D <0x00 0x25010000 0x00 0x2000>; + interrupts =3D ; + power-domains =3D <&scmi_pds 25>; + clocks =3D <&scmi_clk 102>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + dss: display@30200000 { + compatible =3D "ti,am62l-dss"; + reg =3D <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1 */ + <0x00 0x30201000 0x00 0x1000>; /* common1 */ + reg-names =3D "common", "vidl1", "ovr1", "vp1", "common1"; + power-domains =3D <&scmi_pds 39>; + clocks =3D <&scmi_clk 162>, + <&scmi_clk 161>; + clock-names =3D "fck", "vp1"; + interrupts =3D ; + status =3D "disabled"; + + dss_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + gpmc0: memory-controller@3b000000 { + compatible =3D "ti,am64-gpmc"; + power-domains =3D <&scmi_pds 37>; + clocks =3D <&scmi_clk 149>; + clock-names =3D "fck"; + reg =3D <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; + reg-names =3D "cfg", "data"; + interrupts =3D ; + gpmc,num-cs =3D <3>; + gpmc,num-waitpins =3D <2>; + #address-cells =3D <2>; + #size-cells =3D <1>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; + + oc_sram: sram@70800000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x70800000 0x00 0x10000>; + ranges =3D <0x00 0x00 0x70800000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + scmi_shmem: sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x00 0x100>; + bootph-all; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi b/arch/arm64/boot= /dts/ti/k3-am62l-thermal.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..4804c24d56748067ff27acbc825= 9e6d4306109a6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-thermal.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62L Bangap Sensors + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +thermal_zones: thermal-zones { + thermal0: thermal0 { + polling-delay-passive =3D <250>; /* milliSeconds */ + polling-delay =3D <500>; /* milliSeconds */ + thermal-sensors =3D <&vtm0 0>; + + trips { + crit0: crit0 { + temperature =3D <125000>; /* milliCelsius */ + hysteresis =3D <2000>; /* milliCelsius */ + type =3D "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62l-wakeup.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a0ab21a378e48da4b28a8dbb9a1= 0e98b74b89614 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L wakeup domain peripherals + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include + +&cbass_wakeup { + vtm0: temperature-sensor@b00000 { + compatible =3D "ti,j7200-vtm"; + reg =3D <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains =3D <&scmi_pds 46>; + #thermal-sensor-cells =3D <1>; + }; + + pmx0: pinctrl@4084000 { + compatible =3D "ti,am62l-padconf", "pinctrl-single"; + reg =3D <0x00 0x4084000 0x00 0x24c>; + pinctrl-single,register-width =3D <32>; + pinctrl-single,function-mask =3D <0xffffffff>; + #pinctrl-cells =3D <1>; + }; + + wkup_gpio0: gpio@4201000 { + compatible =3D "ti,am64-gpio", "ti,keystone-gpio"; + reg =3D <0x00 0x04201000 0x00 0x100>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-parent =3D <&gic500>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells =3D <2>; + power-domains =3D <&scmi_pds 36>; + clocks =3D <&scmi_clk 146>; + clock-names =3D "gpio"; + ti,ngpio =3D <7>; + ti,davinci-gpio-unbanked =3D <0>; + status =3D "disabled"; + }; + + wkup_timer0: timer@2b100000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2b100000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 93>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 19>; + ti,timer-pwm; + }; + + wkup_timer1: timer@2b110000 { + compatible =3D "ti,am654-timer"; + reg =3D <0x00 0x2b110000 0x00 0x400>; + interrupts =3D ; + clocks =3D <&scmi_clk 98>; + clock-names =3D "fck"; + power-domains =3D <&scmi_pds 20>; + ti,timer-pwm; + }; + + wkup_i2c0: i2c@2b200000 { + compatible =3D "ti,am64-i2c", "ti,omap4-i2c"; + reg =3D <0x00 0x2b200000 0x00 0x100>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&scmi_pds 57>; + clocks =3D <&scmi_clk 262>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + + target-module@2b300050 { + compatible =3D "ti,sysc-omap2", "ti,sysc"; + reg =3D <0x00 0x2b300050 0x00 0x4>, + <0x00 0x2b300054 0x00 0x4>, + <0x00 0x2b300058 0x00 0x4>; + reg-names =3D "rev", "sysc", "syss"; + ranges =3D <0x00 0x00 0x2b300000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + power-domains =3D <&scmi_pds 83>; + clocks =3D <&scmi_clk 324>; + clock-names =3D "fck"; + ti,sysc-mask =3D <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle =3D , + , + , + ; + ti,syss-mask =3D <1>; + ti,no-reset-on-init; + status =3D "disabled"; + + wkup_uart0: serial@0 { + compatible =3D "ti,am64-uart", "ti,am654-uart"; + reg =3D <0x00 0x100>; + interrupts =3D ; + clocks =3D <&scmi_clk 324>; + assigned-clocks =3D <&scmi_clk 324>; + clock-names =3D "fck"; + status =3D "disabled"; + }; + }; + + wkup_conf: bus@43000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00 0x43000000 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chipid: chipid@14 { + compatible =3D "ti,am654-chipid"; + reg =3D <0x14 0x8>; + bootph-all; + }; + + cpsw_mac_syscon: ethernet-mac-syscon@2000 { + compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; + reg =3D <0x2000 0x8>; + }; + + usb_phy_ctrl: syscon@45000 { + compatible =3D "ti,am62-usb-phy-ctrl", "syscon"; + reg =3D <0x45000 0x8>; + bootph-all; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/= k3-am62l.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..d058394a8d19d16f100cd87cf29= 3c67bc189b475 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree Source for AM62L SoC Family + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +#include +#include +#include + +#include "k3-pinctrl.h" + +/ { + model =3D "Texas Instruments K3 AM62L3 SoC"; + compatible =3D "ti,am62l3"; + interrupt-parent =3D <&gic500>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + + psci: psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + scmi: scmi { + compatible =3D "arm,scmi-smc"; + arm,smc-id =3D <0x82004000>; + shmem =3D <&scmi_shmem>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + bootph-all; + }; + + scmi_pds: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + bootph-all; + }; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + cbass_main: bus@f0000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00600000 0x00 0x00600000 0x00 0x00010100>, /* GPIO */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First Peripheral= Window */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000400>, /* Timesync Router = */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* CPSW */ + <0x00 0x09000000 0x00 0x09000000 0x00 0x00400000>, /* CTRL MMRs */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x1a001400>, /* Second Periphera= l Window */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x0000b000>, /* DSS */ + <0x00 0x30270000 0x00 0x30270000 0x00 0x00390000>, /* DSI Wrapper */ + <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI Config */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core W= indow */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core W= indow */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */ + <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */ + <0x00 0x70800000 0x00 0x70800000 0x00 0x00018000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x04 0x00000000 0x04 0x00000000 0x01 0x00000000>, /* FSS DAT0 */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS DAT3 */ + + /* Wakeup Domain Range */ + <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Periphera= l Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + + cbass_wakeup: bus@43000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00 0x00a80000 0x00 0x00a80000 0x00 0x00034000>, /* GTC */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ + <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ + <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripher= al Window */ + <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ + #address-cells =3D <2>; + #size-cells =3D <2>; + }; + }; + + #include "k3-am62l-thermal.dtsi" +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62l-main.dtsi" +#include "k3-am62l-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti= /k3-am62l3.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..da220b85151227c63f59b2b8ec4= 8ae2ebb37e7bf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * Device Tree file for the AM62L3 SoC family (Dual Core A53) + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 + */ + +/dts-v1/; + +#include "k3-am62l.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + + cpu1: cpu@1 { + compatible =3D "arm,cortex-a53"; + reg =3D <0x001>; + device_type =3D "cpu"; + enable-method =3D "psci"; + i-cache-size =3D <0x8000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <128>; + next-level-cache =3D <&l2_0>; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-unified; + cache-level =3D <2>; + cache-size =3D <0x40000>; + cache-line-size =3D <64>; + cache-sets =3D <256>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k= 3-pinctrl.h index c0f09be8d3f94a70812b66c3f91626aac35f4026..fad0fd3fc656eecf97273143a0e= 530d4b745dd8a 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -78,6 +78,8 @@ #define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) #define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (mux= mode)) =20 +#define AM62LX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmod= e)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode= )) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxm= ode)) =20 --=20 2.50.1