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Thu, 11 Sep 2025 18:33:10 +0000 (GMT) From: Farhan Ali To: linux-s390@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: alex.williamson@redhat.com, helgaas@kernel.org, alifm@linux.ibm.com, schnelle@linux.ibm.com, mjrosato@linux.ibm.com Subject: [PATCH v3 04/10] s390/pci: Add architecture specific resource/bus address translation Date: Thu, 11 Sep 2025 11:33:01 -0700 Message-ID: <20250911183307.1910-5-alifm@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911183307.1910-1-alifm@linux.ibm.com> References: <20250911183307.1910-1-alifm@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 4Oz9sv7fwmDOIfBb-aVG6k-2PPrB1_Vv X-Proofpoint-GUID: 4Oz9sv7fwmDOIfBb-aVG6k-2PPrB1_Vv X-Authority-Analysis: v=2.4 cv=EYDIQOmC c=1 sm=1 tr=0 ts=68c315e9 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=yYx7OUe3D3zVL1aRsq0A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyMCBTYWx0ZWRfXxompx4eB6Q1R e2kSJHEG5B456HbYZ7y0KWygZjOhwTIuFhtBDNF2UHPUljltFhBAbdvh4PTGjTvrdzWAXEWIb5q Nx2yn1fqHApB2tbhQGAG3gJeFQuAwzkW6ovrBK4sC7Srm/bXTlvrOSyVVwRPmDzKS8QctWL3SIf siH/FFxIHBpvL65AKJf5BGmSdIBWg2zSFD7g36+i5Dlf6rtpcT7s2T1rnvnD1OTGzovA10MSnxk Tg+c3ze5spU7rZPR5rqovKNUrVj2Suv09NXWL3z/TUA/gVZOBlypNqIBACJ4T6C3butRV8P5SBt dSwTUD3xuDfdafAICQacas+4L+g4Pij2TMm0f5LpfeohH28FPlbIdt4MUtr+9ecxGyA/9Ys/As0 sH5GYe2P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_03,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1011 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060020 Content-Type: text/plain; charset="utf-8" On s390 today we overwrite the PCI BAR resource address to either an artificial cookie address or MIO address. However this address is different from the bus address of the BARs programmed by firmware. The artificial cookie address was created to index into an array of function handles (zpci_iomap_start). The MIO (mapped I/O) addresses are provided by firmware but maybe different from the bus address. This creates an issue when trying to convert the BAR resource address to bus address using the generic pcibios_resource_to_bus. Implement an architecture specific pcibios_resource_to_bus function to correctly translate PCI BAR resource address to bus address for s390. Similarly add architecture specific pcibios_bus_to_resource function to do the reverse translation. Signed-off-by: Farhan Ali --- arch/s390/pci/pci.c | 73 +++++++++++++++++++++++++++++++++++++++ drivers/pci/host-bridge.c | 4 +-- 2 files changed, 75 insertions(+), 2 deletions(-) diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index cd6676c2d602..5baeb5f6f674 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -264,6 +264,79 @@ resource_size_t pcibios_align_resource(void *data, con= st struct resource *res, return 0; } =20 +void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *r= egion, + struct resource *res) +{ + struct zpci_bus *zbus =3D bus->sysdata; + struct zpci_bar_struct *zbar; + struct zpci_dev *zdev; + + region->start =3D res->start; + region->end =3D res->end; + + for (int i =3D 0; i < ZPCI_FUNCTIONS_PER_BUS; i++) { + int j =3D 0; + + zbar =3D NULL; + zdev =3D zbus->function[i]; + if (!zdev) + continue; + + for (j =3D 0; j < PCI_STD_NUM_BARS; j++) { + if (zdev->bars[j].res->start =3D=3D res->start && + zdev->bars[j].res->end =3D=3D res->end) { + zbar =3D &zdev->bars[j]; + break; + } + } + + if (zbar) { + /* only MMIO is supported */ + region->start =3D zbar->val & PCI_BASE_ADDRESS_MEM_MASK; + if (zbar->val & PCI_BASE_ADDRESS_MEM_TYPE_64) + region->start |=3D (u64)zdev->bars[j + 1].val << 32; + + region->end =3D region->start + (1UL << zbar->size) - 1; + return; + } + } +} + +void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, + struct pci_bus_region *region) +{ + struct zpci_bus *zbus =3D bus->sysdata; + struct zpci_dev *zdev; + resource_size_t start, end; + + res->start =3D region->start; + res->end =3D region->end; + + for (int i =3D 0; i < ZPCI_FUNCTIONS_PER_BUS; i++) { + zdev =3D zbus->function[i]; + if (!zdev || !zdev->has_resources) + continue; + + for (int j =3D 0; j < PCI_STD_NUM_BARS; j++) { + if (!zdev->bars[j].val && !zdev->bars[j].size) + continue; + + /* only MMIO is supported */ + start =3D zdev->bars[j].val & PCI_BASE_ADDRESS_MEM_MASK; + if (zdev->bars[j].val & PCI_BASE_ADDRESS_MEM_TYPE_64) + start |=3D (u64)zdev->bars[j + 1].val << 32; + + end =3D start + (1UL << zdev->bars[j].size) - 1; + + if (start =3D=3D region->start && end =3D=3D region->end) { + res->start =3D zdev->bars[j].res->start; + res->end =3D zdev->bars[j].res->end; + return; + } + } + } +} + void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size, pgprot_t prot) { diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c index afa50b446567..56d62afb3afe 100644 --- a/drivers/pci/host-bridge.c +++ b/drivers/pci/host-bridge.c @@ -48,7 +48,7 @@ void pci_set_host_bridge_release(struct pci_host_bridge *= bridge, } EXPORT_SYMBOL_GPL(pci_set_host_bridge_release); =20 -void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *r= egion, +void __weak pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_re= gion *region, struct resource *res) { struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); @@ -73,7 +73,7 @@ static bool region_contains(struct pci_bus_region *region= 1, return region1->start <=3D region2->start && region1->end >=3D region2->e= nd; } =20 -void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, +void __weak pcibios_bus_to_resource(struct pci_bus *bus, struct resource *= res, struct pci_bus_region *region) { struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); --=20 2.43.0