From nobody Thu Oct 2 20:46:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69977369983; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; cv=none; b=RGL9fiWsBo2AsdcGFWE3m/eIQLQed231a8+Zoxgk/D5mU/ew0ISWYWEESjy4Id357mOo0dCZkYvC/FCMMKcfUOd7xIf/HXX5bemSz8dDheOlg1fmWRzMQBU2hOwYclviOviCUvPYVU42EjtwEL1caxCq/8vzGhsg7QwtIk+/WMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; c=relaxed/simple; bh=WzFwdnb/weY1BfCYsn8nBeYLnmC5YscOBh1kWZFapkI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uFDezeDi3SajlMrzbOZC9tXXra/eIeeqE6wglkHltTb0ACjX8HzxfwKW8oK2i7K2HZT5z6Mgx6VlYjFzACHBA+0WZIvObnp+2m+PwuD/Py3kF1g5zIq2u8OHvEMxhpJ5KM99zu4A6YFKu1kxe4xtoBps2JQjBrshpHK37I43RQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aAixnrkK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aAixnrkK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AE50C113CF; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612836; bh=WzFwdnb/weY1BfCYsn8nBeYLnmC5YscOBh1kWZFapkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aAixnrkK6ogY1UdA6Cjp6ThQtGasFtjjg7sxdNkWSd9Bzoi7Ywv8jyy+YKxjk4PZB NCra51SZcYII02kG/CZqAumdBg5f8gzKlrLFZ+g8aHT3ev2763V+Mn3tIenDlABlBd j+st1A3dxxpzf+Pm+B8VqvzhqTEzS2LfbIKZzcxFnbY3qlWWj8tEhOtjFrC8SG9+PY QjlWs6lqRm/8I8cx5OkqZRttMYErGjuZiI3HEIuE+BdJ1oit+wx12NgkEK1TKFAm/C H0QCpV/ocb0h6IfOOqjHJUX4B4/a2KF9u/C6HMJOOaBYaPUESczovx+Pjm0v4qVJcU Hjqm/FjFSpftQ== Received: by wens.tw (Postfix, from userid 1000) id 112515FEEE; Fri, 12 Sep 2025 01:47:12 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: allwinner: a523: Add NPU device node Date: Fri, 12 Sep 2025 01:47:10 +0800 Message-Id: <20250911174710.3149589-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index f93376372aba..9676caf9bd4e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -852,6 +852,18 @@ mcu_ccu: clock-controller@7102000 { #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + npu: npu@7122000 { + compatible =3D "vivante,gc"; + reg =3D <0x07122000 0x1000>; + interrupts =3D ; + clocks =3D <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names =3D "bus", "core", "reg"; + resets =3D <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains =3D <&ppu PD_NPU>; + }; }; =20 thermal-zones { --=20 2.39.5