From nobody Thu Oct 2 20:46:42 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 985CF36C09C; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612837; cv=none; b=d8uiemYV4capVeO0hFe1ilTrCgRQDgGTuOmUN37usZmln+wS/JfV/FJ8X1VuohK1GRwZT48TDoFbxxyenbQxU/GlV42B+ZApR8AwOvXJer0WRbhRI09QUJmSYdaUcmDtd1t3mZwLjcSt+RhotvuctGhuxPQxxXVNMQTmd+brd80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612837; c=relaxed/simple; bh=ImBVT45GxJiTTP2fU7fclUDByXFPw1FuSHPXOCwzMUU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U4flDrxPOsV0aoDSUO9W35JL4iI3PsDDopFikmuwGP+9LPjtMiP2I5JJYvRzzCDghgYKoquo37W66qcW54E3tUN3ufAAMj2Jxxy58wxRqHzzGaWxmngWpMlEd+uTD8vlMbcP8bnNjxYP8dDJziA298aTbKjWkfwAKrV1Rho6BHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ial0fF8E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ial0fF8E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA127C4CEFC; Thu, 11 Sep 2025 17:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612836; bh=ImBVT45GxJiTTP2fU7fclUDByXFPw1FuSHPXOCwzMUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ial0fF8EIOx+KJkjaK9rNJf9S4N2xkgwx1SvuNIlzw081KDl2yQv1ttZTIlJPUGD+ ZM6Q6HJhgBnU+F8bfOeE0uJMCLsfkyPosJD6A/czJHltSxG+VLHoYt8T2Jqh7LWF/G dLHLtuvhCmCljXpPiWhAE4XoXjKy6e7cWrvpGLAWiqjNMDQ35vUMBVgAvh9J7ERm3G yn0upQ0eUyzY4SKsEjuMNtbjd/QUPNSMzOYGf0AttScFhvwV9XEFsGCAwzA7wHq5iD 7RxT9/MH9q/cv7G7rrt197XapbXmfLpnOoT0sh0AGj9dAeRRzPJSTAd+cRjqRDwu+J kyWsksKvGolGQ== Received: by wens.tw (Postfix, from userid 1000) id 0296D5FF03; Fri, 12 Sep 2025 01:47:11 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] clk: sunxi-ng: add support for the A523/T527 MCU CCU Date: Fri, 12 Sep 2025 01:47:08 +0800 Message-Id: <20250911174710.3149589-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset controls for the RISC-V MCU and other peripherals. There is a second audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main oscillator as the parent for all the bus clocks. But the diagram suggests busses from the other PRCM are used in this block as well. Add a driver to support this part. Unlike the BSP driver, the SoC's main MBUS clock is chosen as the parent for the MCU MBUS clock, and the latter then serves as the parent of the MCU DMA controller's MBUS clock. The bus gate clocks also use their respective bus clocks as parents according to the system bus tree diagram. In cases where a block does not appear in that diagram, an educated guess is made. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- Changes since v1: - Added comment for "fixed" dividers in audio PLL clock - Corrected variable names for audio PLL divider clocks - Added comment for the reversed order of some of the DSP clock's parents when compared to the manual - Added comments for clocks and resets only found in the BSP driver - Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks - Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies - Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c | 469 +++++++++++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8896fd052ef1..6af2d020e03e 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -57,6 +57,11 @@ config SUN55I_A523_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN55I_A523_MCU_CCU + tristate "Support for the Allwinner A523/T527 MCU CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN55I_A523_R_CCU tristate "Support for the Allwinner A523/T527 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 82e471036de6..a1c4087d7241 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SUN50I_H6_CCU) +=3D sun50i-h6-ccu.o obj-$(CONFIG_SUN50I_H6_R_CCU) +=3D sun50i-h6-r-ccu.o obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o +obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o @@ -61,6 +62,7 @@ sun50i-h6-ccu-y +=3D ccu-sun50i-h6.o sun50i-h6-r-ccu-y +=3D ccu-sun50i-h6-r.o sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o +sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c b/drivers/clk/sunxi= -ng/ccu-sun55i-a523-mcu.c new file mode 100644 index 000000000000..197844f0fe4e --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Chen-Yu Tsai + * + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + */ + +#include +#include +#include +#include + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nm.h" + +static const struct clk_parent_data osc24M[] =3D { + { .fw_name =3D "hosc" } +}; + +static const struct clk_parent_data ahb[] =3D { + { .fw_name =3D "r-ahb" } +}; + +static const struct clk_parent_data apb[] =3D { + { .fw_name =3D "r-apb0" } +}; + +#define SUN55I_A523_PLL_AUDIO1_REG 0x00c +static struct ccu_sdm_setting pll_audio1_sdm_table[] =3D { + { .rate =3D 2167603200, .pattern =3D 0xa000a234, .m =3D 1, .n =3D 90 }, /= * div2->22.5792 */ + { .rate =3D 2359296000, .pattern =3D 0xa0009ba6, .m =3D 1, .n =3D 98 }, /= * div2->24.576 */ + { .rate =3D 1806336000, .pattern =3D 0xa000872b, .m =3D 1, .n =3D 75 }, /= * div5->22.576 */ +}; + +static struct ccu_nm pll_audio1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), + .sdm =3D _SUNXI_CCU_SDM(pll_audio1_sdm_table, BIT(24), + 0x010, BIT(31)), + .min_rate =3D 180000000U, + .max_rate =3D 3500000000U, + .common =3D { + .reg =3D 0x00c, + .features =3D CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("pll-audio1", + osc24M, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * /2 and /5 dividers are actually programmable, but we just use the + * values from the BSP, since the audio PLL only needs to provide a + * couple clock rates. This also matches the names given in the manual. + */ +static const struct clk_hw *pll_audio1_div_parents[] =3D { &pll_audio1_clk= .common.hw }; +static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2", + pll_audio1_div_parents, 2, 1, + CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5", + pll_audio1_div_parents, 5, 1, + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_GATE(audio_out_clk, "audio-out", + "pll-audio1-div2", 0x01c, + 0, 5, BIT(31), CLK_SET_RATE_PARENT); + +static const struct clk_parent_data dsp_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + /* + * The order of the following two parent is from the BSP code. It is + * the opposite in the manual. Testing with the DSP is required to + * figure out the real order. + */ + { .hw =3D &pll_audio1_div5_clk.hw }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .fw_name =3D "dsp" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "mcu-dsp", dsp_parents, 0x0= 020, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data i2s_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; + +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s0_clk, "i2s0", i2s_parents, 0x02c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s1_clk, "i2s1", i2s_parents, 0x030, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s2_clk, "i2s2", i2s_parents, 0x034, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_clk, "i2s3", i2s_parents, 0x038, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_parent_data i2s3_asrc_parents[] =3D { + { .fw_name =3D "pll-periph0-300m" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_asrc_clk, "i2s3-asrc", + i2s3_asrc_parents, 0x03c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_i2s0_clk, "bus-i2s0", apb, 0x040, BIT(0), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s1_clk, "bus-i2s1", apb, 0x040, BIT(1), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s2_clk, "bus-i2s2", apb, 0x040, BIT(2), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s3_clk, "bus-i2s3", apb, 0x040, BIT(3), 0= ); + +static const struct clk_parent_data audio_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_tx_clk, "spdif-tx", + audio_parents, 0x044, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_rx_clk, "spdif-rx", + i2s3_asrc_parents, 0x048, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_spdif_clk, "bus-spdif", apb, 0x04c, BIT(0),= 0); + +static SUNXI_CCU_DUALDIV_MUX_GATE(dmic_clk, "dmic", audio_parents, 0x050, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_dmic_clk, "bus-dmic", apb, 0x054, BIT(0), 0= ); + +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_dac_clk, "audio-dac", + audio_parents, 0x058, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_adc_clk, "audio-adc", + audio_parents, 0x05c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_audio_codec_clk, "bus-audio-codec", + apb, 0x060, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_dsp_msgbox_clk, "bus-dsp-msgbox", + ahb, 0x068, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_dsp_cfg_clk, "bus-dsp-cfg", + apb, 0x06c, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", ahb, 0x070, BIT(1= ), 0); +static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", ahb, 0x070, BIT(2= ), 0); + +static const struct clk_parent_data timer_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "r-ahb" } +}; +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer0_clk, "mcu-timer0", timer_= parents, + 0x074, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer1_clk, "mcu-timer1", timer_= parents, + 0x078, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer2_clk, "mcu-timer2", timer_= parents, + 0x07c, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer3_clk, "mcu-timer3", timer_= parents, + 0x080, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer4_clk, "mcu-timer4", timer_= parents, + 0x084, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer5_clk, "mcu-timer5", timer_= parents, + 0x088, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", ahb, 0x08c,= BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", ahb, 0x104, BIT= (0), 0); +/* tzma* only found in BSP code. */ +static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", ahb, 0x108, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", ahb, 0x10c, BIT(0), 0); +/* parent is a guess as this block is not shown in the system bus tree dia= gram */ +static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", ahb, 0x114, BIT= (0), 0); + +/* + * user manual has "mbus" clock as parent of both clocks below, + * but this makes more sense, since BSP MCU DMA controller has + * reference to both of them, likely needing both enabled. + */ +static SUNXI_CCU_GATE_FW(mbus_mcu_clk, "mbus-mcu", "mbus", 0x11c, BIT(1), = 0); +static SUNXI_CCU_GATE_HW(mbus_mcu_dma_clk, "mbus-mcu-dma", + &mbus_mcu_clk.common.hw, 0x11c, BIT(0), 0); + +static const struct clk_parent_data riscv_pwm_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; + +static SUNXI_CCU_MUX_DATA_WITH_GATE(riscv_clk, "riscv", + riscv_pwm_parents, 0x120, + 27, 3, BIT(31), 0); +/* Parents are guesses as these two blocks are not shown in the system bus= tree diagram */ +static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", ahb, + 0x124, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", ahb, + 0x128, BIT(0), 0); + +static SUNXI_CCU_MUX_DATA_WITH_GATE(mcu_pwm0_clk, "mcu-pwm0", + riscv_pwm_parents, 0x130, + 24, 3, BIT(31), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_pwm0_clk, "bus-mcu-pwm0", apb, + 0x134, BIT(0), 0); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the com= mon + * sunxi CCU code, to be filled with the MMIO base address and the shared = lock. + */ +static struct ccu_common *sun55i_a523_mcu_ccu_clks[] =3D { + &pll_audio1_clk.common, + &audio_out_clk.common, + &dsp_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &i2s2_clk.common, + &i2s3_clk.common, + &i2s3_asrc_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2s2_clk.common, + &bus_i2s3_clk.common, + &spdif_tx_clk.common, + &spdif_rx_clk.common, + &bus_spdif_clk.common, + &dmic_clk.common, + &bus_dmic_clk.common, + &audio_dac_clk.common, + &audio_adc_clk.common, + &bus_audio_codec_clk.common, + &bus_dsp_msgbox_clk.common, + &bus_dsp_cfg_clk.common, + &bus_npu_aclk.common, + &bus_npu_hclk.common, + &mcu_timer0_clk.common, + &mcu_timer1_clk.common, + &mcu_timer2_clk.common, + &mcu_timer3_clk.common, + &mcu_timer4_clk.common, + &mcu_timer5_clk.common, + &bus_mcu_timer_clk.common, + &bus_mcu_dma_clk.common, + &tzma0_clk.common, + &tzma1_clk.common, + &bus_pubsram_clk.common, + &mbus_mcu_dma_clk.common, + &mbus_mcu_clk.common, + &riscv_clk.common, + &bus_riscv_cfg_clk.common, + &bus_riscv_msgbox_clk.common, + &mcu_pwm0_clk.common, + &bus_mcu_pwm0_clk.common, +}; + +static struct clk_hw_onecell_data sun55i_a523_mcu_hw_clks =3D { + .hws =3D { + [CLK_MCU_PLL_AUDIO1] =3D &pll_audio1_clk.common.hw, + [CLK_MCU_PLL_AUDIO1_DIV2] =3D &pll_audio1_div2_clk.hw, + [CLK_MCU_PLL_AUDIO1_DIV5] =3D &pll_audio1_div5_clk.hw, + [CLK_MCU_AUDIO_OUT] =3D &audio_out_clk.common.hw, + [CLK_MCU_DSP] =3D &dsp_clk.common.hw, + [CLK_MCU_I2S0] =3D &i2s0_clk.common.hw, + [CLK_MCU_I2S1] =3D &i2s1_clk.common.hw, + [CLK_MCU_I2S2] =3D &i2s2_clk.common.hw, + [CLK_MCU_I2S3] =3D &i2s3_clk.common.hw, + [CLK_MCU_I2S3_ASRC] =3D &i2s3_asrc_clk.common.hw, + [CLK_BUS_MCU_I2S0] =3D &bus_i2s0_clk.common.hw, + [CLK_BUS_MCU_I2S1] =3D &bus_i2s1_clk.common.hw, + [CLK_BUS_MCU_I2S2] =3D &bus_i2s2_clk.common.hw, + [CLK_BUS_MCU_I2S3] =3D &bus_i2s3_clk.common.hw, + [CLK_MCU_SPDIF_TX] =3D &spdif_tx_clk.common.hw, + [CLK_MCU_SPDIF_RX] =3D &spdif_rx_clk.common.hw, + [CLK_BUS_MCU_SPDIF] =3D &bus_spdif_clk.common.hw, + [CLK_MCU_DMIC] =3D &dmic_clk.common.hw, + [CLK_BUS_MCU_DMIC] =3D &bus_dmic_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_DAC] =3D &audio_dac_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_ADC] =3D &audio_adc_clk.common.hw, + [CLK_BUS_MCU_AUDIO_CODEC] =3D &bus_audio_codec_clk.common.hw, + [CLK_BUS_MCU_DSP_MSGBOX] =3D &bus_dsp_msgbox_clk.common.hw, + [CLK_BUS_MCU_DSP_CFG] =3D &bus_dsp_cfg_clk.common.hw, + [CLK_BUS_MCU_NPU_HCLK] =3D &bus_npu_hclk.common.hw, + [CLK_BUS_MCU_NPU_ACLK] =3D &bus_npu_aclk.common.hw, + [CLK_MCU_TIMER0] =3D &mcu_timer0_clk.common.hw, + [CLK_MCU_TIMER1] =3D &mcu_timer1_clk.common.hw, + [CLK_MCU_TIMER2] =3D &mcu_timer2_clk.common.hw, + [CLK_MCU_TIMER3] =3D &mcu_timer3_clk.common.hw, + [CLK_MCU_TIMER4] =3D &mcu_timer4_clk.common.hw, + [CLK_MCU_TIMER5] =3D &mcu_timer5_clk.common.hw, + [CLK_BUS_MCU_TIMER] =3D &bus_mcu_timer_clk.common.hw, + [CLK_BUS_MCU_DMA] =3D &bus_mcu_dma_clk.common.hw, + [CLK_MCU_TZMA0] =3D &tzma0_clk.common.hw, + [CLK_MCU_TZMA1] =3D &tzma1_clk.common.hw, + [CLK_BUS_MCU_PUBSRAM] =3D &bus_pubsram_clk.common.hw, + [CLK_MCU_MBUS_DMA] =3D &mbus_mcu_dma_clk.common.hw, + [CLK_MCU_MBUS] =3D &mbus_mcu_clk.common.hw, + [CLK_MCU_RISCV] =3D &riscv_clk.common.hw, + [CLK_BUS_MCU_RISCV_CFG] =3D &bus_riscv_cfg_clk.common.hw, + [CLK_BUS_MCU_RISCV_MSGBOX] =3D &bus_riscv_msgbox_clk.common.hw, + [CLK_MCU_PWM0] =3D &mcu_pwm0_clk.common.hw, + [CLK_BUS_MCU_PWM0] =3D &bus_mcu_pwm0_clk.common.hw, + }, + .num =3D CLK_BUS_MCU_PWM0 + 1, +}; + +static struct ccu_reset_map sun55i_a523_mcu_ccu_resets[] =3D { + [RST_BUS_MCU_I2S0] =3D { 0x0040, BIT(16) }, + [RST_BUS_MCU_I2S1] =3D { 0x0040, BIT(17) }, + [RST_BUS_MCU_I2S2] =3D { 0x0040, BIT(18) }, + [RST_BUS_MCU_I2S3] =3D { 0x0040, BIT(19) }, + [RST_BUS_MCU_SPDIF] =3D { 0x004c, BIT(16) }, + [RST_BUS_MCU_DMIC] =3D { 0x0054, BIT(16) }, + [RST_BUS_MCU_AUDIO_CODEC] =3D { 0x0060, BIT(16) }, + [RST_BUS_MCU_DSP_MSGBOX] =3D { 0x0068, BIT(16) }, + [RST_BUS_MCU_DSP_CFG] =3D { 0x006c, BIT(16) }, + [RST_BUS_MCU_NPU] =3D { 0x0070, BIT(16) }, + [RST_BUS_MCU_TIMER] =3D { 0x008c, BIT(16) }, + /* dsp and dsp_debug resets only found in BSP code. */ + [RST_BUS_MCU_DSP_DEBUG] =3D { 0x0100, BIT(16) }, + [RST_BUS_MCU_DSP] =3D { 0x0100, BIT(17) }, + [RST_BUS_MCU_DMA] =3D { 0x0104, BIT(16) }, + [RST_BUS_MCU_PUBSRAM] =3D { 0x0114, BIT(16) }, + [RST_BUS_MCU_RISCV_CFG] =3D { 0x0124, BIT(16) }, + [RST_BUS_MCU_RISCV_DEBUG] =3D { 0x0124, BIT(17) }, + [RST_BUS_MCU_RISCV_CORE] =3D { 0x0124, BIT(18) }, + [RST_BUS_MCU_RISCV_MSGBOX] =3D { 0x0128, BIT(16) }, + [RST_BUS_MCU_PWM0] =3D { 0x0134, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun55i_a523_mcu_ccu_desc =3D { + .ccu_clks =3D sun55i_a523_mcu_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_clks), + + .hw_clks =3D &sun55i_a523_mcu_hw_clks, + + .resets =3D sun55i_a523_mcu_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_resets), +}; + +static int sun55i_a523_mcu_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int ret; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + val =3D readl(reg + SUN55I_A523_PLL_AUDIO1_REG); + + /* + * The PLL clock code does not model all bits, for instance it does + * not support a separate enable and gate bit. We present the + * gate bit(27) as the enable bit, but then have to set the + * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. + */ + val |=3D BIT(31) | BIT(30) | BIT(29); + + /* Enforce p1 =3D 5, p0 =3D 2 (the default) for PLL_AUDIO1 */ + val &=3D ~(GENMASK(22, 20) | GENMASK(18, 16)); + val |=3D (4 << 20) | (1 << 16); + + writel(val, reg + SUN55I_A523_PLL_AUDIO1_REG); + + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_mcu_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun55i_a523_mcu_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun55i-a523-mcu-ccu" }, + { } +}; + +static struct platform_driver sun55i_a523_mcu_ccu_driver =3D { + .probe =3D sun55i_a523_mcu_ccu_probe, + .driver =3D { + .name =3D "sun55i-a523-mcu-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun55i_a523_mcu_ccu_ids, + }, +}; +module_platform_driver(sun55i_a523_mcu_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A523 MCU CCU"); +MODULE_LICENSE("GPL"); --=20 2.39.5