From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D072472BC; Thu, 11 Sep 2025 17:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612834; cv=none; b=DXv74Aoydup1xCn7nSUtd/g0OOUgq61DxUnDcluyHt639GYQRM1VjdeDvaK77XQ3Cpy/E0EBQrGphG+d9ccO4RP4X7zHPgi6sjhgRJXY+/VAjAklzRJMLt/Hu9TrtfH82i6pGa+VYdq6/i4O0chT7U0oLO83UiJWY99Pg6HNaBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612834; c=relaxed/simple; bh=/cTSt66cQ+6yac9OFUXZq7y3BS/9WNfqleMKgu9n+cU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oHWb+wwScNFgd6e0KCVcJoSlgM2aYOcXiS/mnClXrSeHvK3+2zRb7sgUWaVQF64eybzUVjzO0/rCb0AyT4q1JVDpgClhG8mEbP0GU4t2fs5yk1qDVwlw6LV+i4C3BDHmLEJ/8x7/QdO32SEkiorBtC81VvPcwIg3rvYLNR0OQM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W1923mdy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W1923mdy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0090C4CEFA; Thu, 11 Sep 2025 17:47:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612834; bh=/cTSt66cQ+6yac9OFUXZq7y3BS/9WNfqleMKgu9n+cU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W1923mdyrb6wKeWPz0BQ+K8Ki71BI7YgVstxpHbobJLymlXvdhlo8hm3X5Dn9Zp74 Fi2SbgYSlBfITlSafaMwz/93h3RuiPr2ZQ9lwPcn1JmZyXXM/TWjrhiUNkNqfiaL/L bOv3FtrzuMGfDpZU/1LYOjmvlx3O2MMEN2P5TSwVnK+zg+EZQK2+/wkp9jInk3MhJf 2tMmCbOUaNnpnguDcaZlGqriNK7wP9ilM5KZeKro8Vrs4EQ5ca85Dsqji4VpgrkskA 6xM9vghqFvn3s4bBZexgbjkqdJqkNCgrk2hUrpOO+RPBNqjAdw4vA9kY4DiNOsf7i4 QqA94Wd2+qDwQ== Received: by wens.tw (Postfix, from userid 1000) id C990B5FBEB; Fri, 12 Sep 2025 01:47:11 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 1/7] dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock Date: Fri, 12 Sep 2025 01:47:04 +0800 Message-Id: <20250911174710.3149589-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun55i-a523-ccu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindi= ngs/clock/sun55i-a523-ccu.h index c8259ac5ada7..54808fcfd556 100644 --- a/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -185,5 +185,6 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 +#define CLK_NPU 179 =20 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ --=20 2.39.5 From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D73248F48; Thu, 11 Sep 2025 17:47:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612834; cv=none; b=P+zOJb25t69u/yO7NrM6fsj7HtaGt/a/PR2JtkdY4wQp0P+JRcMcAchMRh2CXkHas7YgA2HmqG486Pl5zN+8n0Oiu75aMuBuwRve7otR1Shqf49lte+uTEvti021n84+OiwrUeH9UVyuoU3CBdXLcWRD4U0nM80RgkAwvZ7yjic= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612834; c=relaxed/simple; bh=Q3Bq96TZlKcAyxsYaW5NK7Z7jsH62AFVMSMZMWwZAZ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JSzwU3Lx227NhoErAI2ExUemuM3nPC3IkO2fxY3vpIpHPfWcr/+GV99pQkEwS7W5g6S6SgMJFAk6ygnrrpSkr9dsGYmjSO2Ak74NT0dlzYAoJda10Rq5y8KM+m34aZTndzgqmH7Sdtfk62rVf/x90TD+XAXh9fv/W636DjiRO4U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eioH7piU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eioH7piU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03FB9C4CEF9; Thu, 11 Sep 2025 17:47:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612834; bh=Q3Bq96TZlKcAyxsYaW5NK7Z7jsH62AFVMSMZMWwZAZ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eioH7piUxt6gprqkiVToK4rfU/Xupd6Mn1pE3NkbKtJIyE7oQ6nvApZ+G4vhFmqdu HPe11lS0dnZp1MN+1fpKJIUym3im+wiQkzf0Lh0Da+ZRAMdV9BGe/jmz7D0y/xxeg4 upmixnqzth9A7vd3GpzgyWpT8Xxs3HJsjfMgXH5KKhcaL1K8TkvGhSZw6+Qs5me/8y bx1mFzJsBqbiVVCe/d+RN2LUZneMpmXEqHmsFxoAnuJ0fpPs1NdS1B6Fc+9bsAaU+F rZjGqFP8dQ7YeCj6ClNuJBawQxIZLmsV5NiB09DMnqvUseBvFH4WYS03XKDi8FKkpR LADvn2mWscqFQ== Received: by wens.tw (Postfix, from userid 1000) id D3AE45FE52; Fri, 12 Sep 2025 01:47:11 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring Subject: [PATCH v2 2/7] dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller Date: Fri, 12 Sep 2025 01:47:05 +0800 Message-Id: <20250911174710.3149589-3-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) Signed-off-by: Chen-Yu Tsai Reviewed-by not dropped since this is a minor change. --- Changes since v1: - Moved "r-ahb" clock to the end of the list and added "r-apb0" clock Reviewed-by not dropped since this is a minor change. --- .../clock/allwinner,sun55i-a523-ccu.yaml | 37 ++++++++++++- .../dt-bindings/clock/sun55i-a523-mcu-ccu.h | 54 +++++++++++++++++++ .../dt-bindings/reset/sun55i-a523-mcu-ccu.h | 30 +++++++++++ 3 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/sun55i-a523-mcu-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-mcu-ccu.h diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-= ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-cc= u.yaml index f5f62e9a10a1..58be701a720e 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu =20 reg: @@ -26,11 +27,11 @@ properties: =20 clocks: minItems: 4 - maxItems: 5 + maxItems: 9 =20 clock-names: minItems: 4 - maxItems: 5 + maxItems: 9 =20 required: - "#clock-cells" @@ -63,6 +64,38 @@ allOf: - const: iosc - const: losc-fanout =20 + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: MBUS clock + - description: PRCM AHB clock + - description: PRCM APB0 clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: mbus + - const: r-ahb + - const: r-apb0 + - if: properties: compatible: diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-b= indings/clock/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..6efc6bc7e11a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ + +#define CLK_MCU_PLL_AUDIO1 0 +#define CLK_MCU_PLL_AUDIO1_DIV2 1 +#define CLK_MCU_PLL_AUDIO1_DIV5 2 +#define CLK_MCU_AUDIO_OUT 3 +#define CLK_MCU_DSP 4 +#define CLK_MCU_I2S0 5 +#define CLK_MCU_I2S1 6 +#define CLK_MCU_I2S2 7 +#define CLK_MCU_I2S3 8 +#define CLK_MCU_I2S3_ASRC 9 +#define CLK_BUS_MCU_I2S0 10 +#define CLK_BUS_MCU_I2S1 11 +#define CLK_BUS_MCU_I2S2 12 +#define CLK_BUS_MCU_I2S3 13 +#define CLK_MCU_SPDIF_TX 14 +#define CLK_MCU_SPDIF_RX 15 +#define CLK_BUS_MCU_SPDIF 16 +#define CLK_MCU_DMIC 17 +#define CLK_BUS_MCU_DMIC 18 +#define CLK_MCU_AUDIO_CODEC_DAC 19 +#define CLK_MCU_AUDIO_CODEC_ADC 20 +#define CLK_BUS_MCU_AUDIO_CODEC 21 +#define CLK_BUS_MCU_DSP_MSGBOX 22 +#define CLK_BUS_MCU_DSP_CFG 23 +#define CLK_BUS_MCU_NPU_HCLK 24 +#define CLK_BUS_MCU_NPU_ACLK 25 +#define CLK_MCU_TIMER0 26 +#define CLK_MCU_TIMER1 27 +#define CLK_MCU_TIMER2 28 +#define CLK_MCU_TIMER3 29 +#define CLK_MCU_TIMER4 30 +#define CLK_MCU_TIMER5 31 +#define CLK_BUS_MCU_TIMER 32 +#define CLK_BUS_MCU_DMA 33 +#define CLK_MCU_TZMA0 34 +#define CLK_MCU_TZMA1 35 +#define CLK_BUS_MCU_PUBSRAM 36 +#define CLK_MCU_MBUS_DMA 37 +#define CLK_MCU_MBUS 38 +#define CLK_MCU_RISCV 39 +#define CLK_BUS_MCU_RISCV_CFG 40 +#define CLK_BUS_MCU_RISCV_MSGBOX 41 +#define CLK_MCU_PWM0 42 +#define CLK_BUS_MCU_PWM0 43 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-b= indings/reset/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..a89a0b44f08b --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ + +#define RST_BUS_MCU_I2S0 0 +#define RST_BUS_MCU_I2S1 1 +#define RST_BUS_MCU_I2S2 2 +#define RST_BUS_MCU_I2S3 3 +#define RST_BUS_MCU_SPDIF 4 +#define RST_BUS_MCU_DMIC 5 +#define RST_BUS_MCU_AUDIO_CODEC 6 +#define RST_BUS_MCU_DSP_MSGBOX 7 +#define RST_BUS_MCU_DSP_CFG 8 +#define RST_BUS_MCU_NPU 9 +#define RST_BUS_MCU_TIMER 10 +#define RST_BUS_MCU_DSP_DEBUG 11 +#define RST_BUS_MCU_DSP 12 +#define RST_BUS_MCU_DMA 13 +#define RST_BUS_MCU_PUBSRAM 14 +#define RST_BUS_MCU_RISCV_CFG 15 +#define RST_BUS_MCU_RISCV_DEBUG 16 +#define RST_BUS_MCU_RISCV_CORE 17 +#define RST_BUS_MCU_RISCV_MSGBOX 18 +#define RST_BUS_MCU_PWM0 19 + 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Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Also, merge the private header back into the driver code itself. The header only contains a macro containing the total number of clocks. This has to be updated every time a missing clock gets added. Having it in a separate file doesn't help the process. Instead just drop the macro, and thus the header no longer has any reason to exist. Also move the .num value to after the list of clks to make it obvious that it should be updated when new clks are added. Signed-off-by: Chen-Yu Tsai Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- Changes since v1: - Move .num to after list of clks --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 21 ++++++++++++++++++--- drivers/clk/sunxi-ng/ccu-sun55i-a523.h | 14 -------------- 2 files changed, 18 insertions(+), 17 deletions(-) delete mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523.h diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 1a9a1cb869e2..acb532f8361b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -11,6 +11,9 @@ #include #include =20 +#include +#include + #include "../clk.h" =20 #include "ccu_common.h" @@ -25,8 +28,6 @@ #include "ccu_nkmp.h" #include "ccu_nm.h" =20 -#include "ccu-sun55i-a523.h" - /* * The 24 MHz oscillator, the root of most of the clock tree. * .fw_name is the string used in the DT "clock-names" property, used to @@ -486,6 +487,18 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_p= arents, 0x690, =20 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0); =20 +static const struct clk_hw *npu_parents[] =3D { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_800M_clk.common.hw, + &pll_npu_2x_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0x6e0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), = 0); =20 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c, @@ -1217,6 +1230,7 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D { &bus_ce_sys_clk.common, &ve_clk.common, &bus_ve_clk.common, + &npu_clk.common, &bus_dma_clk.common, &bus_msgbox_clk.common, &bus_spinlock_clk.common, @@ -1343,7 +1357,6 @@ static struct ccu_common *sun55i_a523_ccu_clks[] =3D { }; =20 static struct clk_hw_onecell_data sun55i_a523_hw_clks =3D { - .num =3D CLK_NUMBER, .hws =3D { [CLK_PLL_DDR0] =3D &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X] =3D &pll_periph0_4x_clk.common.hw, @@ -1524,7 +1537,9 @@ static struct clk_hw_onecell_data sun55i_a523_hw_clks= =3D { [CLK_FANOUT0] =3D &fanout0_clk.common.hw, [CLK_FANOUT1] =3D &fanout1_clk.common.hw, [CLK_FANOUT2] =3D &fanout2_clk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, }, + .num =3D CLK_NPU + 1, }; =20 static struct ccu_reset_map sun55i_a523_ccu_resets[] =3D { diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.h deleted file mode 100644 index fc8dd42f1b47..000000000000 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2024 Arm Ltd. - */ - -#ifndef _CCU_SUN55I_A523_H -#define _CCU_SUN55I_A523_H - -#include -#include - -#define CLK_NUMBER (CLK_FANOUT2 + 1) - -#endif /* _CCU_SUN55I_A523_H */ --=20 2.39.5 From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 183AD3629B3; Thu, 11 Sep 2025 17:47:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" From: Chen-Yu Tsai Some clocks (for timers) on the A523 are mux-divider-gate types with the divider being values of power-of-two. Add a macro for these types of clocks so that we can use the divider types instead of the M-P types without an M divider. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu_div.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h index 90d49ee8e0cc..be00b3277e97 100644 --- a/drivers/clk/sunxi-ng/ccu_div.h +++ b/drivers/clk/sunxi-ng/ccu_div.h @@ -274,6 +274,24 @@ struct ccu_div { SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \ _mshift, _mwidth, 0, _flags) =20 +#define SUNXI_CCU_P_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _mshift, _mwidth, \ + _muxshift, _muxwidth, \ + _gate, _flags) \ + struct ccu_div _struct =3D { \ + .enable =3D _gate, \ + .div =3D _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, \ + CLK_DIVIDER_POWER_OF_TWO), \ + .mux =3D _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA(_name, \ + _parents, \ + &ccu_div_ops, \ + _flags), \ + }, \ + } + static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) { struct ccu_common *common =3D hw_to_ccu_common(hw); --=20 2.39.5 From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 985CF36C09C; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612837; cv=none; b=d8uiemYV4capVeO0hFe1ilTrCgRQDgGTuOmUN37usZmln+wS/JfV/FJ8X1VuohK1GRwZT48TDoFbxxyenbQxU/GlV42B+ZApR8AwOvXJer0WRbhRI09QUJmSYdaUcmDtd1t3mZwLjcSt+RhotvuctGhuxPQxxXVNMQTmd+brd80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612837; c=relaxed/simple; bh=ImBVT45GxJiTTP2fU7fclUDByXFPw1FuSHPXOCwzMUU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=U4flDrxPOsV0aoDSUO9W35JL4iI3PsDDopFikmuwGP+9LPjtMiP2I5JJYvRzzCDghgYKoquo37W66qcW54E3tUN3ufAAMj2Jxxy58wxRqHzzGaWxmngWpMlEd+uTD8vlMbcP8bnNjxYP8dDJziA298aTbKjWkfwAKrV1Rho6BHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ial0fF8E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ial0fF8E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA127C4CEFC; Thu, 11 Sep 2025 17:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612836; bh=ImBVT45GxJiTTP2fU7fclUDByXFPw1FuSHPXOCwzMUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ial0fF8EIOx+KJkjaK9rNJf9S4N2xkgwx1SvuNIlzw081KDl2yQv1ttZTIlJPUGD+ ZM6Q6HJhgBnU+F8bfOeE0uJMCLsfkyPosJD6A/czJHltSxG+VLHoYt8T2Jqh7LWF/G dLHLtuvhCmCljXpPiWhAE4XoXjKy6e7cWrvpGLAWiqjNMDQ35vUMBVgAvh9J7ERm3G yn0upQ0eUyzY4SKsEjuMNtbjd/QUPNSMzOYGf0AttScFhvwV9XEFsGCAwzA7wHq5iD 7RxT9/MH9q/cv7G7rrt197XapbXmfLpnOoT0sh0AGj9dAeRRzPJSTAd+cRjqRDwu+J kyWsksKvGolGQ== Received: by wens.tw (Postfix, from userid 1000) id 0296D5FF03; Fri, 12 Sep 2025 01:47:11 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] clk: sunxi-ng: add support for the A523/T527 MCU CCU Date: Fri, 12 Sep 2025 01:47:08 +0800 Message-Id: <20250911174710.3149589-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523/T527 SoCs have a new MCU PRCM, which has more clocks and reset controls for the RISC-V MCU and other peripherals. There is a second audio PLL, but no bus clock dividers. The BSP driver uses the 24MHz main oscillator as the parent for all the bus clocks. But the diagram suggests busses from the other PRCM are used in this block as well. Add a driver to support this part. Unlike the BSP driver, the SoC's main MBUS clock is chosen as the parent for the MCU MBUS clock, and the latter then serves as the parent of the MCU DMA controller's MBUS clock. The bus gate clocks also use their respective bus clocks as parents according to the system bus tree diagram. In cases where a block does not appear in that diagram, an educated guess is made. Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- Changes since v1: - Added comment for "fixed" dividers in audio PLL clock - Corrected variable names for audio PLL divider clocks - Added comment for the reversed order of some of the DSP clock's parents when compared to the manual - Added comments for clocks and resets only found in the BSP driver - Corrected register offset for i2s3-asrc and bus-mcu-pwm0 clocks - Made "r-ahb" and new "r-apb0" external bus clocks the parents of the bus gate clocks, with comments if guessed which one applies - Moved .num_clks to after the list of clocks, making it obvious that the value needs to be added if more clocks are added to the list --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c | 469 +++++++++++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 8896fd052ef1..6af2d020e03e 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -57,6 +57,11 @@ config SUN55I_A523_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN55I_A523_MCU_CCU + tristate "Support for the Allwinner A523/T527 MCU CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN55I_A523_R_CCU tristate "Support for the Allwinner A523/T527 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 82e471036de6..a1c4087d7241 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SUN50I_H6_CCU) +=3D sun50i-h6-ccu.o obj-$(CONFIG_SUN50I_H6_R_CCU) +=3D sun50i-h6-r-ccu.o obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o +obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o @@ -61,6 +62,7 @@ sun50i-h6-ccu-y +=3D ccu-sun50i-h6.o sun50i-h6-r-ccu-y +=3D ccu-sun50i-h6-r.o sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o +sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c b/drivers/clk/sunxi= -ng/ccu-sun55i-a523-mcu.c new file mode 100644 index 000000000000..197844f0fe4e --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523-mcu.c @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Chen-Yu Tsai + * + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + */ + +#include +#include +#include +#include + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nm.h" + +static const struct clk_parent_data osc24M[] =3D { + { .fw_name =3D "hosc" } +}; + +static const struct clk_parent_data ahb[] =3D { + { .fw_name =3D "r-ahb" } +}; + +static const struct clk_parent_data apb[] =3D { + { .fw_name =3D "r-apb0" } +}; + +#define SUN55I_A523_PLL_AUDIO1_REG 0x00c +static struct ccu_sdm_setting pll_audio1_sdm_table[] =3D { + { .rate =3D 2167603200, .pattern =3D 0xa000a234, .m =3D 1, .n =3D 90 }, /= * div2->22.5792 */ + { .rate =3D 2359296000, .pattern =3D 0xa0009ba6, .m =3D 1, .n =3D 98 }, /= * div2->24.576 */ + { .rate =3D 1806336000, .pattern =3D 0xa000872b, .m =3D 1, .n =3D 75 }, /= * div5->22.576 */ +}; + +static struct ccu_nm pll_audio1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), + .sdm =3D _SUNXI_CCU_SDM(pll_audio1_sdm_table, BIT(24), + 0x010, BIT(31)), + .min_rate =3D 180000000U, + .max_rate =3D 3500000000U, + .common =3D { + .reg =3D 0x00c, + .features =3D CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("pll-audio1", + osc24M, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * /2 and /5 dividers are actually programmable, but we just use the + * values from the BSP, since the audio PLL only needs to provide a + * couple clock rates. This also matches the names given in the manual. + */ +static const struct clk_hw *pll_audio1_div_parents[] =3D { &pll_audio1_clk= .common.hw }; +static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2", + pll_audio1_div_parents, 2, 1, + CLK_SET_RATE_PARENT); +static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5", + pll_audio1_div_parents, 5, 1, + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_M_WITH_GATE(audio_out_clk, "audio-out", + "pll-audio1-div2", 0x01c, + 0, 5, BIT(31), CLK_SET_RATE_PARENT); + +static const struct clk_parent_data dsp_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + /* + * The order of the following two parent is from the BSP code. It is + * the opposite in the manual. Testing with the DSP is required to + * figure out the real order. + */ + { .hw =3D &pll_audio1_div5_clk.hw }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .fw_name =3D "dsp" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "mcu-dsp", dsp_parents, 0x0= 020, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data i2s_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; + +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s0_clk, "i2s0", i2s_parents, 0x02c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s1_clk, "i2s1", i2s_parents, 0x030, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s2_clk, "i2s2", i2s_parents, 0x034, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_clk, "i2s3", i2s_parents, 0x038, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_parent_data i2s3_asrc_parents[] =3D { + { .fw_name =3D "pll-periph0-300m" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_asrc_clk, "i2s3-asrc", + i2s3_asrc_parents, 0x03c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_i2s0_clk, "bus-i2s0", apb, 0x040, BIT(0), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s1_clk, "bus-i2s1", apb, 0x040, BIT(1), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s2_clk, "bus-i2s2", apb, 0x040, BIT(2), 0= ); +static SUNXI_CCU_GATE_DATA(bus_i2s3_clk, "bus-i2s3", apb, 0x040, BIT(3), 0= ); + +static const struct clk_parent_data audio_parents[] =3D { + { .fw_name =3D "pll-audio0-4x" }, + { .hw =3D &pll_audio1_div2_clk.hw }, + { .hw =3D &pll_audio1_div5_clk.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_tx_clk, "spdif-tx", + audio_parents, 0x044, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_rx_clk, "spdif-rx", + i2s3_asrc_parents, 0x048, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_spdif_clk, "bus-spdif", apb, 0x04c, BIT(0),= 0); + +static SUNXI_CCU_DUALDIV_MUX_GATE(dmic_clk, "dmic", audio_parents, 0x050, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_dmic_clk, "bus-dmic", apb, 0x054, BIT(0), 0= ); + +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_dac_clk, "audio-dac", + audio_parents, 0x058, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); +static SUNXI_CCU_DUALDIV_MUX_GATE(audio_adc_clk, "audio-adc", + audio_parents, 0x05c, + 0, 5, /* M */ + 5, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static SUNXI_CCU_GATE_DATA(bus_audio_codec_clk, "bus-audio-codec", + apb, 0x060, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_dsp_msgbox_clk, "bus-dsp-msgbox", + ahb, 0x068, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_dsp_cfg_clk, "bus-dsp-cfg", + apb, 0x06c, BIT(0), 0); + +static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", ahb, 0x070, BIT(1= ), 0); +static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", ahb, 0x070, BIT(2= ), 0); + +static const struct clk_parent_data timer_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "r-ahb" } +}; +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer0_clk, "mcu-timer0", timer_= parents, + 0x074, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer1_clk, "mcu-timer1", timer_= parents, + 0x078, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer2_clk, "mcu-timer2", timer_= parents, + 0x07c, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer3_clk, "mcu-timer3", timer_= parents, + 0x080, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer4_clk, "mcu-timer4", timer_= parents, + 0x084, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer5_clk, "mcu-timer5", timer_= parents, + 0x088, + 1, 3, /* P */ + 4, 2, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", ahb, 0x08c,= BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", ahb, 0x104, BIT= (0), 0); +/* tzma* only found in BSP code. */ +static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", ahb, 0x108, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", ahb, 0x10c, BIT(0), 0); +/* parent is a guess as this block is not shown in the system bus tree dia= gram */ +static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", ahb, 0x114, BIT= (0), 0); + +/* + * user manual has "mbus" clock as parent of both clocks below, + * but this makes more sense, since BSP MCU DMA controller has + * reference to both of them, likely needing both enabled. + */ +static SUNXI_CCU_GATE_FW(mbus_mcu_clk, "mbus-mcu", "mbus", 0x11c, BIT(1), = 0); +static SUNXI_CCU_GATE_HW(mbus_mcu_dma_clk, "mbus-mcu-dma", + &mbus_mcu_clk.common.hw, 0x11c, BIT(0), 0); + +static const struct clk_parent_data riscv_pwm_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; + +static SUNXI_CCU_MUX_DATA_WITH_GATE(riscv_clk, "riscv", + riscv_pwm_parents, 0x120, + 27, 3, BIT(31), 0); +/* Parents are guesses as these two blocks are not shown in the system bus= tree diagram */ +static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", ahb, + 0x124, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", ahb, + 0x128, BIT(0), 0); + +static SUNXI_CCU_MUX_DATA_WITH_GATE(mcu_pwm0_clk, "mcu-pwm0", + riscv_pwm_parents, 0x130, + 24, 3, BIT(31), 0); +static SUNXI_CCU_GATE_DATA(bus_mcu_pwm0_clk, "bus-mcu-pwm0", apb, + 0x134, BIT(0), 0); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the com= mon + * sunxi CCU code, to be filled with the MMIO base address and the shared = lock. + */ +static struct ccu_common *sun55i_a523_mcu_ccu_clks[] =3D { + &pll_audio1_clk.common, + &audio_out_clk.common, + &dsp_clk.common, + &i2s0_clk.common, + &i2s1_clk.common, + &i2s2_clk.common, + &i2s3_clk.common, + &i2s3_asrc_clk.common, + &bus_i2s0_clk.common, + &bus_i2s1_clk.common, + &bus_i2s2_clk.common, + &bus_i2s3_clk.common, + &spdif_tx_clk.common, + &spdif_rx_clk.common, + &bus_spdif_clk.common, + &dmic_clk.common, + &bus_dmic_clk.common, + &audio_dac_clk.common, + &audio_adc_clk.common, + &bus_audio_codec_clk.common, + &bus_dsp_msgbox_clk.common, + &bus_dsp_cfg_clk.common, + &bus_npu_aclk.common, + &bus_npu_hclk.common, + &mcu_timer0_clk.common, + &mcu_timer1_clk.common, + &mcu_timer2_clk.common, + &mcu_timer3_clk.common, + &mcu_timer4_clk.common, + &mcu_timer5_clk.common, + &bus_mcu_timer_clk.common, + &bus_mcu_dma_clk.common, + &tzma0_clk.common, + &tzma1_clk.common, + &bus_pubsram_clk.common, + &mbus_mcu_dma_clk.common, + &mbus_mcu_clk.common, + &riscv_clk.common, + &bus_riscv_cfg_clk.common, + &bus_riscv_msgbox_clk.common, + &mcu_pwm0_clk.common, + &bus_mcu_pwm0_clk.common, +}; + +static struct clk_hw_onecell_data sun55i_a523_mcu_hw_clks =3D { + .hws =3D { + [CLK_MCU_PLL_AUDIO1] =3D &pll_audio1_clk.common.hw, + [CLK_MCU_PLL_AUDIO1_DIV2] =3D &pll_audio1_div2_clk.hw, + [CLK_MCU_PLL_AUDIO1_DIV5] =3D &pll_audio1_div5_clk.hw, + [CLK_MCU_AUDIO_OUT] =3D &audio_out_clk.common.hw, + [CLK_MCU_DSP] =3D &dsp_clk.common.hw, + [CLK_MCU_I2S0] =3D &i2s0_clk.common.hw, + [CLK_MCU_I2S1] =3D &i2s1_clk.common.hw, + [CLK_MCU_I2S2] =3D &i2s2_clk.common.hw, + [CLK_MCU_I2S3] =3D &i2s3_clk.common.hw, + [CLK_MCU_I2S3_ASRC] =3D &i2s3_asrc_clk.common.hw, + [CLK_BUS_MCU_I2S0] =3D &bus_i2s0_clk.common.hw, + [CLK_BUS_MCU_I2S1] =3D &bus_i2s1_clk.common.hw, + [CLK_BUS_MCU_I2S2] =3D &bus_i2s2_clk.common.hw, + [CLK_BUS_MCU_I2S3] =3D &bus_i2s3_clk.common.hw, + [CLK_MCU_SPDIF_TX] =3D &spdif_tx_clk.common.hw, + [CLK_MCU_SPDIF_RX] =3D &spdif_rx_clk.common.hw, + [CLK_BUS_MCU_SPDIF] =3D &bus_spdif_clk.common.hw, + [CLK_MCU_DMIC] =3D &dmic_clk.common.hw, + [CLK_BUS_MCU_DMIC] =3D &bus_dmic_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_DAC] =3D &audio_dac_clk.common.hw, + [CLK_MCU_AUDIO_CODEC_ADC] =3D &audio_adc_clk.common.hw, + [CLK_BUS_MCU_AUDIO_CODEC] =3D &bus_audio_codec_clk.common.hw, + [CLK_BUS_MCU_DSP_MSGBOX] =3D &bus_dsp_msgbox_clk.common.hw, + [CLK_BUS_MCU_DSP_CFG] =3D &bus_dsp_cfg_clk.common.hw, + [CLK_BUS_MCU_NPU_HCLK] =3D &bus_npu_hclk.common.hw, + [CLK_BUS_MCU_NPU_ACLK] =3D &bus_npu_aclk.common.hw, + [CLK_MCU_TIMER0] =3D &mcu_timer0_clk.common.hw, + [CLK_MCU_TIMER1] =3D &mcu_timer1_clk.common.hw, + [CLK_MCU_TIMER2] =3D &mcu_timer2_clk.common.hw, + [CLK_MCU_TIMER3] =3D &mcu_timer3_clk.common.hw, + [CLK_MCU_TIMER4] =3D &mcu_timer4_clk.common.hw, + [CLK_MCU_TIMER5] =3D &mcu_timer5_clk.common.hw, + [CLK_BUS_MCU_TIMER] =3D &bus_mcu_timer_clk.common.hw, + [CLK_BUS_MCU_DMA] =3D &bus_mcu_dma_clk.common.hw, + [CLK_MCU_TZMA0] =3D &tzma0_clk.common.hw, + [CLK_MCU_TZMA1] =3D &tzma1_clk.common.hw, + [CLK_BUS_MCU_PUBSRAM] =3D &bus_pubsram_clk.common.hw, + [CLK_MCU_MBUS_DMA] =3D &mbus_mcu_dma_clk.common.hw, + [CLK_MCU_MBUS] =3D &mbus_mcu_clk.common.hw, + [CLK_MCU_RISCV] =3D &riscv_clk.common.hw, + [CLK_BUS_MCU_RISCV_CFG] =3D &bus_riscv_cfg_clk.common.hw, + [CLK_BUS_MCU_RISCV_MSGBOX] =3D &bus_riscv_msgbox_clk.common.hw, + [CLK_MCU_PWM0] =3D &mcu_pwm0_clk.common.hw, + [CLK_BUS_MCU_PWM0] =3D &bus_mcu_pwm0_clk.common.hw, + }, + .num =3D CLK_BUS_MCU_PWM0 + 1, +}; + +static struct ccu_reset_map sun55i_a523_mcu_ccu_resets[] =3D { + [RST_BUS_MCU_I2S0] =3D { 0x0040, BIT(16) }, + [RST_BUS_MCU_I2S1] =3D { 0x0040, BIT(17) }, + [RST_BUS_MCU_I2S2] =3D { 0x0040, BIT(18) }, + [RST_BUS_MCU_I2S3] =3D { 0x0040, BIT(19) }, + [RST_BUS_MCU_SPDIF] =3D { 0x004c, BIT(16) }, + [RST_BUS_MCU_DMIC] =3D { 0x0054, BIT(16) }, + [RST_BUS_MCU_AUDIO_CODEC] =3D { 0x0060, BIT(16) }, + [RST_BUS_MCU_DSP_MSGBOX] =3D { 0x0068, BIT(16) }, + [RST_BUS_MCU_DSP_CFG] =3D { 0x006c, BIT(16) }, + [RST_BUS_MCU_NPU] =3D { 0x0070, BIT(16) }, + [RST_BUS_MCU_TIMER] =3D { 0x008c, BIT(16) }, + /* dsp and dsp_debug resets only found in BSP code. */ + [RST_BUS_MCU_DSP_DEBUG] =3D { 0x0100, BIT(16) }, + [RST_BUS_MCU_DSP] =3D { 0x0100, BIT(17) }, + [RST_BUS_MCU_DMA] =3D { 0x0104, BIT(16) }, + [RST_BUS_MCU_PUBSRAM] =3D { 0x0114, BIT(16) }, + [RST_BUS_MCU_RISCV_CFG] =3D { 0x0124, BIT(16) }, + [RST_BUS_MCU_RISCV_DEBUG] =3D { 0x0124, BIT(17) }, + [RST_BUS_MCU_RISCV_CORE] =3D { 0x0124, BIT(18) }, + [RST_BUS_MCU_RISCV_MSGBOX] =3D { 0x0128, BIT(16) }, + [RST_BUS_MCU_PWM0] =3D { 0x0134, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun55i_a523_mcu_ccu_desc =3D { + .ccu_clks =3D sun55i_a523_mcu_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_clks), + + .hw_clks =3D &sun55i_a523_mcu_hw_clks, + + .resets =3D sun55i_a523_mcu_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun55i_a523_mcu_ccu_resets), +}; + +static int sun55i_a523_mcu_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int ret; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + val =3D readl(reg + SUN55I_A523_PLL_AUDIO1_REG); + + /* + * The PLL clock code does not model all bits, for instance it does + * not support a separate enable and gate bit. We present the + * gate bit(27) as the enable bit, but then have to set the + * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. + */ + val |=3D BIT(31) | BIT(30) | BIT(29); + + /* Enforce p1 =3D 5, p0 =3D 2 (the default) for PLL_AUDIO1 */ + val &=3D ~(GENMASK(22, 20) | GENMASK(18, 16)); + val |=3D (4 << 20) | (1 << 16); + + writel(val, reg + SUN55I_A523_PLL_AUDIO1_REG); + + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_mcu_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun55i_a523_mcu_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun55i-a523-mcu-ccu" }, + { } +}; + +static struct platform_driver sun55i_a523_mcu_ccu_driver =3D { + .probe =3D sun55i_a523_mcu_ccu_probe, + .driver =3D { + .name =3D "sun55i-a523-mcu-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun55i_a523_mcu_ccu_ids, + }, +}; +module_platform_driver(sun55i_a523_mcu_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A523 MCU CCU"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1108F36934F; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; cv=none; b=QvR2SLMCC4ggQr2mr3XIv4xlHJmjyzJCzulq6nUx+54N+gsTwpLIuxcHqifKC0YZb6HqwDZm6ZOLUUcKBV6CNKhw7vckNXd2mndr3U4xxymGFuzwDU1m7nS87W+MBcbqgdjckmnItqkJIIflvWgH04jk4k6HC1YdTlU5PP/sBG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; c=relaxed/simple; bh=W8J/+Z9oRBNbp4TXxTxT486U9Z9A7OK+Xcu6z7nwH6U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jT6R2QxMU/bRjjfg1TkFZF0gnqaEextNoOMC+8/fpvrYKLZtHU5kufGTK7+plkjGhto9iNTNOH7x5bI7eKdjMx+pvvef9x3WzwYRHH0jZTCoaQfI2g4pQI9yLtM0V2R1WmDYKytrJHCS2DL6QYBAyfz8c4elsRsSRO+qCJTpw7c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JJd45Roz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JJd45Roz" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C86C2C4CEFB; Thu, 11 Sep 2025 17:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612835; bh=W8J/+Z9oRBNbp4TXxTxT486U9Z9A7OK+Xcu6z7nwH6U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JJd45RozqFkAXe9m5Hfhk0n4JHTQvVyC/c+SxDDlCKZ6RCZCiEjddSRtjO0TmsKvZ u172mTIPv0AfawQuFAXI77k94Eol/+WUutllAE5dcQZuddsPhizkBIynE/991UjTyt lQ/BOQOR0cxz8qOLvmZ19G6WWca1+Gfgb2xjRDMp44ZDT7ML4su25Jj3HPpnc/3u5b IdUQ4sS7Ywc591SNk+0Q9jjbghEXKsu5o1DxfowV3N6IsgmEIcDqGBS3LJpkeB45wp Aztno5dew+S53sRlGe9A8OLj8ZNC8j37jwySePMSv80khSINbvTy5G/qtXzEAl1NKP 9yM+WdKM5vWIg== Received: by wens.tw (Postfix, from userid 1000) id 09AEA5FF0D; Fri, 12 Sep 2025 01:47:12 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] arm64: dts: allwinner: a523: Add MCU PRCM CCU node Date: Fri, 12 Sep 2025 01:47:09 +0800 Message-Id: <20250911174710.3149589-7-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai Add a device node for the third supported clock controller found in the A523 / T527 SoCs. This controller has clocks and resets for the RISC-V MCU, and others peripherals possibly meant to operate in low power mode driven by the MCU, such as audio interfaces, an audio DSP, and the NPU. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- Changes since v1: - Enlarged MCU PRCM register range to 0x200 - Moved "r-ahb" clock to the end of the list and added "r-apb0" clock --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index 79bd9ce08c7c..f93376372aba 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -825,6 +827,31 @@ rtc: rtc@7090000 { clock-names =3D "bus", "hosc", "ahb"; #clock-cells =3D <1>; }; + + mcu_ccu: clock-controller@7102000 { + compatible =3D "allwinner,sun55i-a523-mcu-ccu"; + reg =3D <0x7102000 0x200>; + clocks =3D <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_PERIPH0_300M>, + <&ccu CLK_DSP>, + <&ccu CLK_MBUS>, + <&r_ccu CLK_R_AHB>, + <&r_ccu CLK_R_APB0>; + clock-names =3D "hosc", + "losc", + "iosc", + "pll-audio0-4x", + "pll-periph0-300m", + "dsp", + "mbus", + "r-ahb", + "r-apb0"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; }; =20 thermal-zones { --=20 2.39.5 From nobody Thu Oct 2 19:27:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69977369983; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; cv=none; b=RGL9fiWsBo2AsdcGFWE3m/eIQLQed231a8+Zoxgk/D5mU/ew0ISWYWEESjy4Id357mOo0dCZkYvC/FCMMKcfUOd7xIf/HXX5bemSz8dDheOlg1fmWRzMQBU2hOwYclviOviCUvPYVU42EjtwEL1caxCq/8vzGhsg7QwtIk+/WMo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612836; c=relaxed/simple; bh=WzFwdnb/weY1BfCYsn8nBeYLnmC5YscOBh1kWZFapkI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uFDezeDi3SajlMrzbOZC9tXXra/eIeeqE6wglkHltTb0ACjX8HzxfwKW8oK2i7K2HZT5z6Mgx6VlYjFzACHBA+0WZIvObnp+2m+PwuD/Py3kF1g5zIq2u8OHvEMxhpJ5KM99zu4A6YFKu1kxe4xtoBps2JQjBrshpHK37I43RQk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aAixnrkK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aAixnrkK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2AE50C113CF; Thu, 11 Sep 2025 17:47:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612836; bh=WzFwdnb/weY1BfCYsn8nBeYLnmC5YscOBh1kWZFapkI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aAixnrkK6ogY1UdA6Cjp6ThQtGasFtjjg7sxdNkWSd9Bzoi7Ywv8jyy+YKxjk4PZB NCra51SZcYII02kG/CZqAumdBg5f8gzKlrLFZ+g8aHT3ev2763V+Mn3tIenDlABlBd j+st1A3dxxpzf+Pm+B8VqvzhqTEzS2LfbIKZzcxFnbY3qlWWj8tEhOtjFrC8SG9+PY QjlWs6lqRm/8I8cx5OkqZRttMYErGjuZiI3HEIuE+BdJ1oit+wx12NgkEK1TKFAm/C H0QCpV/ocb0h6IfOOqjHJUX4B4/a2KF9u/C6HMJOOaBYaPUESczovx+Pjm0v4qVJcU Hjqm/FjFSpftQ== Received: by wens.tw (Postfix, from userid 1000) id 112515FEEE; Fri, 12 Sep 2025 01:47:12 +0800 (CST) From: Chen-Yu Tsai To: Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Andre Przywara , linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] arm64: dts: allwinner: a523: Add NPU device node Date: Fri, 12 Sep 2025 01:47:10 +0800 Message-Id: <20250911174710.3149589-8-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174710.3149589-1-wens@kernel.org> References: <20250911174710.3149589-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index f93376372aba..9676caf9bd4e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -852,6 +852,18 @@ mcu_ccu: clock-controller@7102000 { #clock-cells =3D <1>; #reset-cells =3D <1>; }; + + npu: npu@7122000 { + compatible =3D "vivante,gc"; + reg =3D <0x07122000 0x1000>; + interrupts =3D ; + clocks =3D <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names =3D "bus", "core", "reg"; + resets =3D <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains =3D <&ppu PD_NPU>; + }; }; =20 thermal-zones { --=20 2.39.5