From nobody Thu Oct 2 20:46:41 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EA5636C07F; Thu, 11 Sep 2025 17:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612438; cv=none; b=mfFyN4620XQhUExDS04IhciuH8o3A2DLhyDt5DrHIbxwDyc7K7dhVmNaf3tS1ABYuvVUfEQlhjWCkz8lWbcH64sGifw6yGBbomOADGo+Og7lHyztVlQoNi2KBWhdALJmPFKcSxk3h3tuizfzFMT8r8GaoMwiZDXrSSEVlJJ8Z7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757612438; c=relaxed/simple; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=D/MKA6pbxtGa34pCIfvyrEAZxUSs6FAmsiU2PIwaFbQkMhUqNJDJ0WazERbDDZBEnWyTbQdy0cET3IFenn4en2Qd8esrkh/+rzCd/X49uEUD+WO6VJHzh67bzRuIKWaEUjpnPuOx3JnitpXhCye92jmLrfd1p64gG/7T/7HyVQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OXKWDV6/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OXKWDV6/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03BDEC4CEF0; Thu, 11 Sep 2025 17:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757612438; bh=KwQ33/Me6CtoPqF903pwWNvdntE/FNahw7BHgwIWeoE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OXKWDV6/zRIDx8rmJIF19WHTQ1kLiS67cArk4RJNLqqLh/AHyIzr7jna4Yi7RD49O sNolPJdJi+9pg8YW8VaEr58zA5XSiuyR5JfEdr2//hK9Jn9Y9WCX6ehSS9I4jFX86r lzNI9PD+v5010UKCCzPgjcdWe2BSXCin+Ql/OtSDW/lK/QPrqWju5/Dg+SuNkYJ2Aq WjY8mg/puH2u3ZKyMWc+/qrIIcZ+z41aTZ57eCQiY0dXFz3ehRJ5W1fNncZX72jfNR aFZXn2BSnW/j/WlWFfzXfjjj2Z783x6U97TXDkQWSLw7MJXSOt5T0T6DQ15FMbfXhq aT6v7dLkdDOZA== Received: by wens.tw (Postfix, from userid 1000) id 4659F5FEEE; Fri, 12 Sep 2025 01:40:33 +0800 (CST) From: Chen-Yu Tsai To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Andre Przywara , Jernej Skrabec Subject: [PATCH net-next v5 5/6] arm64: dts: allwinner: t527: avaota-a1: enable second Ethernet port Date: Fri, 12 Sep 2025 01:40:31 +0800 Message-Id: <20250911174032.3147192-6-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911174032.3147192-1-wens@kernel.org> References: <20250911174032.3147192-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai On the Avaota A1 board, the second Ethernet controller, aka the GMAC200, is connected to a second external RTL8211F-CG PHY. The PHY uses an external 25MHz crystal, and has the SoC's PJ16 pin connected to its reset pin. Enable the second Ethernet port. Also fix up the label for the existing external PHY connected to the first Ethernet port. Acked-by: Jernej Skrabec Signed-off-by: Chen-Yu Tsai Reviewed-by: Andrew Lunn --- Changes since v1: - Switch to generic (tx|rx)-internal-delay-ps properties --- .../dts/allwinner/sun55i-t527-avaota-a1.dts | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..f540965ffaa4 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -13,6 +13,7 @@ / { =20 aliases { ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; serial0 =3D &uart0; }; =20 @@ -67,7 +68,7 @@ &ehci1 { =20 &gmac0 { phy-mode =3D "rgmii-id"; - phy-handle =3D <&ext_rgmii_phy>; + phy-handle =3D <&ext_rgmii0_phy>; phy-supply =3D <®_dcdc4>; =20 allwinner,tx-delay-ps =3D <100>; @@ -76,13 +77,24 @@ &gmac0 { status =3D "okay"; }; =20 +&gmac1 { + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii1_phy>; + phy-supply =3D <®_dcdc4>; + + tx-internal-delay-ps =3D <100>; + rx-internal-delay-ps =3D <100>; + + status =3D "okay"; +}; + &gpu { mali-supply =3D <®_dcdc2>; status =3D "okay"; }; =20 &mdio0 { - ext_rgmii_phy: ethernet-phy@1 { + ext_rgmii0_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; reset-gpios =3D <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ @@ -91,6 +103,16 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; =20 +&mdio1 { + ext_rgmii1_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + reset-gpios =3D <&pio 9 16 GPIO_ACTIVE_LOW>; /* PJ16 */ + reset-assert-us =3D <10000>; + reset-deassert-us =3D <150000>; + }; +}; + &mmc0 { vmmc-supply =3D <®_cldo3>; cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PF6 */ --=20 2.39.5