From nobody Thu Oct 2 21:28:10 2025 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9474A32276F for ; Thu, 11 Sep 2025 12:45:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757594720; cv=none; b=H+H7AriQG3nGQsF3MNTiWl+hEuXoChpuP/2FwDUjKVI/J1UGoKYjuCmf/XIKjGJxrJ7R9qg2SxesVsMrr8YvtWeitHVm1XrOTcJ14ei3vT9BVRQW+BxsGGY6dErzhLIySFghCeWTtwlJKo2lhLKan8r2KQxm1DYWTUxCaWJXj+g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757594720; c=relaxed/simple; bh=kohYFVXIspoaPKJua62Rblg42hVWuEWH4mMzi3ehyc4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rKLHsZ7Cu/CYSlcb8BQkdEon9ki0jeudf6N3aHBaCsJ5j91d3FjznrfLcsMp6w0ZIgt43Uv43iGdPEvczZBp7vniLy62ntTqPq4vFEllgE+VBp50EGUGl9+lrdxQY1tPQ7PBlW4WeF4FSxpSrjisPVyhpF6nciT7Mhw7xq7wO5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=Xn8Tawu/; arc=none smtp.client-ip=115.124.30.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="Xn8Tawu/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757594714; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=klrJ7g5FLgpuRyahGw6eB5ihL1iuaDQ6Jxw1/EVd0js=; b=Xn8Tawu/lSHe5b+OTSAts4Qr+ckhRNC9D/ewvfXDSE1q5MCBFTc2NJ6ESgZahBeI/qDYK9Jf2esy6Q3ifVNszXXBpsMTjZpUQs8/dcOplB7cUm98mdp2kP1F3zGKYLQ0VmwZbRdoiidYWsW0CpnbARpcYZid51UYYyMcWOU1gYs= Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0WnmLJjq_1757594712 cluster:ay36) by smtp.aliyun-inc.com; Thu, 11 Sep 2025 20:45:13 +0800 From: cp0613@linux.alibaba.com To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, guoren@kernel.org Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Pei Subject: [RFC PATCH 4/4] riscv: trace: Support sink using dma buffer Date: Thu, 11 Sep 2025 20:44:48 +0800 Message-ID: <20250911124448.1771-5-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250911124448.1771-1-cp0613@linux.alibaba.com> References: <20250911124448.1771-1-cp0613@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Pei In common SoC systems, the trace data by the sink is usually written to the memory, and the memory needs to be a large block. We have two methods to achieve this. One is based on reserved memory. This method requires pre-isolation of memory and is not flexible enough. Therefore, we chose the second method, which is based on IOMMU to map non-contiguous memory to continuous. When implementing the driver, only the DMA alloc related APIs are needed. Signed-off-by: Chen Pei --- arch/riscv/events/riscv_trace.c | 49 ++++++++++++++++++++++++++++++++- arch/riscv/events/riscv_trace.h | 4 ++- 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/riscv/events/riscv_trace.c b/arch/riscv/events/riscv_trac= e.c index 3ac4a3be5d3e..e8deaefa0180 100644 --- a/arch/riscv/events/riscv_trace.c +++ b/arch/riscv/events/riscv_trace.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include "riscv_trace.h" =20 @@ -55,6 +56,44 @@ static void riscv_trace_init_filter_attrs(struct perf_ev= ent *event) riscv_trace_pmu.filter_attr.priv_mode); } =20 +static int riscv_trace_sink_dma_alloc(unsigned long size) +{ + struct riscv_trace_component *component; + dma_addr_t dma_addr; + + list_for_each_entry(component, &riscv_trace_controllers, list) { + if (component->type =3D=3D RISCV_TRACE_SINK) { + component->sink.vaddr =3D + dma_alloc_coherent(riscv_trace_pmu.pmu.dev, size, + &dma_addr, GFP_KERNEL); + if (component->sink.vaddr) { + component->sink.start_addr =3D dma_addr; + component->sink.limit_addr =3D dma_addr + size; + continue; + } else { + pr_err("dma_alloc_coherent failed\n"); + return -ENOMEM; + } + } + } + + return 0; +} + +static void riscv_trace_sink_dma_free(void) +{ + struct riscv_trace_component *component; + + list_for_each_entry(component, &riscv_trace_controllers, list) { + if (component->type =3D=3D RISCV_TRACE_SINK) { + if (component->sink.vaddr) + dma_free_coherent(riscv_trace_pmu.pmu.dev, + component->sink.limit_addr - component->sink.start_addr, + component->sink.vaddr, component->sink.start_addr); + } + } +} + static int riscv_trace_event_init(struct perf_event *event) { if (event->attr.type !=3D riscv_trace_pmu.pmu.type) @@ -105,7 +144,7 @@ static void *riscv_trace_buffer_setup_aux(struct perf_e= vent *event, void **pages { struct riscv_trace_aux_buf *buf; struct page **pagelist; - int i; + int i, ret; =20 if (overwrite) { pr_warn("Overwrite mode is not supported\n"); @@ -135,6 +174,12 @@ static void *riscv_trace_buffer_setup_aux(struct perf_= event *event, void **pages =20 pr_info("nr_pages=3D%d length=3D%d\n", buf->nr_pages, buf->length); =20 + ret =3D riscv_trace_sink_dma_alloc(buf->length); + if (ret) { + kfree(pagelist); + goto err; + } + kfree(pagelist); return buf; err: @@ -148,6 +193,8 @@ static void riscv_trace_buffer_free_aux(void *aux) =20 vunmap(buf->base); kfree(buf); + + riscv_trace_sink_dma_free(); } =20 static int __init riscv_trace_init(void) diff --git a/arch/riscv/events/riscv_trace.h b/arch/riscv/events/riscv_trac= e.h index c28216227006..7819fbeace1f 100644 --- a/arch/riscv/events/riscv_trace.h +++ b/arch/riscv/events/riscv_trace.h @@ -49,7 +49,9 @@ struct riscv_trace_funnel { }; =20 struct riscv_trace_sink { - ; + u64 start_addr; + u64 limit_addr; + void __iomem *vaddr; }; =20 struct riscv_trace_component { --=20 2.49.0