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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 11:44:59.2552 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15b17741-3fe7-43e3-a198-08ddf128a30e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7937 Content-Type: text/plain; charset="utf-8" AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma --- Changes in v1: Removed the pci device id from pci_ids.h file. Added the vendor id macro as per the suggested method. Changed the type of the newly added devmem_phys_off variable. Added to logic to assign offsets for LL and data region blocks in case more number of channels are enabled than given in amd_mdb_data struct. --- drivers/dma/dw-edma/dw-edma-pcie.c | 132 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 3371e0a7..48ecfce 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -23,6 +23,11 @@ #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) =20 +/* AMD MDB specific defines */ +#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 +#define PCI_DEVICE_ID_AMD_MDB_B054 0xb054 +#define DW_PCIE_AMD_MDB_INVALID_ADDR (~0ULL) + #define DW_BLOCK(a, b, c) \ { \ .bar =3D a, \ @@ -50,6 +55,7 @@ struct dw_edma_pcie_data { u8 irqs; u16 wr_ch_cnt; u16 rd_ch_cnt; + pci_bus_addr_t devmem_phys_off; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -90,6 +96,89 @@ struct dw_edma_pcie_data { .rd_ch_cnt =3D 2, }; =20 +static const struct dw_edma_pcie_data amd_mdb_data =3D { + /* MDB registers location */ + .rg.bar =3D BAR_0, + .rg.off =3D 0x00001000, /* 4 Kbytes */ + .rg.sz =3D 0x00002000, /* 8 Kbytes */ + /* MDB memory linked list location */ + .ll_wr =3D { + /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00000000, 0x00000800) + /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00200000, 0x00000800) + }, + .ll_rd =3D { + /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00400000, 0x00000800) + /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00600000, 0x00000800) + }, + /* MDB memory data location */ + .dt_wr =3D { + /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00800000, 0x00000800) + /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00900000, 0x00000800) + }, + .dt_rd =3D { + /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00a00000, 0x00000800) + /* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00b00000, 0x00000800) + }, + /* Other */ + .mf =3D EDMA_MF_HDMA_NATIVE, + .irqs =3D 1, + .wr_ch_cnt =3D 2, + .rd_ch_cnt =3D 2, +}; + +static void dw_edma_assign_chan_data(struct dw_edma_pcie_data *pdata, + enum pci_barno bar) +{ + u16 i; + off_t off =3D 0, offsz =3D 0x200000; + size_t size =3D 0x800; + u16 wr_ch =3D pdata->wr_ch_cnt; + u16 rd_ch =3D pdata->rd_ch_cnt; + + if (wr_ch <=3D 2 || rd_ch <=3D 2) + return; + + /* Write channel LL region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->ll_wr[i].bar =3D bar; + pdata->ll_wr[i].off =3D off; + pdata->ll_wr[i].sz =3D size; + off +=3D offsz + size; + } + + /* Read channel LL region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->ll_rd[i].bar =3D bar; + pdata->ll_rd[i].off =3D off; + pdata->ll_rd[i].sz =3D size; + off +=3D offsz + size; + } + + /* Write channel data region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->dt_wr[i].bar =3D bar; + pdata->dt_wr[i].off =3D off; + pdata->dt_wr[i].sz =3D size; + off +=3D offsz + size; + } + + /* Read channel data region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->dt_rd[i].bar =3D bar; + pdata->dt_rd[i].off =3D off; + pdata->dt_rd[i].sz =3D size; + off +=3D offsz + size; + } +} + static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) { return pci_irq_vector(to_pci_dev(dev), nr); @@ -121,7 +210,11 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, u16 vsec; u64 off; =20 - vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, + /* + * Synopsys and AMD (Xilinx) use the same VSEC ID for the purpose + * of map, channel counts, etc. + */ + vsec =3D pci_find_vsec_capability(pdev, pdev->vendor, DW_PCIE_VSEC_DMA_ID); if (!vsec) return; @@ -155,6 +248,24 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, off <<=3D 32; off |=3D val; pdata->rg.off =3D off; + + /* AMD specific VSEC capability */ + vsec =3D pci_find_vsec_capability(pdev, pdev->vendor, + DW_PCIE_XILINX_MDB_VSEC_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_ID(val) !=3D 0x20 || + PCI_VNDR_HEADER_REV(val) !=3D 0x1) + return; + + pci_read_config_dword(pdev, vsec + 0xc, &val); + off =3D val; + pci_read_config_dword(pdev, vsec + 0x8, &val); + off <<=3D 32; + off |=3D val; + pdata->devmem_phys_off =3D off; } =20 static int dw_edma_pcie_probe(struct pci_dev *pdev, @@ -179,6 +290,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, } =20 memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); + vsec_data->devmem_phys_off =3D DW_PCIE_AMD_MDB_INVALID_ADDR; =20 /* * Tries to find if exists a PCIe Vendor-Specific Extended Capability @@ -186,6 +298,22 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, */ dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data); =20 + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { + /* + * There is no valid address found for the LL memory + * space on the device side. + */ + if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_AMD_MDB_INVALID_ADDR) + return -EINVAL; + + /* + * Configure the channel LL and data blocks if number of + * channels enabled in VSEC capability are more than the + * channels configured in amd_mdb_data. + */ + dw_edma_assign_chan_data(vsec_data, BAR_2); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 11:45:04.0571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21c9b83a-bf22-456e-3cc9-08ddf128a5e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6928 Content-Type: text/plain; charset="utf-8" AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - When a valid physical base address is not configured via the Xilinx VSEC capability then the IP can still be used in non-LL mode. The default mode for all the DMA transactions and for all the DMA channels then is non-LL mode. - When a valid physical base address is configured but the client wants to use the non-LL mode for DMA transactions then also the flexibility is provided via the peripheral_config struct member of dma_slave_config. In this case the channels can be individually configured in non-LL mode. This use case is desirable for single DMA transfer of a chunk, this saves the effort of preparing the Link List. Signed-off-by: Devendra K Verma --- Changes in v1 Changed the function return type for dw_edma_get_phys_addr(). Corrected the typo raised in review. --- drivers/dma/dw-edma/dw-edma-core.c | 38 ++++++++++++++++++--- drivers/dma/dw-edma/dw-edma-core.h | 1 + drivers/dma/dw-edma/dw-edma-pcie.c | 36 +++++++++++++++----- drivers/dma/dw-edma/dw-hdma-v0-core.c | 62 +++++++++++++++++++++++++++++++= +++- include/linux/dma/edma.h | 1 + 5 files changed, 123 insertions(+), 15 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index b43255f..3283ac5 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -223,8 +223,28 @@ static int dw_edma_device_config(struct dma_chan *dcha= n, struct dma_slave_config *config) { struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + int nollp =3D 0; + + if (WARN_ON(config->peripheral_config && + config->peripheral_size !=3D sizeof(int))) + return -EINVAL; =20 memcpy(&chan->config, config, sizeof(*config)); + + /* + * When there is no valid LLP base address available + * then the default DMA ops will use the non-LL mode. + * Cases where LL mode is enabled and client wants + * to use the non-LL mode then also client can do + * so via providing the peripheral_config param. + */ + if (config->peripheral_config) + nollp =3D *(int *)config->peripheral_config; + + chan->nollp =3D false; + if (chan->dw->chip->nollp || (!chan->dw->chip->nollp && nollp)) + chan->nollp =3D true; + chan->configured =3D true; =20 return 0; @@ -353,7 +373,7 @@ static void dw_edma_device_issue_pending(struct dma_cha= n *dchan) struct dw_edma_chan *chan =3D dchan2dw_edma_chan(xfer->dchan); enum dma_transfer_direction dir =3D xfer->direction; struct scatterlist *sg =3D NULL; - struct dw_edma_chunk *chunk; + struct dw_edma_chunk *chunk =3D NULL; struct dw_edma_burst *burst; struct dw_edma_desc *desc; u64 src_addr, dst_addr; @@ -419,9 +439,11 @@ static void dw_edma_device_issue_pending(struct dma_ch= an *dchan) if (unlikely(!desc)) goto err_alloc; =20 - chunk =3D dw_edma_alloc_chunk(desc); - if (unlikely(!chunk)) - goto err_alloc; + if (!chan->nollp) { + chunk =3D dw_edma_alloc_chunk(desc); + if (unlikely(!chunk)) + goto err_alloc; + } =20 if (xfer->type =3D=3D EDMA_XFER_INTERLEAVED) { src_addr =3D xfer->xfer.il->src_start; @@ -450,7 +472,13 @@ static void dw_edma_device_issue_pending(struct dma_ch= an *dchan) if (xfer->type =3D=3D EDMA_XFER_SCATTER_GATHER && !sg) break; =20 - if (chunk->bursts_alloc =3D=3D chan->ll_max) { + /* + * For non-LL mode, only a single burst can be handled + * in a single chunk unlike LL mode where multiple bursts + * can be configured in a single chunk. + */ + if ((chunk && chunk->bursts_alloc =3D=3D chan->ll_max) || + chan->nollp) { chunk =3D dw_edma_alloc_chunk(desc); if (unlikely(!chunk)) goto err_alloc; diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-ed= ma-core.h index 71894b9..2a4ad45 100644 --- a/drivers/dma/dw-edma/dw-edma-core.h +++ b/drivers/dma/dw-edma/dw-edma-core.h @@ -86,6 +86,7 @@ struct dw_edma_chan { u8 configured; =20 struct dma_slave_config config; + bool nollp; }; =20 struct dw_edma_irq { diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 48ecfce..daf1fa7 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -268,6 +268,15 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, pdata->devmem_phys_off =3D off; } =20 +static pci_bus_addr_t dw_edma_get_phys_addr(struct pci_dev *pdev, + struct dw_edma_pcie_data *pdata, + enum pci_barno bar) +{ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) + return pdata->devmem_phys_off; + return pci_bus_address(pdev, bar); +} + static int dw_edma_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *pid) { @@ -277,6 +286,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, struct dw_edma_chip *chip; int err, nr_irqs; int i, mask; + bool nollp =3D false; =20 vsec_data =3D kmalloc(sizeof(*vsec_data), GFP_KERNEL); if (!vsec_data) @@ -301,17 +311,20 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { /* * There is no valid address found for the LL memory - * space on the device side. + * space on the device side. In the absence of LL base + * address use the non-LL mode or simple mode supported by + * the HDMA IP. */ if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_AMD_MDB_INVALID_ADDR) - return -EINVAL; + nollp =3D true; =20 /* * Configure the channel LL and data blocks if number of * channels enabled in VSEC capability are more than the * channels configured in amd_mdb_data. */ - dw_edma_assign_chan_data(vsec_data, BAR_2); + if (!nollp) + dw_edma_assign_chan_data(vsec_data, BAR_2); } =20 /* Mapping PCI BAR regions */ @@ -359,6 +372,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->mf =3D vsec_data->mf; chip->nr_irqs =3D nr_irqs; chip->ops =3D &dw_edma_pcie_plat_ops; + chip->nollp =3D nollp; =20 chip->ll_wr_cnt =3D vsec_data->wr_ch_cnt; chip->ll_rd_cnt =3D vsec_data->rd_ch_cnt; @@ -367,7 +381,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, if (!chip->reg_base) return -ENOMEM; =20 - for (i =3D 0; i < chip->ll_wr_cnt; i++) { + for (i =3D 0; i < chip->ll_wr_cnt && !nollp; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_wr[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_wr[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_wr[i]; @@ -378,7 +392,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -387,12 +402,13 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } =20 - for (i =3D 0; i < chip->ll_rd_cnt; i++) { + for (i =3D 0; i < chip->ll_rd_cnt && !nollp; i++) { struct dw_edma_region *ll_region =3D &chip->ll_region_rd[i]; struct dw_edma_region *dt_region =3D &chip->dt_region_rd[i]; struct dw_edma_block *ll_block =3D &vsec_data->ll_rd[i]; @@ -403,7 +419,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 ll_region->vaddr.io +=3D ll_block->off; - ll_region->paddr =3D pci_bus_address(pdev, ll_block->bar); + ll_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + ll_block->bar); ll_region->paddr +=3D ll_block->off; ll_region->sz =3D ll_block->sz; =20 @@ -412,7 +429,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, return -ENOMEM; =20 dt_region->vaddr.io +=3D dt_block->off; - dt_region->paddr =3D pci_bus_address(pdev, dt_block->bar); + dt_region->paddr =3D dw_edma_get_phys_addr(pdev, vsec_data, + dt_block->bar); dt_region->paddr +=3D dt_block->off; dt_region->sz =3D dt_block->sz; } diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index e3f8db4..befb9e0 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -225,7 +225,7 @@ static void dw_hdma_v0_sync_ll_data(struct dw_edma_chun= k *chunk) readl(chunk->ll_region.vaddr.io); } =20 -static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool fir= st) { struct dw_edma_chan *chan =3D chunk->chan; struct dw_edma *dw =3D chan->dw; @@ -263,6 +263,66 @@ static void dw_hdma_v0_core_start(struct dw_edma_chunk= *chunk, bool first) SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START); } =20 +static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk) +{ + struct dw_edma_chan *chan =3D chunk->chan; + struct dw_edma *dw =3D chan->dw; + struct dw_edma_burst *child; + u32 val; + + list_for_each_entry(child, &chunk->burst->list, list) { + SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0)); + + /* Source address */ + SET_CH_32(dw, chan->dir, chan->id, sar.lsb, + lower_32_bits(child->sar)); + SET_CH_32(dw, chan->dir, chan->id, sar.msb, + upper_32_bits(child->sar)); + + /* Destination address */ + SET_CH_32(dw, chan->dir, chan->id, dar.lsb, + lower_32_bits(child->dar)); + SET_CH_32(dw, chan->dir, chan->id, dar.msb, + upper_32_bits(child->dar)); + + /* Transfer size */ + SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz); + + /* Interrupt setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, int_setup) | + HDMA_V0_STOP_INT_MASK | + HDMA_V0_ABORT_INT_MASK | + HDMA_V0_LOCAL_STOP_INT_EN | + HDMA_V0_LOCAL_ABORT_INT_EN; + + if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) { + val |=3D HDMA_V0_REMOTE_STOP_INT_EN | + HDMA_V0_REMOTE_ABORT_INT_EN; + } + + SET_CH_32(dw, chan->dir, chan->id, int_setup, val); + + /* Channel control setup */ + val =3D GET_CH_32(dw, chan->dir, chan->id, control1); + val &=3D ~HDMA_V0_LINKLIST_EN; + SET_CH_32(dw, chan->dir, chan->id, control1, val); + + /* Ring the doorbell */ + SET_CH_32(dw, chan->dir, chan->id, doorbell, + HDMA_V0_DOORBELL_START); + } +} + +static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first) +{ + struct dw_edma_chan *chan =3D chunk->chan; + + if (!chan->nollp) + dw_hdma_v0_core_ll_start(chunk, first); + else + dw_hdma_v0_core_non_ll_start(chunk); +} + static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) { struct dw_edma *dw =3D chan->dw; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747..e14e16f 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -99,6 +99,7 @@ struct dw_edma_chip { enum dw_edma_map_format mf; =20 struct dw_edma *dw; + bool nollp; }; =20 /* Export to the platform drivers */ --=20 1.8.3.1