From nobody Thu Oct 2 20:44:34 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33BC53176F4 for ; Thu, 11 Sep 2025 11:07:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757588876; cv=none; b=fZR/YSzvhRvtD1IocIveilElQ1ceCnYrperhEwRa7n56gDs34LWpZf3N2qSu42i0QLKIzXgqksJ9ModVk6zAfgvzvTXF/3sdiFmRW/OxbZLz0Er1qFkPEvm7IuCCBVMyeY2ELiACTwho7P6b2X1Zuo2deNYqztrm4txNJmmVwZw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757588876; c=relaxed/simple; bh=rtoGwOGvgmKInZwM2Qm8/5eaQawmdlilvfZFMjo8T2s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ms194cUi6bCXVXG6KaH/zYJ3lDPlQzNr3gElvrhccqly77W+qgMCjrKHupSiaL6+OnmLMBekK8JCxJHjWRpxlXrjqmnY4/udDqm0lY2i0j0rTGjdyEsOPUZKBMa9XBBzstM4MNLQZmFePwIZJ6hPANacHfMz5yO5oGBUN4K6n+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=I/7RTDxh; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I/7RTDxh" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 58BB7QKe731290; Thu, 11 Sep 2025 06:07:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757588846; bh=qO+VhbXYIysM2Mf7i4Pp5L1ZOP0kI1GsjnLInfeFpJ8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I/7RTDxhnUle8n/jj5EV6rWz0Pfn0av/6BphDkeFSeYZ9IaELbMEjsclmpy2Srfrw D6WhyjcvHO0XVkZRKCb/e0kl7DfmFWOkapDpVXGJVuO1VBC2J5G75y4NvYbVJStc4C pQZPg97g7OZ82GB+znrkc/FRbPRUp/fMGvrISlPw= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 58BB7QbV1895185 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 11 Sep 2025 06:07:26 -0500 Received: from DLEE205.ent.ti.com (157.170.170.85) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 11 Sep 2025 06:07:26 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE205.ent.ti.com (157.170.170.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 11 Sep 2025 06:07:26 -0500 Received: from a0512632.dhcp.ti.com (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58BB7FP42031347; Thu, 11 Sep 2025 06:07:21 -0500 From: Swamil Jain To: , , , , , , , CC: , , , , , , , Subject: [PATCH v6 1/3] drm/tidss: oldi: Add property to identify OLDI supported VP Date: Thu, 11 Sep 2025 16:37:13 +0530 Message-ID: <20250911110715.2873596-2-s-jain1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250911110715.2873596-1-s-jain1@ti.com> References: <20250911110715.2873596-1-s-jain1@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jayesh Choudhary TIDSS should know which VP has OLDI output to avoid calling clock functions for that VP as those are controlled by oldi driver. Add a property "is_ext_vp_clk" to "tidss_device" structure for that. Mark it 'true' in tidss_oldi_init() and 'false' in tidss_oldi_deinit(). Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain --- drivers/gpu/drm/tidss/tidss_drv.h | 2 ++ drivers/gpu/drm/tidss/tidss_oldi.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_drv.h b/drivers/gpu/drm/tidss/tids= s_drv.h index 84454a4855d1..e1c1f41d8b4b 100644 --- a/drivers/gpu/drm/tidss/tidss_drv.h +++ b/drivers/gpu/drm/tidss/tidss_drv.h @@ -24,6 +24,8 @@ struct tidss_device { =20 const struct dispc_features *feat; struct dispc_device *dispc; + bool is_ext_vp_clk[TIDSS_MAX_PORTS]; + =20 unsigned int num_crtcs; struct drm_crtc *crtcs[TIDSS_MAX_PORTS]; diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tid= ss_oldi.c index 7688251beba2..7ecbb2c3d0a2 100644 --- a/drivers/gpu/drm/tidss/tidss_oldi.c +++ b/drivers/gpu/drm/tidss/tidss_oldi.c @@ -430,6 +430,7 @@ void tidss_oldi_deinit(struct tidss_device *tidss) for (int i =3D 0; i < tidss->num_oldis; i++) { if (tidss->oldis[i]) { drm_bridge_remove(&tidss->oldis[i]->bridge); + tidss->is_ext_vp_clk[tidss->oldis[i]->parent_vp] =3D false; tidss->oldis[i] =3D NULL; } } @@ -580,6 +581,7 @@ int tidss_oldi_init(struct tidss_device *tidss) oldi->bridge.timings =3D &default_tidss_oldi_timings; =20 tidss->oldis[tidss->num_oldis++] =3D oldi; + tidss->is_ext_vp_clk[oldi->parent_vp] =3D true; oldi->tidss =3D tidss; =20 drm_bridge_add(&oldi->bridge); From nobody Thu Oct 2 20:44:34 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C96B13112D9 for ; Thu, 11 Sep 2025 11:07:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757588873; cv=none; b=CrFSAmpIh51tFEb1g7wMHOjer7CEXM7OHGRbgkdxo2zey8pZOCDSPMBF32KLfwPd0Y18P9tX8tm3hOEKaeWeXu1DXOM19vmBZZD+qZMyXfbLFn6inFPZ3dFnCVlocrj8lXD1e+uQgWFpC0euNaTGpvgRZKDuDX1MkV1juhjsuBI= ARC-Message-Signature: i=1; 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Thu, 11 Sep 2025 06:07:31 -0500 Received: from a0512632.dhcp.ti.com (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58BB7FP52031347; Thu, 11 Sep 2025 06:07:26 -0500 From: Swamil Jain To: , , , , , , , CC: , , , , , , , Subject: [PATCH v6 2/3] drm/tidss: Remove max_pclk_khz from tidss display features: Date: Thu, 11 Sep 2025 16:37:14 +0530 Message-ID: <20250911110715.2873596-3-s-jain1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250911110715.2873596-1-s-jain1@ti.com> References: <20250911110715.2873596-1-s-jain1@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jayesh Choudhary TIDSS hardware, by itself, does not have variable max pixel clock for each VP. The maximum pixel clock is determined by the SoC's clocking architecture. The limitation that has been modeled until now comes from the SoC's clocking architecture (PLL can only be programmed to a particular max value). Instead of putting it as a constant field in dispc_features, we can use clk_round_rate() to see if requested clock can be set or not. Remove the constant "max_pclk_khz" from dispc_features. In mode_valid() call, check if a best frequency match for the mode clock can be found or not using clk_round_rate(). Since TIDSS display controller provides clock tolerance of 5%, we use this while checking if the requested pixel clock is supported. Also, move up dispc_pclk_diff() before it is called. This will make the existing compatibles reusable if DSS features are the same across two SoCs with the only difference being the pixel clock. Note: This uses clk_round_rate() to validate all modes and ensure that the driver enumerates only those whose clocking requirements are well within the tolerance range. However, this incurs a slight delay, as for each mode, clk_round_rate() is called, which takes ~100 us. So, for a monitor supporting 30 modes, it takes an extra 3.5 ms to do clk_round_rate() to enumerate all modes. If the user wants to bypass this validation logic, they can manually modify the driver to bypass these calls selectively. For example, they can just do a clk_round_rate() check for the highest resolution mode and bypass it for the rest of the modes, as done here [1]. [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/ Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain --- drivers/gpu/drm/tidss/tidss_dispc.c | 78 +++++++++++------------------ drivers/gpu/drm/tidss/tidss_dispc.h | 1 - drivers/gpu/drm/tidss/tidss_drv.h | 1 - 3 files changed, 30 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 7c8c15a5c39b..1cd83a6763ba 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -59,10 +59,6 @@ static const u16 tidss_k2g_common_regs[DISPC_COMMON_REG_= TABLE_LEN] =3D { const struct dispc_features dispc_k2g_feats =3D { .min_pclk_khz =3D 4375, =20 - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 150000, - }, - /* * XXX According TRM the RGB input buffer width up to 2560 should * work on 3 taps, but in practice it only works up to 1280. @@ -145,11 +141,6 @@ static const u16 tidss_am65x_common_regs[DISPC_COMMON_= REG_TABLE_LEN] =3D { }; =20 const struct dispc_features dispc_am65x_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - [DISPC_VP_OLDI_AM65X] =3D 165000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -245,11 +236,6 @@ static const u16 tidss_j721e_common_regs[DISPC_COMMON_= REG_TABLE_LEN] =3D { }; =20 const struct dispc_features dispc_j721e_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 170000, - [DISPC_VP_INTERNAL] =3D 600000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 2048, .in_width_max_3tap_rgb =3D 4096, @@ -316,11 +302,6 @@ const struct dispc_features dispc_j721e_feats =3D { }; =20 const struct dispc_features dispc_am625_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - [DISPC_VP_INTERNAL] =3D 170000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -377,15 +358,6 @@ const struct dispc_features dispc_am625_feats =3D { }; =20 const struct dispc_features dispc_am62a7_feats =3D { - /* - * if the code reaches dispc_mode_valid with VP1, - * it should return MODE_BAD. - */ - .max_pclk_khz =3D { - [DISPC_VP_TIED_OFF] =3D 0, - [DISPC_VP_DPI] =3D 165000, - }, - .scaling =3D { .in_width_max_5tap_rgb =3D 1280, .in_width_max_3tap_rgb =3D 2560, @@ -442,10 +414,6 @@ const struct dispc_features dispc_am62a7_feats =3D { }; =20 const struct dispc_features dispc_am62l_feats =3D { - .max_pclk_khz =3D { - [DISPC_VP_DPI] =3D 165000, - }, - .subrev =3D DISPC_AM62L, =20 .common =3D "common", @@ -1331,25 +1299,50 @@ static void dispc_vp_set_default_color(struct dispc= _device *dispc, DISPC_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); } =20 +/* + * Calculate the percentage difference between the requested pixel clock r= ate + * and the effective rate resulting from calculating the clock divider val= ue. + */ +unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) +{ + int r =3D rate / 100, rr =3D real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +static int check_pixel_clock(struct dispc_device *dispc, + u32 hw_videoport, unsigned long clock) +{ + unsigned long round_clock; + + if (dispc->tidss->is_ext_vp_clk[hw_videoport]) + return 0; + round_clock =3D clk_round_rate(dispc->vp_clk[hw_videoport], clock); + /* + * To keep the check consistent with dispc_vp_set_clk_rate(), we + * use the same 5% check here. + */ + if (dispc_pclk_diff(clock, round_clock) > 5) + return -EINVAL; + return 0; +} + enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, u32 hw_videoport, const struct drm_display_mode *mode) { u32 hsw, hfp, hbp, vsw, vfp, vbp; enum dispc_vp_bus_type bus_type; - int max_pclk; =20 bus_type =3D dispc->feat->vp_bus_type[hw_videoport]; =20 - max_pclk =3D dispc->feat->max_pclk_khz[bus_type]; - - if (WARN_ON(max_pclk =3D=3D 0)) + if (WARN_ON(bus_type =3D=3D DISPC_VP_TIED_OFF)) return MODE_BAD; =20 if (mode->clock < dispc->feat->min_pclk_khz) return MODE_CLOCK_LOW; =20 - if (mode->clock > max_pclk) + if (check_pixel_clock(dispc, hw_videoport, mode->clock * 1000)) return MODE_CLOCK_HIGH; =20 if (mode->hdisplay > 4096) @@ -1421,17 +1414,6 @@ void dispc_vp_disable_clk(struct dispc_device *dispc= , u32 hw_videoport) clk_disable_unprepare(dispc->vp_clk[hw_videoport]); } =20 -/* - * Calculate the percentage difference between the requested pixel clock r= ate - * and the effective rate resulting from calculating the clock divider val= ue. - */ -unsigned int dispc_pclk_diff(unsigned long rate, unsigned long real_rate) -{ - int r =3D rate / 100, rr =3D real_rate / 100; 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charset="utf-8" From: Jayesh Choudhary Since OLDI consumes DSS VP clock directly as serial clock, mode_valid() check cannot be performed in tidss driver which should be checked in OLDI driver. Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") Tested-by: Michael Walle Reviewed-by: Devarsh Thakkar Signed-off-by: Jayesh Choudhary Signed-off-by: Swamil Jain --- drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/tidss/tid= ss_oldi.c index 7ecbb2c3d0a2..ada691839ef3 100644 --- a/drivers/gpu/drm/tidss/tidss_oldi.c +++ b/drivers/gpu/drm/tidss/tidss_oldi.c @@ -309,6 +309,26 @@ static u32 *tidss_oldi_atomic_get_input_bus_fmts(struc= t drm_bridge *bridge, return input_fmts; } =20 +static int tidss_oldi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct tidss_oldi *oldi =3D drm_bridge_to_tidss_oldi(bridge); + struct drm_display_mode *adjusted_mode; + unsigned long round_clock; + + adjusted_mode =3D &crtc_state->adjusted_mode; + round_clock =3D clk_round_rate(oldi->serial, adjusted_mode->clock * 7 * 1= 000); + /* + * To keep the check consistent with dispc_vp_set_clk_rate(), + * we use the same 5% check here. + */ + if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, round_clock) > 5) + return -EINVAL; + return 0; +} + static const struct drm_bridge_funcs tidss_oldi_bridge_funcs =3D { .attach =3D tidss_oldi_bridge_attach, .atomic_pre_enable =3D tidss_oldi_atomic_pre_enable, @@ -317,6 +337,7 @@ static const struct drm_bridge_funcs tidss_oldi_bridge_= funcs =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_check =3D tidss_oldi_atomic_check, }; =20 static int get_oldi_mode(struct device_node *oldi_tx, int *companion_insta= nce)