From nobody Thu Oct 2 21:54:42 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A72E73101B6; Thu, 11 Sep 2025 10:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586633; cv=none; b=MsL+7A1IxzzG1dOLjNI3g09NJtA3YNBKBNc3EKq48mSORjyDa3QJAAl5I2Jmf6By0sYWxvxghsYhWbCTgcD40TZ20H6Ccp1aR9W09IuPaFjCRLcGlFgI9naIJi+SFlLTIYoEgi5nsJvwn1s0meAkBcX88P1ZfplodJmTV19gMMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757586633; c=relaxed/simple; bh=BcYGu4RgilFcvfQYGfqceCdOYr0t+LpCXEUuNDQN9X4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IJ1/P7hN3q32oIi/fme6s19AV5BHi0vHrkmOTRPDeYniJmN+fUN6uI4fLjYJimQeGLEMC8YSxBZFckPixM9ojA+XszscfbInh5MJJm9V5Tf6HI2In+04sAdh1eXYwStJhEw3y+wmqGoiVZrENgisgiVu3eKBnGoSpxy8oMDx/K8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bqrz+uVX; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bqrz+uVX" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 58BAUC6U784571; Thu, 11 Sep 2025 05:30:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757586612; bh=Ctk232sd6pXzssE5jN1isdkw/zIJ7hLt8xZeV1QhZiU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bqrz+uVXRqspbWsW/y2XOYd0lrtNsz1G9Kjpz3NLJGWnStDHUONl9zQrG9Kwv56tV SNGpK6bOPJS9Y4XoCeKBWn8m4SBQpYAQQuQZWv/F86xZUL91Wwpc1Jm6k+s5vFyJX2 TrVFuAkguVw2mUsZ6I6IdfeZuImY7n4gOQgopKXE= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 58BAUBDq1877042 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 11 Sep 2025 05:30:11 -0500 Received: from DFLE213.ent.ti.com (10.64.6.71) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 11 Sep 2025 05:30:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE213.ent.ti.com (10.64.6.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Thu, 11 Sep 2025 05:30:11 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 58BASXbr1985821; Thu, 11 Sep 2025 05:30:04 -0500 From: Rishikesh Donadkar To: , , CC: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 13/16] media: ti: j721e-csi2rx: Change the drain architecture for multistream Date: Thu, 11 Sep 2025 15:58:29 +0530 Message-ID: <20250911102832.1583440-14-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250911102832.1583440-1-r-donadkar@ti.com> References: <20250911102832.1583440-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" On buffer starvation the DMA is marked IDLE, and the stale data in the internal FIFOs gets drained only on the next VIDIOC_QBUF call from the userspace. This approach works fine for a single stream case. But in multistream scenarios, buffer starvation for one stream i.e. one virtual channel, can block the shared HW FIFO of the CSI2RX IP. This can stall the pipeline for all other virtual channels, even if buffers are available for them. This patch introduces a new architecture, that continuously drains data from the shared HW FIFO into a small (32KiB) buffer if no buffers are made available to the driver from the userspace. This ensures independence between different streams, where a slower downstream element for one camera does not block streaming for other cameras. Additionally, after a drain is done for a VC, the next frame will be a partial frame, as a portion of its data will have already been drained before a valid buffer is queued by user space to the driver. Use wait for completion barrier to make sure the shared hardware FIFO is cleared of the data at the end of stream after the source has stopped sending data. Reviewed-by: Jai Luthra Reviewed-by: Yemike Abhilash Chandra Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 112 ++++++++---------- 1 file changed, 50 insertions(+), 62 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 45d652e4304c..69d091cdd05f 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -83,7 +83,6 @@ struct ti_csi2rx_buffer { =20 enum ti_csi2rx_dma_state { TI_CSI2RX_DMA_STOPPED, /* Streaming not started yet. */ - TI_CSI2RX_DMA_IDLE, /* Streaming but no pending DMA operation. */ TI_CSI2RX_DMA_ACTIVE, /* Streaming and pending DMA operation. */ }; =20 @@ -111,6 +110,7 @@ struct ti_csi2rx_ctx { struct v4l2_format v_fmt; struct ti_csi2rx_dma dma; struct media_pad pad; + struct completion drain_complete; u32 sequence; u32 idx; u32 vc; @@ -252,6 +252,10 @@ static const struct ti_csi2rx_fmt ti_csi2rx_formats[] = =3D { static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ctx, struct ti_csi2rx_buffer *buf); =20 +/* Forward declarations needed by ti_csi2rx_drain_callback. */ +static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *ctx); +static int ti_csi2rx_dma_submit_pending(struct ti_csi2rx_ctx *ctx); + static const struct ti_csi2rx_fmt *find_format_by_fourcc(u32 pixelformat) { unsigned int i; @@ -617,9 +621,32 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx = *ctx) =20 static void ti_csi2rx_drain_callback(void *param) { - struct completion *drain_complete =3D param; + struct ti_csi2rx_ctx *ctx =3D param; + struct ti_csi2rx_dma *dma =3D &ctx->dma; + unsigned long flags; + + spin_lock_irqsave(&dma->lock, flags); + + if (dma->state =3D=3D TI_CSI2RX_DMA_STOPPED) { + complete(&ctx->drain_complete); + spin_unlock_irqrestore(&dma->lock, flags); + return; + } =20 - complete(drain_complete); + /* + * If dma->queue is empty, it indicates that no buffer has been + * provided by user space. In this case, initiate a transactions + * to drain the DMA. Since one drain of size DRAIN_BUFFER_SIZE + * will be done here, the subsequent frame will be a + * partial frame, with a size of frame_size - DRAIN_BUFFER_SIZE + */ + if (list_empty(&dma->queue)) { + if (ti_csi2rx_drain_dma(ctx)) + dev_warn(ctx->csi->dev, "DMA drain failed\n"); + } else { + ti_csi2rx_dma_submit_pending(ctx); + } + spin_unlock_irqrestore(&dma->lock, flags); } =20 /* @@ -637,12 +664,9 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *c= tx) { struct ti_csi2rx_dev *csi =3D ctx->csi; struct dma_async_tx_descriptor *desc; - struct completion drain_complete; dma_cookie_t cookie; int ret; =20 - init_completion(&drain_complete); - desc =3D dmaengine_prep_slave_single(ctx->dma.chan, csi->drain.paddr, csi->drain.len, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -652,7 +676,7 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *ct= x) } =20 desc->callback =3D ti_csi2rx_drain_callback; - desc->callback_param =3D &drain_complete; + desc->callback_param =3D ctx; =20 cookie =3D dmaengine_submit(desc); ret =3D dma_submit_error(cookie); @@ -661,13 +685,6 @@ static int ti_csi2rx_drain_dma(struct ti_csi2rx_ctx *c= tx) =20 dma_async_issue_pending(ctx->dma.chan); =20 - if (!wait_for_completion_timeout(&drain_complete, - msecs_to_jiffies(DRAIN_TIMEOUT_MS))) { - dmaengine_terminate_sync(ctx->dma.chan); - dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); - ret =3D -ETIMEDOUT; - goto out; - } out: return ret; } @@ -716,9 +733,11 @@ static void ti_csi2rx_dma_callback(void *param) =20 ti_csi2rx_dma_submit_pending(ctx); =20 - if (list_empty(&dma->submitted)) - dma->state =3D TI_CSI2RX_DMA_IDLE; - + if (list_empty(&dma->submitted)) { + if (ti_csi2rx_drain_dma(ctx)) + dev_warn(ctx->csi->dev, + "DMA drain failed on one of the transactions\n"); + } spin_unlock_irqrestore(&dma->lock, flags); } =20 @@ -754,6 +773,7 @@ static int ti_csi2rx_start_dma(struct ti_csi2rx_ctx *ct= x, static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ctx) { struct ti_csi2rx_dma *dma =3D &ctx->dma; + struct ti_csi2rx_dev *csi =3D ctx->csi; enum ti_csi2rx_dma_state state; unsigned long flags; int ret; @@ -763,6 +783,8 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *ct= x) dma->state =3D TI_CSI2RX_DMA_STOPPED; spin_unlock_irqrestore(&dma->lock, flags); =20 + init_completion(&ctx->drain_complete); + if (state !=3D TI_CSI2RX_DMA_STOPPED) { /* * Normal DMA termination does not clean up pending data on @@ -771,11 +793,20 @@ static void ti_csi2rx_stop_dma(struct ti_csi2rx_ctx *= ctx) * enforced before terminating DMA. */ ret =3D ti_csi2rx_drain_dma(ctx); - if (ret && ret !=3D -ETIMEDOUT) + if (ret) dev_warn(ctx->csi->dev, "Failed to drain DMA. Next frame might be bogus\n"); } =20 + /* We wait for the drain to complete so that the stream stops + * cleanly, making sure the shared hardware FIFO is cleared of + * data from the current stream. No more data will be coming from + * the source after this. + */ + if (!wait_for_completion_timeout(&ctx->drain_complete, + msecs_to_jiffies(DRAIN_TIMEOUT_MS))) + dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); + ret =3D dmaengine_terminate_sync(ctx->dma.chan); if (ret) dev_err(ctx->csi->dev, "Failed to stop DMA: %d\n", ret); @@ -838,57 +869,14 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer = *vb) struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vb->vb2_queue); struct ti_csi2rx_buffer *buf; struct ti_csi2rx_dma *dma =3D &ctx->dma; - bool restart_dma =3D false; unsigned long flags =3D 0; - int ret; =20 buf =3D container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); buf->ctx =3D ctx; =20 spin_lock_irqsave(&dma->lock, flags); - /* - * Usually the DMA callback takes care of queueing the pending buffers. - * But if DMA has stalled due to lack of buffers, restart it now. - */ - if (dma->state =3D=3D TI_CSI2RX_DMA_IDLE) { - /* - * Do not restart DMA with the lock held because - * ti_csi2rx_drain_dma() might block for completion. - * There won't be a race on queueing DMA anyway since the - * callback is not being fired. - */ - restart_dma =3D true; - dma->state =3D TI_CSI2RX_DMA_ACTIVE; - } else { - list_add_tail(&buf->list, &dma->queue); - } + list_add_tail(&buf->list, &dma->queue); spin_unlock_irqrestore(&dma->lock, flags); - - if (restart_dma) { - /* - * Once frames start dropping, some data gets stuck in the DMA - * pipeline somewhere. So the first DMA transfer after frame - * drops gives a partial frame. This is obviously not useful to - * the application and will only confuse it. Issue a DMA - * transaction to drain that up. - */ - ret =3D ti_csi2rx_drain_dma(ctx); - if (ret && ret !=3D -ETIMEDOUT) - dev_warn(ctx->csi->dev, - "Failed to drain DMA. Next frame might be bogus\n"); - - spin_lock_irqsave(&dma->lock, flags); - ret =3D ti_csi2rx_start_dma(ctx, buf); - if (ret) { - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); - dma->state =3D TI_CSI2RX_DMA_IDLE; - spin_unlock_irqrestore(&dma->lock, flags); - dev_err(ctx->csi->dev, "Failed to start DMA: %d\n", ret); - } else { - list_add_tail(&buf->list, &dma->submitted); - spin_unlock_irqrestore(&dma->lock, flags); - } - } } =20 static int ti_csi2rx_get_route(struct ti_csi2rx_ctx *ctx) --=20 2.34.1