From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B96AE2C0F97; Thu, 11 Sep 2025 07:56:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577405; cv=none; b=DkdMyjoRNVfO3hvDD9n/e1x4XTbaTPRyMZUasSCdhso8BjJsAuKCfaaHGerRDeVk6WUUkoIUHJa7RmS002HPl/4l/YqUMqZG6hBseRGH2r89gAh0TOGa3JRwMW0Q22I9U3WWfst0SrFmcXM5nYH0X3XPW/IqBFCmqfmvpIXyryY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577405; c=relaxed/simple; bh=pBsfzo+76jLYoCUvLmqxOlwLg75OBZ+MgvSzYO1t/jk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Ss6DZea4NlEIWItWNg4BOsaaE2M09tN5He6gmS1BMBM1L0SOaAKZmvvJOMIsRGS9Hy/UJgo8RlG8Dxv7euV6CTB0M/aloDcJHIAkU7VZSSHqFFvNu+W5EWJwT1vBsfE+gG2EQee4zf0SvLwqDemcssWH3FAFHdJScGwTBttuin0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B7OvQRjv; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B7OvQRjv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757577403; x=1789113403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pBsfzo+76jLYoCUvLmqxOlwLg75OBZ+MgvSzYO1t/jk=; b=B7OvQRjvFeXMCoHxqZwIYWQcZHwU7xWi9nSExT8iJw3scB1OrlVVkQFE 7v0GeqjruJf5uikXmZwck4jq8TFdUCi5DoGb8YS9mB8g01J7jufTvAnqt 4dOo/22PXjjkLBHCAtm4l1xwII+h+eYc4ZTfDlcN09ec/AGOhBaVgshVr wLrvZ+sWGKmH4eWVknSj26ubqGn3Trk0/c6mce6FC2DeXKudMI+0Pf4Mb a2074nAS8EsKutwDKUfm2GN/hXltfMGv3FRXPL6lyWMC/nLizVxGB707m oau8zVNlb3TsFem5/gIkQC0qbmE2l9QtWvkEvJxkqeZsn7YOVjI/Emoa2 Q==; X-CSE-ConnectionGUID: SfDktIlGShuLBsKf2T188g== X-CSE-MsgGUID: UcCjomu3RkCL+ssLgFMplQ== X-IronPort-AV: E=McAfee;i="6800,10657,11549"; a="70999106" X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="70999106" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:34 -0700 X-CSE-ConnectionGUID: hPtAErc8QiiZR+eavhkRxw== X-CSE-MsgGUID: 6d26r8G6RLeJknLwmOVvPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="210757590" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.187]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:26 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Jonathan Corbet , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 01/11] PCI: Move Resizable BAR code into rebar.c Date: Thu, 11 Sep 2025 10:55:55 +0300 Message-Id: <20250911075605.5277-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> References: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In the lack of better place to put it, Resizable BAR code has been placed inside pci.c and setup-res.c that do not use it for anything. Upcoming changes are going to add more Resizable BAR related API functions to PCI core increasing the Resizable BAR code size from the current. As pci.c is huge file as is, extract the Resizable BAR related code out of it into rebar.c and move the actual BAR resize code from setup-res.c as well. Signed-off-by: Ilpo J=C3=A4rvinen --- Documentation/driver-api/pci/pci.rst | 3 + drivers/pci/Makefile | 2 +- drivers/pci/pci.c | 145 ---------------- drivers/pci/pci.h | 1 + drivers/pci/rebar.c | 236 +++++++++++++++++++++++++++ drivers/pci/setup-res.c | 78 --------- 6 files changed, 241 insertions(+), 224 deletions(-) create mode 100644 drivers/pci/rebar.c diff --git a/Documentation/driver-api/pci/pci.rst b/Documentation/driver-ap= i/pci/pci.rst index 59d86e827198..99a1bbaaec5d 100644 --- a/Documentation/driver-api/pci/pci.rst +++ b/Documentation/driver-api/pci/pci.rst @@ -37,6 +37,9 @@ PCI Support Library .. kernel-doc:: drivers/pci/slot.c :export: =20 +.. kernel-doc:: drivers/pci/rebar.c + :export: + .. kernel-doc:: drivers/pci/rom.c :export: =20 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 67647f1880fb..f3c81c892786 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -4,7 +4,7 @@ =20 obj-$(CONFIG_PCI) +=3D access.o bus.o probe.o host-bridge.o \ remove.o pci.o pci-driver.o search.o \ - rom.o setup-res.o irq.o vpd.o \ + rebar.o rom.o setup-res.o irq.o vpd.o \ setup-bus.o vc.o mmap.o devres.o =20 obj-$(CONFIG_PCI) +=3D msi/ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b0f4d98036cd..da3a48bf2799 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1874,32 +1874,6 @@ static void pci_restore_config_space(struct pci_dev = *pdev) } } =20 -static void pci_restore_rebar_state(struct pci_dev *pdev) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - pos =3D pdev->rebar_cap; - if (!pos) - return; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - struct resource *res; - int bar_idx, size; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; - res =3D pci_resource_n(pdev, bar_idx); - size =3D pci_rebar_bytes_to_size(resource_size(res)); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - } -} - /** * pci_restore_state - Restore the saved state of a PCI device * @dev: PCI device that we're dealing with @@ -3738,125 +3712,6 @@ void pci_acs_init(struct pci_dev *dev) pci_enable_acs(dev); } =20 -void pci_rebar_init(struct pci_dev *pdev) -{ - pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); -} - -/** - * pci_rebar_find_pos - find position of resize ctrl reg for BAR - * @pdev: PCI device - * @bar: BAR to find - * - * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. - */ -static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) -{ - unsigned int pos, nbars, i; - u32 ctrl; - - if (pci_resource_is_iov(bar)) { - pos =3D pci_iov_vf_rebar_cap(pdev); - bar =3D pci_resource_num_to_vf_bar(bar); - } else { - pos =3D pdev->rebar_cap; - } - - if (!pos) - return -ENOTSUPP; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); - - for (i =3D 0; i < nbars; i++, pos +=3D 8) { - int bar_idx; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); - if (bar_idx =3D=3D bar) - return pos; - } - - return -ENOENT; -} - -/** - * pci_rebar_get_possible_sizes - get possible sizes for BAR - * @pdev: PCI device - * @bar: BAR to query - * - * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. - */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) -{ - int pos; - u32 cap; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return 0; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); - cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); - - /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ - if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && - bar =3D=3D 0 && cap =3D=3D 0x700) - return 0x3f00; - - return cap; -} -EXPORT_SYMBOL(pci_rebar_get_possible_sizes); - -/** - * pci_rebar_get_current_size - get the current size of a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. - */ -int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); -} - -/** - * pci_rebar_set_size - set a new size for a BAR - * @pdev: PCI device - * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) - * - * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. - */ -int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) -{ - int pos; - u32 ctrl; - - pos =3D pci_rebar_find_pos(pdev, bar); - if (pos < 0) - return pos; - - pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); - ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; - ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); - pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); - return 0; -} - /** * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port * @dev: the PCI device diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 34f65d69662e..f1b30414b2f1 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -926,6 +926,7 @@ static inline int acpi_get_rc_resources(struct device *= dev, const char *hid, #endif =20 void pci_rebar_init(struct pci_dev *pdev); +void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); static inline u64 pci_rebar_size_to_bytes(int size) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c new file mode 100644 index 000000000000..b87cfa6fb3ef --- /dev/null +++ b/drivers/pci/rebar.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Resizable BAR Extended Capability handling. + */ + +#include +#include +#include +#include +#include +#include + +#include "pci.h" + +void pci_rebar_init(struct pci_dev *pdev) +{ + pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); +} + +/** + * pci_rebar_find_pos - find position of resize ctrl reg for BAR + * @pdev: PCI device + * @bar: BAR to find + * + * Helper to find the position of the ctrl register for a BAR. + * Returns -ENOTSUPP if resizable BARs are not supported at all. + * Returns -ENOENT if no ctrl register for the BAR could be found. + */ +static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + if (pci_resource_is_iov(bar)) { + pos =3D pci_iov_vf_rebar_cap(pdev); + bar =3D pci_resource_num_to_vf_bar(bar); + } else { + pos =3D pdev->rebar_cap; + } + + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); + if (bar_idx =3D=3D bar) + return pos; + } + + return -ENOENT; +} + +/** + * pci_rebar_get_possible_sizes - get possible sizes for BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the possible sizes of a resizable BAR as bitmask defined in the spec + * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + */ +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap =3D FIELD_GET(PCI_REBAR_CAP_SIZES, cap); + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor =3D=3D PCI_VENDOR_ID_ATI && pdev->device =3D=3D 0x731f && + bar =3D=3D 0 && cap =3D=3D 0x700) + return 0x3f00; + + return cap; +} +EXPORT_SYMBOL(pci_rebar_get_possible_sizes); + +/** + * pci_rebar_get_current_size - get the current size of a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * + * Read the size of a BAR from the resizable BAR config. + * Returns size if found or negative error code. + */ +int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + return FIELD_GET(PCI_REBAR_CTRL_BAR_SIZE, ctrl); +} + +/** + * pci_rebar_set_size - set a new size for a BAR + * @pdev: PCI device + * @bar: BAR to set size to + * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * + * Set the new size of a BAR as defined in the spec. + * Returns zero if resizing was successful, error code otherwise. + */ +int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) +{ + int pos; + u32 ctrl; + + pos =3D pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return pos; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + return 0; +} + +void pci_restore_rebar_state(struct pci_dev *pdev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos =3D pdev->rebar_cap; + if (!pos) + return; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars =3D FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i =3D 0; i < nbars; i++, pos +=3D 8) { + struct resource *res; + int bar_idx, size; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx =3D ctrl & PCI_REBAR_CTRL_BAR_IDX; + res =3D pci_resource_n(pdev, bar_idx); + size =3D pci_rebar_bytes_to_size(resource_size(res)); + ctrl &=3D ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |=3D FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); + } +} + +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, + int resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, + int size) +{ + resource_size_t res_size =3D pci_rebar_size_to_bytes(size); + struct resource *res =3D pci_resource_n(dev, resno); + + if (!pci_resource_is_iov(resno)) { + resource_set_size(res, res_size); + } else { + resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); + pci_iov_resource_set_size(dev, resno, res_size); + } +} + +int pci_resize_resource(struct pci_dev *dev, int resno, int size) +{ + struct resource *res =3D pci_resource_n(dev, resno); + struct pci_host_bridge *host; + int old, ret; + u32 sizes; + + /* Check if we must preserve the firmware's resource assignment */ + host =3D pci_find_host_bridge(dev->bus); + if (host->preserve_config) + return -ENOTSUPP; + + /* Make sure the resource isn't assigned before resizing it. */ + if (!(res->flags & IORESOURCE_UNSET)) + return -EBUSY; + + if (pci_resize_is_memory_decoding_enabled(dev, resno)) + return -EBUSY; + + sizes =3D pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + old =3D pci_rebar_get_current_size(dev, resno); + if (old < 0) + return old; + + ret =3D pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + pci_resize_resource_set_size(dev, resno, size); + + /* Check if the new config works by trying to assign everything. */ + if (dev->bus->self) { + ret =3D pci_reassign_bridge_resources(dev->bus->self, res->flags); + if (ret) + goto error_resize; + } + return 0; + +error_resize: + pci_rebar_set_size(dev, resno, old); + pci_resize_resource_set_size(dev, resno, old); + return ret; +} +EXPORT_SYMBOL(pci_resize_resource); diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index d2b3ed51e880..20b02b74e90b 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -423,84 +423,6 @@ void pci_release_resource(struct pci_dev *dev, int res= no) } EXPORT_SYMBOL(pci_release_resource); =20 -static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, - int resno) -{ - u16 cmd; - - if (pci_resource_is_iov(resno)) - return pci_iov_is_memory_decoding_enabled(dev); - - pci_read_config_word(dev, PCI_COMMAND, &cmd); - - return cmd & PCI_COMMAND_MEMORY; -} - -static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, - int size) -{ - resource_size_t res_size =3D pci_rebar_size_to_bytes(size); - struct resource *res =3D pci_resource_n(dev, resno); - - if (!pci_resource_is_iov(resno)) { - resource_set_size(res, res_size); - } else { - resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); - pci_iov_resource_set_size(dev, resno, res_size); - } -} - -int pci_resize_resource(struct pci_dev *dev, int resno, int size) -{ - struct resource *res =3D pci_resource_n(dev, resno); - struct pci_host_bridge *host; - int old, ret; - u32 sizes; - - /* Check if we must preserve the firmware's resource assignment */ - host =3D pci_find_host_bridge(dev->bus); - if (host->preserve_config) - return -ENOTSUPP; - - /* Make sure the resource isn't assigned before resizing it. */ - if (!(res->flags & IORESOURCE_UNSET)) - return -EBUSY; - - if (pci_resize_is_memory_decoding_enabled(dev, resno)) - return -EBUSY; - - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) - return -EINVAL; - - old =3D pci_rebar_get_current_size(dev, resno); - if (old < 0) - return old; - - ret =3D pci_rebar_set_size(dev, resno, size); - if (ret) - return ret; - - pci_resize_resource_set_size(dev, resno, size); - - /* Check if the new config works by trying to assign everything. */ - if (dev->bus->self) { - ret =3D pci_reassign_bridge_resources(dev->bus->self, res->flags); - if (ret) - goto error_resize; - } - return 0; - -error_resize: - pci_rebar_set_size(dev, resno, old); - pci_resize_resource_set_size(dev, resno, old); - return ret; -} -EXPORT_SYMBOL(pci_resize_resource); - int pci_enable_resources(struct pci_dev *dev, int mask) { u16 cmd, old_cmd; --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF97F2C1590; Thu, 11 Sep 2025 07:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.15 ARC-Seal: i=1; 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a="60012531" X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="60012531" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:47 -0700 X-CSE-ConnectionGUID: vbdtxzA3RCyRsmebXrL/BQ== X-CSE-MsgGUID: zBK8wFg/SwaGIZ8jBWABJw== X-ExtLoop1: 1 Received: from opintica-mobl1 (HELO localhost) ([10.245.245.187]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:56:39 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 02/11] PCI: Cleanup pci_rebar_bytes_to_size() and move into rebar.c Date: Thu, 11 Sep 2025 10:55:56 +0300 Message-Id: <20250911075605.5277-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> References: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move pci_rebar_bytes_to_size() from include/linux/pci.h into rebar.c as it does not look very trivial and is not expected to be performance critical. Convert literals to use a newly added PCI_REBAR_MIN_SIZE define. Also add kernel doc for the function as the function is exported. Signed-off-by: Ilpo J=C3=A4rvinen Reviewed-by: Michael J. Ruhl #include #include +#include #include +#include #include =20 #include "pci.h" =20 +#define PCI_REBAR_MIN_SIZE ((resource_size_t)SZ_1M) + +/** + * pci_rebar_bytes_to_size - Convert size in bytes to PCI BAR Size + * @bytes: size in bytes + * + * Convert bytes to BAR Size in Resizable BAR Capability (PCIe r6.2, + * sec. 7.8.6.3). + * + * Return: BAR Size as defined in the PCIe spec (0=3D1MB, bit 31=3D128TB). + */ +int pci_rebar_bytes_to_size(u64 bytes) +{ + int rebar_minsize =3D ilog2(PCI_REBAR_MIN_SIZE); + + bytes =3D roundup_pow_of_two(bytes); + + return max(ilog2(bytes), rebar_minsize) - rebar_minsize; +} +EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index 59876de13860..894e9020b07d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1418,16 +1418,12 @@ void pcibios_reset_secondary_bus(struct pci_dev *de= v); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); void pci_release_resource(struct pci_dev *dev, int resno); -static inline int pci_rebar_bytes_to_size(u64 bytes) -{ - bytes =3D roundup_pow_of_two(bytes); - - /* Return BAR size as defined in the resizable BAR specification */ - return max(ilog2(bytes), 20) - 20; -} =20 +/* Resizable BAR related routines */ +int pci_rebar_bytes_to_size(u64 bytes); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); + int pci_select_bars(struct pci_dev *dev, unsigned long flags); bool pci_device_is_present(struct pci_dev *pdev); void pci_ignore_hotplug(struct pci_dev *dev); --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0BD12C0269; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable pci_rebar_size_to_bytes() is in drivers/pci/pci.h but would be useful for endpoint drivers as well. Move the function into rebar.c and export it. In addition, convert the literal to where the number comes from (PCI_REBAR_MIN_SIZE). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/pci.h | 4 ---- drivers/pci/rebar.c | 12 ++++++++++++ include/linux/pci.h | 1 + 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f1b30414b2f1..3d5068d6e195 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -929,10 +929,6 @@ void pci_rebar_init(struct pci_dev *pdev); void pci_restore_rebar_state(struct pci_dev *pdev); int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); -static inline u64 pci_rebar_size_to_bytes(int size) -{ - return 1ULL << (size + 20); -} =20 struct device_node; =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 961bd43be02b..020ed7a1b3aa 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -35,6 +35,18 @@ int pci_rebar_bytes_to_size(u64 bytes) } EXPORT_SYMBOL_GPL(pci_rebar_bytes_to_size); =20 +/** + * pci_rebar_size_to_bytes - Convert BAR Size to bytes + * @size: BAR Size as defined in the PCIe spec (0=3D1MB, bit 31=3D128TB) + * + * Return: BAR size in bytes. + */ +resource_size_t pci_rebar_size_to_bytes(int size) +{ + return 1ULL << (size + ilog2(PCI_REBAR_MIN_SIZE)); +} +EXPORT_SYMBOL_GPL(pci_rebar_size_to_bytes); + void pci_rebar_init(struct pci_dev *pdev) { pdev->rebar_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); diff --git a/include/linux/pci.h b/include/linux/pci.h index 894e9020b07d..6f0c31290675 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1421,6 +1421,7 @@ void pci_release_resource(struct pci_dev *dev, int re= sno); =20 /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); +resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); =20 --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EFEA2C11FC; Thu, 11 Sep 2025 07:57:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Fix the copy-pasted errors in the Resizable BAR handling functions kernel doc and generally improve wording choices. Fix the formatting errors of the Return: line. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/rebar.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 020ed7a1b3aa..64315dd8b6bb 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -58,8 +58,9 @@ void pci_rebar_init(struct pci_dev *pdev) * @bar: BAR to find * * Helper to find the position of the ctrl register for a BAR. - * Returns -ENOTSUPP if resizable BARs are not supported at all. - * Returns -ENOENT if no ctrl register for the BAR could be found. + * + * Return: %-ENOTSUPP if resizable BARs are not supported at all, + * %-ENOENT if no ctrl register for the BAR could be found. */ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) { @@ -92,12 +93,15 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) } =20 /** - * pci_rebar_get_possible_sizes - get possible sizes for BAR + * pci_rebar_get_possible_sizes - get possible sizes for Resizable BAR * @pdev: PCI device * @bar: BAR to query * * Get the possible sizes of a resizable BAR as bitmask defined in the spec - * (bit 0=3D1MB, bit 31=3D128TB). Returns 0 if BAR isn't resizable. + * (bit 0=3D1MB, bit 31=3D128TB). + * + * Return: A bitmask of possible sizes (0=3D1MB, 31=3D128TB), or %0 if BAR= isn't + * resizable. */ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { @@ -121,12 +125,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev= , int bar) EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 /** - * pci_rebar_get_current_size - get the current size of a BAR + * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device - * @bar: BAR to set size to + * @bar: BAR to get the size from * - * Read the size of a BAR from the resizable BAR config. - * Returns size if found or negative error code. + * Reads the current size of a BAR from the Resizable BAR config. + * + * Return: BAR Size if @bar is resizable (bit 0=3D1MB, bit 31=3D128TB), or + * negative on error. */ int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) { @@ -142,13 +148,14 @@ int pci_rebar_get_current_size(struct pci_dev *pdev, = int bar) } =20 /** - * pci_rebar_set_size - set a new size for a BAR + * pci_rebar_set_size - set a new size for a Resizable BAR * @pdev: PCI device * @bar: BAR to set size to - * @size: new size as defined in the spec (0=3D1MB, 31=3D128TB) + * @size: new size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) * * Set the new size of a BAR as defined in the spec. - * Returns zero if resizing was successful, error code otherwise. + * + * Return: %0 if resizing was successful, or negative on error. */ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) { --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 460062C327D; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Many callers of pci_rebar_get_possible_sizes() are interested in finding out if a particular BAR Size (PCIe r6.2 sec. 7.8.6.3) is supported by the particular BAR. Add pci_rebar_size_supported() into PCI core to make it easy for the drivers to determine if the BAR Size is supported or not. Use the new function in pci_resize_resource() and in pci_iov_vf_bar_set_size(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/iov.c | 7 +------ drivers/pci/rebar.c | 29 +++++++++++++++++++++++------ include/linux/pci.h | 1 + 3 files changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index ac4375954c94..51844a9176a0 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1334,7 +1334,6 @@ EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); */ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) { - u32 sizes; int ret; =20 if (!pci_resource_is_iov(resno)) @@ -1343,11 +1342,7 @@ int pci_iov_vf_bar_set_size(struct pci_dev *dev, int= resno, int size) if (pci_iov_is_memory_decoding_enabled(dev)) return -EBUSY; =20 - sizes =3D pci_rebar_get_possible_sizes(dev, resno); - if (!sizes) - return -ENOTSUPP; - - if (!(sizes & BIT(size))) + if (!pci_rebar_size_supported(dev, resno, size)) return -EINVAL; =20 ret =3D pci_rebar_set_size(dev, resno, size); diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 64315dd8b6bb..735d9afd6ab1 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -3,6 +3,7 @@ * PCI Resizable BAR Extended Capability handling. */ =20 +#include #include #include #include @@ -124,6 +125,27 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev,= int bar) } EXPORT_SYMBOL(pci_rebar_get_possible_sizes); =20 +/** + * pci_rebar_size_supported - check if size is supported for BAR + * @pdev: PCI device + * @bar: BAR to check + * @size: size as defined in the PCIe spec (0=3D1MB, 31=3D128TB) + * + * Return: %true if @bar is resizable and @size is a supported, otherwise + * %false. + */ +bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size) +{ + u64 sizes; + + sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + if (!sizes) + return false; + + return BIT(size) & sizes; +} +EXPORT_SYMBOL_GPL(pci_rebar_size_supported); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device @@ -231,7 +253,6 @@ int pci_resize_resource(struct pci_dev *dev, int resno,= int size) struct resource *res =3D pci_resource_n(dev, resno); struct pci_host_bridge *host; int old, ret; - u32 sizes; =20 /* Check if we must preserve the firmware's resource assignment */ host =3D pci_find_host_bridge(dev->bus); @@ -245,11 +266,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno= , int size) if (pci_resize_is_memory_decoding_enabled(dev, resno)) return -EBUSY; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported() that helps in checking if a BAR Size is supported for the BAR or not. Use it in i915_resize_lmem_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/= i915/gt/intel_region_lmem.c index 51bb27e10a4f..69c65fc8a72d 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -61,16 +61,12 @@ static void i915_resize_lmem_bar(struct drm_i915_privat= e *i915, resource_size_t current_size =3D roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR= )); =20 if (i915->params.lmem_bar_size) { - u32 bar_sizes; - - rebar_size =3D i915->params.lmem_bar_size * - (resource_size_t)SZ_1M; - bar_sizes =3D pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR); - + rebar_size =3D i915->params.lmem_bar_size * (resource_size_t)SZ_1M; if (rebar_size =3D=3D current_size) return; =20 - if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))) || + if (!pci_rebar_size_supported(pdev, GEN12_LMEM_BAR, + pci_rebar_bytes_to_size(rebar_size)) || rebar_size >=3D roundup_pow_of_two(lmem_size)) { rebar_size =3D lmem_size; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable PCI core provides pci_rebar_size_supported(), use it in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/gpu/drm/xe/xe_vram.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index e421a74fb87c..08a9abebfee7 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -21,8 +21,6 @@ #include "xe_sriov.h" #include "xe_vram.h" =20 -#define BAR_SIZE_SHIFT 20 - static void _resize_bar(struct xe_device *xe, int resno, resource_size_t size) { @@ -71,25 +69,22 @@ static void resize_vram_bar(struct xe_device *xe) =20 /* set to a specific size? */ if (force_vram_bar_size) { - u32 bar_size_bit; - - rebar_size =3D force_vram_bar_size * (resource_size_t)SZ_1M; + rebar_size =3D pci_rebar_bytes_to_size(force_vram_bar_size * + (resource_size_t)SZ_1M); =20 - bar_size_bit =3D bar_size_mask & BIT(pci_rebar_bytes_to_size(rebar_size)= ); - - if (!bar_size_bit) { + if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", - (u64)rebar_size >> 20, bar_size_mask, (u64)current_size >> 20); + (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, + bar_size_mask, (u64)current_size >> 20); return; } =20 - rebar_size =3D 1ULL << (__fls(bar_size_bit) + BAR_SIZE_SHIFT); - + rebar_size =3D pci_rebar_size_to_bytes(rebar_size); if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D 1ULL << (__fls(bar_size_mask) + BAR_SIZE_SHIFT); + rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFA562BEFEB; Thu, 11 Sep 2025 07:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577486; cv=none; b=h8YjV625Z2LZfm2XmqU/Sj17wzitSwBwXLkSvfLRKU1kwaB8FqA/yCd4jBED3lp61YHRdRDTc8HUIvCp2QdToKvZtBKLZRgD0VkdmvKWqIXX5+kp6+ieQLPoFOda8yfWi9CfqFFN1RZhtGIOlEuqZ5n2xo4U82cgV9mn4Kaaq7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577486; c=relaxed/simple; bh=eg1UYhv7Re0EQKia5CuYjI3vnVpbRQ0R1QZ1gddY+LU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=W2TZ2zlMwB8onsgugq7mGKBdONMFzJ9UuZ/G9gdWuHnyx9xAzStHFPRegXIkwLp98zM163DEKEQvEhlAn5rCg1hTYs2bcISdpaqhmpBHWXvELbMx/3r9TS+dXpeMN3/gRrHOvjaYkH1rx0i2Qo/tE+zIo0UeVZG1zMk65+0yjPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CFkxP3uI; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CFkxP3uI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757577485; x=1789113485; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eg1UYhv7Re0EQKia5CuYjI3vnVpbRQ0R1QZ1gddY+LU=; b=CFkxP3uIXuTSCz839v5g+qwBD1uSFgi1+ObmHrAtRcWVNmcqP/sUU49/ oC1sAd6oI9M9/m2yCjsDkVNHDkkp01AbrG9CyXD9yl6mKGJC494lW4TK4 ONxIULpuEoCSCSerbiEObpwoi+uNrtFXzZ9jtQpC2Pvr66STPyGQKT4oB 90T+FFt3PqY9cM9TWg8Ezt0gkyo0vrbtfse5JTh7FzgB0i4fuWsitxAPi Cg/f2BwN1Vo7knQ7l7pMSo/k0usqe8BSi8vxNnsaxOWqnJmizJrY1nF+c nCQhCVuZPYTYrIRWU5FXLJfWdeNyb0G3AugoczuQyCpGCVd/tnRSODPig A==; X-CSE-ConnectionGUID: 8FYYXpFGT92Eqa5hqX7Ygg== X-CSE-MsgGUID: LvZTb5GfQ8WNb8kqMte46A== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="63728896" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63728896" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:58:04 -0700 X-CSE-ConnectionGUID: CD1NoNyJQZOg/d1t/22LSA== X-CSE-MsgGUID: GxRSkfKFSa2BxA7V1GRA+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="174422502" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.187]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:57:57 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 08/11] PCI: Add pci_rebar_get_max_size() Date: Thu, 11 Sep 2025 10:56:02 +0300 Message-Id: <20250911075605.5277-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> References: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add pci_rebar_get_max_size() into PCI core to allow simplifying code that wants to know the maximum possible size for a Resizable BAR. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/pci/rebar.c | 23 +++++++++++++++++++++++ include/linux/pci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 735d9afd6ab1..76572c7a6e6e 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -146,6 +147,28 @@ bool pci_rebar_size_supported(struct pci_dev *pdev, in= t bar, int size) } EXPORT_SYMBOL_GPL(pci_rebar_size_supported); =20 +/** + * pci_rebar_get_max_size - get the maximum supported size of a BAR + * @pdev: PCI device + * @bar: BAR to query + * + * Get the largest supported size of a resizable BAR as a size. + * + * Returns: the maximum BAR size as defined in the PCIe spec (0=3D1MB, 31= =3D128TB), + * or %-NOENT on error. + */ +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) +{ + u32 sizes; + + sizes =3D pci_rebar_get_possible_sizes(pdev, bar); + if (!sizes) + return -ENOENT; + + return __fls(sizes); +} +EXPORT_SYMBOL_GPL(pci_rebar_get_max_size); + /** * pci_rebar_get_current_size - get the current size of a Resizable BAR * @pdev: PCI device diff --git a/include/linux/pci.h b/include/linux/pci.h index 917c3b897739..a4236aafad24 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1424,6 +1424,7 @@ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); +int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); =20 int pci_select_bars(struct pci_dev *dev, unsigned long flags); --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62AAA2D5940; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() from PCI core in resize_vram_bar() to simplify code. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/gpu/drm/xe/xe_vram.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index 08a9abebfee7..b063c072df1e 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -53,16 +53,11 @@ static void resize_vram_bar(struct xe_device *xe) resource_size_t current_size; resource_size_t rebar_size; struct resource *root_res; - u32 bar_size_mask; + int max_size, i; u32 pci_cmd; - int i; =20 /* gather some relevant info */ current_size =3D pci_resource_len(pdev, LMEM_BAR); - bar_size_mask =3D pci_rebar_get_possible_sizes(pdev, LMEM_BAR); - - if (!bar_size_mask) - return; =20 if (force_vram_bar_size < 0) return; @@ -76,7 +71,8 @@ static void resize_vram_bar(struct xe_device *xe) drm_info(&xe->drm, "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, - bar_size_mask, (u64)current_size >> 20); + pci_rebar_get_possible_sizes(pdev, LMEM_BAR), + (u64)current_size >> 20); return; } =20 @@ -84,7 +80,10 @@ static void resize_vram_bar(struct xe_device *xe) if (rebar_size =3D=3D current_size) return; } else { - rebar_size =3D pci_rebar_size_to_bytes(__fls(bar_size_mask)); + max_size =3D pci_rebar_get_max_size(pdev, LMEM_BAR); + if (max_size < 0) + return; + rebar_size =3D pci_rebar_size_to_bytes(max_size); =20 /* only resize if larger than current */ if (rebar_size <=3D current_size) --=20 2.39.5 From nobody Thu Oct 2 20:44:34 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2172D7806; Thu, 11 Sep 2025 07:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577511; cv=none; b=IU7xGcwG04nuM2Bl1yTkGspsJ6IiGV7Efbqsgp7aSqoUYfb4jcj1nqfloa81/4+OPSp50MR/EqtJ6wz4iA4WH4H/UTFuJGmm0P8wy6LqIM1Hm22TRSPcR4d/9NGOPuL5sWQn/gieABGn6oOSB/vPrp7j+nplGzKKmr5shU5teGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757577511; c=relaxed/simple; bh=YJbpUXJnomq+7nV94XeE/h+A16kP2CVabGQK0HSB9bY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=bYR6PxZxURVsxUvMH5oIMehLM3MeAuG3X5QOBXwXIXkrn/QCB1i3hL2GWMyuZiON8RBfrGm3VwFZHSZFT8vh/mOVcNq1Dz3SJUPzOwDLpVNnbYAzBrLNZ+uAGAf2DBuJNY6C0O2s++MhKLyccxbhtmZ8enWE/aqOd2oVCflHrzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GNP/NTa5; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GNP/NTa5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757577510; x=1789113510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YJbpUXJnomq+7nV94XeE/h+A16kP2CVabGQK0HSB9bY=; b=GNP/NTa5psVBLHibZnZXvdXxX2SOveVK3eindCuQ5jzLTDF2kAU9A6w7 BYWb8vJKupODiu7w3QvbkAD0oMHJG7J7/KFjrweqvoegtHBJOIZdQPMUY TPU3t+YWfvUHn1K3S71rwGudHIBdvrgavRJYZsrgMFwCcd67iVJXab9+b oaBgV4yKbwE0iDfqMZExp/PLLTh4TZmB/VjGUks4mGdG6pTTmSlAb53Kq uc1lcRW/66/Pho/Qc4eOjCSfRDx9+NGI7B1jA0D24D7165NRK0RCfVPBy OrrTWBC+ewmKCC3Z0QjJFPi/qWR+5Z/PoozMO52EFmj9Ib+RkHcfzNIsp A==; X-CSE-ConnectionGUID: E0WJSUVVQAGesh0KSHWgYg== X-CSE-MsgGUID: KnOqkItdQay1g3KhnlEkMg== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="63728934" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63728934" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:58:29 -0700 X-CSE-ConnectionGUID: Sbkad06OQkquDc+OlxBMIg== X-CSE-MsgGUID: eliGRZu4RQKlcbjTqR512A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,256,1751266800"; d="scan'208";a="174422525" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.187]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:58:22 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 10/11] drm/amdgpu: Use pci_rebar_get_max_size() Date: Thu, 11 Sep 2025 10:56:04 +0300 Message-Id: <20250911075605.5277-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> References: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Use pci_rebar_get_max_size() from PCI core to simplify code in amdgpu_device_resize_fb_bar(). Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index 01d234cf8156..c4ab503fb5d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1670,9 +1670,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device = *adev) int rbar_size =3D pci_rebar_bytes_to_size(adev->gmc.real_vram_size); struct pci_bus *root; struct resource *res; + int max_size, r; unsigned int i; u16 cmd; - int r; =20 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; @@ -1718,8 +1718,10 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device= *adev) return 0; =20 /* Limit the BAR size to what is available */ - rbar_size =3D min(fls(pci_rebar_get_possible_sizes(adev->pdev, 0)) - 1, - rbar_size); + max_size =3D pci_rebar_get_max_size(adev->pdev, 0); + if (max_size < 0) + return 0; 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d="scan'208";a="178823677" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.187]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2025 00:58:35 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Micha=C5=82=20Winiarski?= , Alex Deucher , amd-gfx@lists.freedesktop.org, David Airlie , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Jani Nikula , Joonas Lahtinen , Lucas De Marchi , Rodrigo Vivi , Simona Vetter , Tvrtko Ursulin , ?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org, =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Subject: [PATCH 11/11] PCI: Convert BAR sizes bitmasks to u64 Date: Thu, 11 Sep 2025 10:56:05 +0300 Message-Id: <20250911075605.5277-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> References: <20250911075605.5277-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable PCIe r6.2 section 7.8.6 defines resizable BAR sizes beyond the currently supported maximum of 128TB which will require more than u32 to store the entire bitmask. Convert Resizable BAR related functions to use u64 bitmask for BAR sizes to make the typing more future-proof. The support for the larger BAR sizes themselves is not added at this point. Signed-off-by: Ilpo J=C3=A4rvinen --- drivers/gpu/drm/xe/xe_vram.c | 2 +- drivers/pci/iov.c | 2 +- drivers/pci/pci-sysfs.c | 2 +- drivers/pci/rebar.c | 4 ++-- include/linux/pci.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c index b063c072df1e..196b75fa0c57 100644 --- a/drivers/gpu/drm/xe/xe_vram.c +++ b/drivers/gpu/drm/xe/xe_vram.c @@ -69,7 +69,7 @@ static void resize_vram_bar(struct xe_device *xe) =20 if (!pci_rebar_size_supported(pdev, LMEM_BAR, rebar_size)) { drm_info(&xe->drm, - "Requested size: %lluMiB is not supported by rebar sizes: 0x%x. Leavi= ng default: %lluMiB\n", + "Requested size: %lluMiB is not supported by rebar sizes: 0x%llx. Lea= ving default: %lluMiB\n", (u64)pci_rebar_size_to_bytes(rebar_size) >> 20, pci_rebar_get_possible_sizes(pdev, LMEM_BAR), (u64)current_size >> 20); diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 51844a9176a0..d2741c4f3315 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1370,7 +1370,7 @@ EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) { u64 vf_len =3D pci_resource_len(dev, resno); - u32 sizes; + u64 sizes; =20 if (!num_vfs) return 0; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 5eea14c1f7f5..b6920114d538 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1544,7 +1544,7 @@ static ssize_t __resource_resize_show(struct device *= dev, int n, char *buf) pci_config_pm_runtime_get(pdev); =20 ret =3D sysfs_emit(buf, "%016llx\n", - (u64)pci_rebar_get_possible_sizes(pdev, n)); + pci_rebar_get_possible_sizes(pdev, n)); =20 pci_config_pm_runtime_put(pdev); =20 diff --git a/drivers/pci/rebar.c b/drivers/pci/rebar.c index 76572c7a6e6e..b42bda80fabf 100644 --- a/drivers/pci/rebar.c +++ b/drivers/pci/rebar.c @@ -105,7 +105,7 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int= bar) * Return: A bitmask of possible sizes (0=3D1MB, 31=3D128TB), or %0 if BAR= isn't * resizable. */ -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) { int pos; u32 cap; @@ -159,7 +159,7 @@ EXPORT_SYMBOL_GPL(pci_rebar_size_supported); */ int pci_rebar_get_max_size(struct pci_dev *pdev, int bar) { - u32 sizes; + u64 sizes; =20 sizes =3D pci_rebar_get_possible_sizes(pdev, bar); if (!sizes) diff --git a/include/linux/pci.h b/include/linux/pci.h index a4236aafad24..bb10c7eb49e2 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1422,7 +1422,7 @@ void pci_release_resource(struct pci_dev *dev, int re= sno); /* Resizable BAR related routines */ int pci_rebar_bytes_to_size(u64 bytes); resource_size_t pci_rebar_size_to_bytes(int size); -u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); --=20 2.39.5