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Thu, 11 Sep 2025 11:38:44 -0700 (PDT) From: Stephan Gerhold Date: Thu, 11 Sep 2025 20:38:24 +0200 Subject: [PATCH 1/4] arm64: dts: qcom: x1e80100: Add IRIS video codec Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-x1e-iris-dt-v1-1-63caf0fd202c@linaro.org> References: <20250911-x1e-iris-dt-v1-0-63caf0fd202c@linaro.org> In-Reply-To: <20250911-x1e-iris-dt-v1-0-63caf0fd202c@linaro.org> To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dikshita Agarwal , Vikash Garodia , Bryan O'Donoghue , Neil Armstrong X-Mailer: b4 0.14.2 Add the IRIS video codec to accelerate video decoding/encoding. Copied mostly from sm8550.dtsi, only the opp-table is slightly different for X1E. For opp-240000000, we need to vote for a higher OPP on one of the power domains, because the voltage requirements for the PLL and the derived clocks differ (sm8550.dtsi has the same). Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Inspiron 14p --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 87 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index ba602eddfb54616ad38205570bc56a1f0e62c023..d6914165d055cd0c0e80541267e= 2671c7432799e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5234,6 +5234,93 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,x1e80100-iris", "qcom,sm8550-iris"; + + reg =3D <0 0x0aa00000 0 0xf0000>; + interrupts =3D ; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx"; + operating-points-v2 =3D <&iris_opp_table>; + + clocks =3D <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names =3D "iface", + "core", + "vcodec0_core"; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + memory-region =3D <&video_mem>; + + resets =3D <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names =3D "bus"; + + iommus =3D <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-481000000 { + opp-hz =3D /bits/ 64 <481000000>; + required-opps =3D <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible =3D "qcom,x1e80100-videocc"; reg =3D <0 0x0aaf0000 0 0x10000>; --=20 2.50.1