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Thu, 11 Sep 2025 11:34:17 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12270443823912362904 EX-QQ-RecipientCnt: 16 From: Troy Mitchell Date: Thu, 11 Sep 2025 11:34:05 +0800 Subject: [PATCH RESEND v4 3/3] clk: spacemit: fix i2s clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-k1-clk-i2s-generation-v4-3-cba204a50d48@linux.spacemit.com> References: <20250911-k1-clk-i2s-generation-v4-0-cba204a50d48@linux.spacemit.com> In-Reply-To: <20250911-k1-clk-i2s-generation-v4-0-cba204a50d48@linux.spacemit.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Alex Elder , Haylen Chu , Inochi Amaoto Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Jinmei Wei , Troy Mitchell X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Moreover, the current I2S clock configuration does not work as expected due to missing parent clocks. This patch adds the missing parent clocks, defines i2s_sysclk as a DDN clock, and i2s_bclk as a DIV clock. A special note for i2s_bclk: From the register definition, the i2s_bclk divider always implies an additional 1/2 factor. The following table shows the correspondence between index and frequency division coefficients: | index | div | |-------|-------| | 0 | 2 | | 1 | 4 | | 2 | 6 | | 3 | 8 | From a software perspective, introducing i2s_bclk_factor as the parent of i2s_bclk is sufficient to address the issue. The I2S-related clock registers can be found here [1]. Link: https://developer.spacemit.com/documentation?token=3DLCrKwWDasiJuROkVNusc2p= WTnEb [1] Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC= ") Co-developer: Jinmei Wei Suggested-by: Haylen Chu Signed-off-by: Jinmei Wei Signed-off-by: Troy Mitchell --- drivers/clk/spacemit/ccu-k1.c | 28 ++++++++++++++++++++++++++-- include/soc/spacemit/k1-syscon.h | 1 + 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 7155824673fb450971439873b6b6163faf48c7e5..50b472a2721121414f33e9fac63= 70f544e6b8229 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -141,8 +141,28 @@ CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCC= R_1, 16, 13, 0, 13, 2, 0); =20 CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1)= , 0); =20 -CCU_FACTOR_GATE_DEFINE(i2s_sysclk, CCU_PARENT_HW(pll1_d16_153p6), MPMU_ISC= CR, BIT(31), 50, 1); -CCU_FACTOR_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_sysclk), MPMU_ISCCR, BI= T(29), 1, 1); +CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); + +static const struct clk_parent_data i2s_153p6_base_parents[] =3D { + CCU_PARENT_HW(i2s_153p6), + CCU_PARENT_HW(pll1_d8_307p2), +}; +CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0= ); + +static const struct clk_parent_data i2s_sysclk_src_parents[] =3D { + CCU_PARENT_HW(pll1_d96_25p6), + CCU_PARENT_HW(i2s_153p6_base) +}; +CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30= , 1, BIT(31), 0); + +CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0= ); + +CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); +/* + * Divider of i2s_bclk always implies a 1/2 factor, which is + * described by i2s_bclk_factor. + */ +CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, = 27, 2, BIT(29), 0); =20 static const struct clk_parent_data apb_parents[] =3D { CCU_PARENT_HW(pll1_d96_25p6), @@ -756,6 +776,10 @@ static struct clk_hw *k1_ccu_mpmu_hws[] =3D { [CLK_I2S_BCLK] =3D &i2s_bclk.common.hw, [CLK_APB] =3D &apb_clk.common.hw, [CLK_WDT_BUS] =3D &wdt_bus_clk.common.hw, + [CLK_I2S_153P6] =3D &i2s_153p6.common.hw, + [CLK_I2S_153P6_BASE] =3D &i2s_153p6_base.common.hw, + [CLK_I2S_SYSCLK_SRC] =3D &i2s_sysclk_src.common.hw, + [CLK_I2S_BCLK_FACTOR] =3D &i2s_bclk_factor.common.hw, }; =20 static const struct spacemit_ccu_data k1_ccu_mpmu_data =3D { diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-sys= con.h index c59bd7a38e5b4219121341b9c0d9ffda13a9c3e2..354751562c55523ef8a22be931d= dd8aca9651084 100644 --- a/include/soc/spacemit/k1-syscon.h +++ b/include/soc/spacemit/k1-syscon.h @@ -30,6 +30,7 @@ to_spacemit_ccu_adev(struct auxiliary_device *adev) =20 /* MPMU register offset */ #define MPMU_POSR 0x0010 +#define MPMU_FCCR 0x0008 #define POSR_PLL1_LOCK BIT(27) #define POSR_PLL2_LOCK BIT(28) #define POSR_PLL3_LOCK BIT(29) --=20 2.51.0