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Acked-by: Rob Herring (Arm) Reviewed-by: Bryan O'Donoghue Signed-off-by: Wenmeng Liu --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 73144473b9b24e574bfc6bd7d8908f2f3895e087..54441a638da2b7feb4474126481= 0d7a0de319858 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,7 @@ properties: =20 - items: - enum: + - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci - qcom,sdm670-cci @@ -223,6 +224,7 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-cci - qcom,sm8550-cci - qcom,sm8650-cci - qcom,x1e80100-cci --=20 2.34.1 From nobody Thu Oct 2 20:23:38 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C71B320A0B; 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Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/lemans.dtsi | 268 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 268 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 3246ba05a88cd4979de70e1a3c3db3cd5c894379..f557cf1f2bb54fd8d92e910fb6b= fd17f39a1dd4f 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4358,6 +4358,162 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac13000 { + compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac13000 0x0 0x1000>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac14000 { + compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac14000 0x0 0x1000>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci2_0_default &cci2_1_default>; + pinctrl-1 =3D <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci3: cci@ac16000 { + compatible =3D "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac16000 0x0 0x1000>; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_3_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 =3D <&cci3_0_default &cci3_1_default>; + pinctrl-1 =3D <&cci3_0_sleep &cci3_1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ac78000 { compatible =3D "qcom,sa8775p-camss"; =20 @@ -5201,6 +5357,118 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; =20 + cci0_0_default: cci0-0-default-state { + pins =3D "gpio60", "gpio61"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci0_0_sleep: cci0-0-sleep-state { + pins =3D "gpio60", "gpio61"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci0_1_default: cci0-1-default-state { + pins =3D "gpio52", "gpio53"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci0_1_sleep: cci0-1-sleep-state { + pins =3D "gpio52", "gpio53"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_0_default: cci1-0-default-state { + pins =3D "gpio62", "gpio63"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci1_0_sleep: cci1-0-sleep-state { + pins =3D "gpio62", "gpio63"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci1_1_default: cci1-1-default-state { + pins =3D "gpio54", "gpio55"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci1_1_sleep: cci1-1-sleep-state { + pins =3D "gpio54", "gpio55"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_0_default: cci2-0-default-state { + pins =3D "gpio64", "gpio65"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci2_0_sleep: cci2-0-sleep-state { + pins =3D "gpio64", "gpio65"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci2_1_default: cci2-1-default-state { + pins =3D "gpio56", "gpio57"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci2_1_sleep: cci2-1-sleep-state { + pins =3D "gpio56", "gpio57"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_0_default: cci3-0-default-state { + pins =3D "gpio66", "gpio67"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + cci3_0_sleep: cci3-0-sleep-state { + pins =3D "gpio66", "gpio67"; + function =3D "cci_i2c"; + drive-strength =3D <2>; + bias-pull-down; + }; + + cci3_1_default: cci3-1-default-state { + pins =3D "gpio58", "gpio59"; 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Thu, 11 Sep 2025 11:56:53 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Thu, 11 Sep 2025 04:56:49 -0700 From: Wenmeng Liu Date: Thu, 11 Sep 2025 19:55:16 +0800 Subject: [PATCH v5 3/3] arm64: dts: qcom: lemans-evk-camera: Add DT overlay Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250911-camss_rb8-v5-3-c078e4e22d91@oss.qualcomm.com> References: <20250911-camss_rb8-v5-0-c078e4e22d91@oss.qualcomm.com> In-Reply-To: <20250911-camss_rb8-v5-0-c078e4e22d91@oss.qualcomm.com> To: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , , , CC: , , , , , Konrad Dybcio , Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The LeMans EVK board does not include a camera sensor by default, this overlay reflects the possibility of attaching an optional camera sensor. For this reason, the camera sensor configuration is placed in lemans-evk-camera.dtso, rather than modifying the base lemans-evk.dts. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Wenmeng Liu --- arch/arm64/boot/dts/qcom/Makefile | 4 + arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso | 97 +++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 0a7c308dec365263bbb7aa5f5cd306dbeacfd3f1..b27f60fbd527146027eebd4bb7b= 1f8a0a82b3af2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb + +lemans-evk-camera-dtbs :=3D lemans-evk.dtb lemans-evk-camera.dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk-camera.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso b/arch/arm64/b= oot/dts/qcom/lemans-evk-camera.dtso new file mode 100644 index 0000000000000000000000000000000000000000..769befadd4e47d25c376dffab35= 46b78ce656aad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_1p8: regulator-cam1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam1"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + vdda-pll-supply =3D <&vreg_l1c>; + vdda-phy-supply =3D <&vreg_l4a>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + clock-lanes =3D <7>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 =3D <&cci1_0_default>; + pinctrl-1 =3D <&cci1_0_sleep>; + + status =3D "okay"; +}; + +&cci1_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam1_default>; + pinctrl-names =3D "default"; + + clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + dovdd-supply =3D <&vreg_s4a>; + avdd-supply =3D <&vreg_cam1_1p8>; + + port { + imx577_ep1: endpoint { + clock-lanes =3D <7>; + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins =3D "gpio73"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + rst-pins { + pins =3D "gpio133"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.34.1