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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:56:00 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:55:01 +0800 Subject: [PATCH v4 04/13] phy: qcom: qmp-usbc: Add QCS615 DP PHY configuration and init data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-4-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602527; l=7744; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=IRVPgoUXyANCNGRPiPsQa/uGGl1547F/NtoWdkxg/Dk=; b=OryWGMA9lihNDO6oIk5RfVncPUsTbvkuo1u4tDk2/tg/Wc7v7D077T46SKKI2a9Tan9MOrNTn J7q6UiOJ8LDBwROfm7HKyeiu35MF4RehURhh+8QozwmAxlu94j5pvvN X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzMSBTYWx0ZWRfX3UbmPpEprPxo TkBMa8F1aTJdBE5hacd6RTtGfM/5nx9XJVag+GjETYBtKpl/4y2otBpY3WkPlyr2RIP/cAZStVB iELo3UfHgzYHC3SH4HlIhDIsq3uUGMtbjyh2ADw/mZxXs/p5jES5O/yjh06lKCIEfFr1dD7y88r Sh84vZGpMZk3wOa7TknFE6o+higfg5QT3pR3/H3WuFVw8pUSaLZo7mKLZHS3lFrA5gIE+NtVkwD +2L4aQlPQbcoA9QLpK0zige/jWMMKL/3oOZjjEZqLDQasYDHIID3Mjud+0Kv96MmV9RJq7FCGIx 19Em+h02LUhY0IduZZSsx5qGjZRtbmJ3R2I0RtSKUZgzHyWEsvAuLigTAmrHduubP0+RyI1AUgC HHW8NVpG X-Proofpoint-ORIG-GUID: Dpmf0TJHgangX3HISaxLiWgq05iN6YEp X-Proofpoint-GUID: Dpmf0TJHgangX3HISaxLiWgq05iN6YEp X-Authority-Analysis: v=2.4 cv=VIDdn8PX c=1 sm=1 tr=0 ts=68c2e302 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=nm05dWPNFHrtWLP4wFMA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060031 Introduce QCS615 hardware-specific configuration for DP PHY mode, including register offsets, initialization tables, voltage swing and pre-emphasis settings. Add qcs615-qmp-usb3-dp-phy compatible string to associate QCS615 platform with its USB/DP switchable PHY configuration. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 141 +++++++++++++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index de28c3464a40ea97740e16fe78cba4b927911d92..791c7d86c51769bc9c7c5e1c736= 03c87fc71a820 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -284,6 +284,86 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), +}; + struct qmp_usbc_offsets { u16 serdes; u16 pcs; @@ -443,6 +523,34 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_= v3_qcm2290 =3D { .rx2 =3D 0x800, }; =20 +static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 =3D { + .serdes =3D 0x0, + .pcs =3D 0xc00, + .pcs_misc =3D 0xa00, + .tx =3D 0x200, + .rx =3D 0x400, + .tx2 =3D 0x600, + .rx2 =3D 0x800, + .dp_serdes =3D 0x1c00, + .dp_txa =3D 0x1400, + .dp_txb =3D 0x1800, + .dp_dp_phy =3D 0x1000, +}; + +static const u8 qmp_dp_pre_emphasis_hbr2_rbr[4][4] =3D { + {0x00, 0x0b, 0x12, 0xff}, + {0x00, 0x0a, 0x12, 0xff}, + {0x00, 0x0c, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + +static const u8 qmp_dp_voltage_swing_hbr2_rbr[4][4] =3D { + {0x07, 0x0f, 0x14, 0xff}, + {0x11, 0x1d, 0x1f, 0xff}, + {0x18, 0x1f, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, =20 @@ -491,6 +599,36 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg =3D { + .offsets =3D &qmp_usbc_usb3dp_offsets_qcs615, + + .serdes_tbl =3D qcm2290_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl =3D qcm2290_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl =3D qcm2290_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl =3D qcm2290_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + + .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, + + .dp_serdes_tbl =3D qcs615_qmp_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl), + .dp_tx_tbl =3D qcs615_qmp_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_tx_tbl), + + .serdes_tbl_rbr =3D qcs615_qmp_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qcs615_qmp_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qcs615_qmp_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr2), + + .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, + .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, +}; + static int qmp_usbc_com_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); @@ -1161,6 +1299,9 @@ static const struct of_device_id qmp_usbc_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,qcm2290-qmp-usb3-phy", .data =3D &qcm2290_usb3phy_cfg, + }, { + .compatible =3D "qcom,qcs615-qmp-usb3-dp-phy", + .data =3D &qcs615_usb3dp_phy_cfg, }, { .compatible =3D "qcom,qcs615-qmp-usb3-phy", .data =3D &qcm2290_usb3phy_cfg, --=20 2.34.1