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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:56:59 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:55:10 +0800 Subject: [PATCH v4 13/13] drm/msm/dp: Add support for lane mapping configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-13-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602528; l=3440; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=ydjAKX71QvKWvvFLsD1Bwlw16HeAPipo1gwgyRawXAA=; b=URK3ZuXt8hjr965TBLqTHuckNd4RoPiuWF52jnx2F/+KEB7ZTvapur4qpeUyfJbHmlYbZS0xK D3ebmdp3LzLAeFch1oItDUO95apaxHczikuX+uQP2i/doSYgA6mFisz X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-ORIG-GUID: 2eaGv_6DD3zkkes9vCjuFRY8NBxh3TO7 X-Proofpoint-GUID: 2eaGv_6DD3zkkes9vCjuFRY8NBxh3TO7 X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68c2e33d cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=knvC0gF5dBKrktezL5UA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfXzxGa2EkMf1gV mlWLZRxP2tJ0NfRnQW1deHxEeForoDabZVhx4dAv9cYArfJ+nVQVKUOkp+T029Mszhi5FycR+T7 DIMzDhMm7npAPjVM8ibUcHVXla228fwUywtKr1/zTStKyCUB0J+BLvDNCLZrVDRGzeWn9FyYxRc LbNpaE8Xp7mrSHOlF8WG/CpkB/p3TtA+W3Z/cOQCwQkvYEpsBziE6QFKGtaAHWj2wxjjcQKdVGu HCwWT8QIIwmckfjmC/5Lv5Tvj9+SQCt/bfZPocFg8pPWkr+2KU2NmSieNX2bw2kVo2ZQ64XOLPQ pHMFy3HMId8EJWpdib8Doq07jCKcDsq33rQb44dcrrt6MhUL9pomtKP6cnXyeFl6EQNvGbjRqAe NKJ53LFb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 QCS615 platform requires non-default logical-to-physical lane mapping due to its unique hardware routing. Unlike the standard mapping sequence <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit configuration via the data-lanes property in the device tree. This ensures correct signal routing between the DP controller and PHY. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++----- drivers/gpu/drm/msm/dp/dp_link.c | 12 ++++++++++-- drivers/gpu/drm/msm/dp/dp_link.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818= d20853ddec069 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) { - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 *lane_map =3D ctrl->link->lane_map; u32 ln_mapping; =20 - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + ln_mapping =3D lane_map[0] << LANE0_MAPPING_SHIFT; + ln_mapping |=3D lane_map[1] << LANE1_MAPPING_SHIFT; + ln_mapping |=3D lane_map[2] << LANE2_MAPPING_SHIFT; + ln_mapping |=3D lane_map[3] << LANE3_MAPPING_SHIFT; =20 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index caca947122c60abb2a01e295f3e254cf02e34502..7c7a4aa584eb42a0ca7c6ec45de= 585cde8639cb4 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -1242,6 +1242,7 @@ static int msm_dp_link_parse_dt(struct msm_dp_link *m= sm_dp_link) struct msm_dp_link_private *link; struct device_node *of_node; int cnt; + u32 lane_map[DP_MAX_NUM_DP_LANES] =3D {0}; =20 link =3D container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_lin= k); of_node =3D link->dev->of_node; @@ -1255,10 +1256,17 @@ static int msm_dp_link_parse_dt(struct msm_dp_link = *msm_dp_link) cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); } =20 - if (cnt > 0) + if (cnt > 0) { + struct device_node *endpoint; + msm_dp_link->max_dp_lanes =3D cnt; - else + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, -1); + of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt); + } else { msm_dp_link->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ + } + + memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeo= f(u32)); =20 msm_dp_link->max_dp_link_rate =3D msm_dp_link_link_frequencies(of_node); if (!msm_dp_link->max_dp_link_rate) diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_l= ink.h index 0684a962d4ec93f7da764c4af2e2154c7050329c..b1eb2de6d2a7693f17aa2f25665= 7110af839533d 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -74,6 +74,7 @@ struct msm_dp_link { struct msm_dp_link_phy_params phy_params; struct msm_dp_link_info link_params; =20 + u32 lane_map[DP_MAX_NUM_DP_LANES]; u32 max_dp_lanes; u32 max_dp_link_rate; }; --=20 2.34.1