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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:55:41 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:54:58 +0800 Subject: [PATCH v4 01/13] dt-bindings: phy: Add QMP USB3+DP PHY for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-1-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602527; l=3530; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=LgccMGQtMns6i0nd4D5JzFa/u0XEgWzMdMJHz1iq7Mg=; b=mXj8P2zI5LqxmvJf/ITJhpiVlig+/0otZwvxQRDsBRti9c9obJVcSQTesm+iB69NrWfS1lqLZ V6KJztXRPxcBV79k9PWjTr9xRHUa2hlg3SDAYgvXdXof961JAOSGaTy X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-ORIG-GUID: FVC1tJIxLu-2RDeSrQw_RBzh5ASONDUo X-Proofpoint-GUID: FVC1tJIxLu-2RDeSrQw_RBzh5ASONDUo X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68c2e2ee cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=z8W1oWq9hX_DlPyfQGsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfX6ahR7kxG3NEl nlAJ7uXO6i+7NjWcypP9XRoc6cE+UEWgWVrjcVuKN4e2H4iG/8hivBjkYk9Y6wS9xaeAooVZsAa G98EKxYUfWuZ/0tTp8e881e3ksdfXiI4249NtUZnVJNQRbVPAKWT1zaVlSGl3LAHtrZDuFI3sIN p/DFGvDuK4uLEmkT3b0ySXoU5lpiEJQMEgiGaC/8heisU0pT7cjZmxF54MSt7itJDpqGNQSxObN aUcB3YbvbE0FBVTigLj1m8eYuKsFwusIVt0lSQoTJZEFoCbPWzychAX/CtlQnQCBDYD8+82Y0mH GV8cWWVgr1RI7BXfT76M45pFQ4it+tkYZoYK4euTqNtU4AVkO7s7WYAtcvoPEX7dXeWfGIymY50 1XqzDflN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY on QCS615 Platform. This PHY supports both USB3 and DP functionality over USB-C, with PHY mode switching capability. It does not support combo mode. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 111 +++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..efb465c71c1b5870bd7ad3b0ec2= 15cf693a32f04 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) + +maintainers: + - Xiangxu Yin + +description: + The QMP PHY controller supports physical layer functionality for both US= B3 + and DisplayPort over USB-C. While it enables mode switching between USB3= and + DisplayPort, but does not support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-usb3-dp-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy_phy + - const: dp_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - description: offset of the PHY mode register + description: Clamp and PHY mode register present in the TCSR + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + - qcom,tcsr-reg + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e8000 { + compatible =3D "qcom,qcs615-qmp-usb3-dp-phy"; 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This is a preparatory cleanup to enable USB + DP dual mode. Reviewed-by: Dmitry Baryshkov Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 55 ++++++++++++++++------------= ---- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 5e7fcb26744a4401c3076960df9c0dcbec7fdef7..62920dd2aed39bbfddd54ba2682= e3d45d65a09c8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -342,11 +342,10 @@ struct qmp_usbc { =20 struct mutex phy_mutex; =20 + struct phy *usb_phy; enum phy_mode mode; unsigned int usb_init_count; =20 - struct phy *phy; - struct clk_fixed_rate pipe_clk_fixed; =20 struct typec_switch_dev *sw; @@ -454,7 +453,7 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 -static int qmp_usbc_init(struct phy *phy) +static int qmp_usbc_com_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -504,7 +503,7 @@ static int qmp_usbc_init(struct phy *phy) return ret; } =20 -static int qmp_usbc_exit(struct phy *phy) +static int qmp_usbc_com_exit(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -518,7 +517,7 @@ static int qmp_usbc_exit(struct phy *phy) return 0; } =20 -static int qmp_usbc_power_on(struct phy *phy) +static int qmp_usbc_usb_power_on(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -566,7 +565,7 @@ static int qmp_usbc_power_on(struct phy *phy) return ret; } =20 -static int qmp_usbc_power_off(struct phy *phy) +static int qmp_usbc_usb_power_off(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -587,20 +586,20 @@ static int qmp_usbc_power_off(struct phy *phy) return 0; } =20 -static int qmp_usbc_enable(struct phy *phy) +static int qmp_usbc_usb_enable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 mutex_lock(&qmp->phy_mutex); =20 - ret =3D qmp_usbc_init(phy); + ret =3D qmp_usbc_com_init(phy); if (ret) goto out_unlock; =20 - ret =3D qmp_usbc_power_on(phy); + ret =3D qmp_usbc_usb_power_on(phy); if (ret) { - qmp_usbc_exit(phy); + qmp_usbc_com_exit(phy); goto out_unlock; } =20 @@ -611,19 +610,19 @@ static int qmp_usbc_enable(struct phy *phy) return ret; } =20 -static int qmp_usbc_disable(struct phy *phy) +static int qmp_usbc_usb_disable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 qmp->usb_init_count--; - ret =3D qmp_usbc_power_off(phy); + ret =3D qmp_usbc_usb_power_off(phy); if (ret) return ret; - return qmp_usbc_exit(phy); + return qmp_usbc_com_exit(phy); } =20 -static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int subm= ode) +static int qmp_usbc_usb_set_mode(struct phy *phy, enum phy_mode mode, int = submode) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); =20 @@ -632,10 +631,10 @@ static int qmp_usbc_set_mode(struct phy *phy, enum ph= y_mode mode, int submode) return 0; } =20 -static const struct phy_ops qmp_usbc_phy_ops =3D { - .init =3D qmp_usbc_enable, - .exit =3D qmp_usbc_disable, - .set_mode =3D qmp_usbc_set_mode, +static const struct phy_ops qmp_usbc_usb_phy_ops =3D { + .init =3D qmp_usbc_usb_enable, + .exit =3D qmp_usbc_usb_disable, + .set_mode =3D qmp_usbc_usb_set_mode, .owner =3D THIS_MODULE, }; =20 @@ -690,7 +689,7 @@ static int __maybe_unused qmp_usbc_runtime_suspend(stru= ct device *dev) =20 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); =20 - if (!qmp->phy->init_count) { + if (!qmp->usb_init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -710,7 +709,7 @@ static int __maybe_unused qmp_usbc_runtime_resume(struc= t device *dev) =20 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); =20 - if (!qmp->phy->init_count) { + if (!qmp->usb_init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -865,11 +864,11 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, qmp->orientation =3D orientation; =20 if (qmp->usb_init_count) { - qmp_usbc_power_off(qmp->phy); - qmp_usbc_exit(qmp->phy); + qmp_usbc_usb_power_off(qmp->usb_phy); + qmp_usbc_com_exit(qmp->usb_phy); =20 - qmp_usbc_init(qmp->phy); - qmp_usbc_power_on(qmp->phy); + qmp_usbc_com_init(qmp->usb_phy); + qmp_usbc_usb_power_on(qmp->usb_phy); } =20 mutex_unlock(&qmp->phy_mutex); @@ -1097,14 +1096,14 @@ static int qmp_usbc_probe(struct platform_device *p= dev) if (ret) goto err_node_put; =20 - qmp->phy =3D devm_phy_create(dev, np, &qmp_usbc_phy_ops); - if (IS_ERR(qmp->phy)) { - ret =3D PTR_ERR(qmp->phy); + qmp->usb_phy =3D devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); + if (IS_ERR(qmp->usb_phy)) { + ret =3D PTR_ERR(qmp->usb_phy); dev_err(dev, "failed to create PHY: %d\n", ret); goto err_node_put; } =20 - phy_set_drvdata(qmp->phy, qmp); + phy_set_drvdata(qmp->usb_phy, qmp); =20 of_node_put(np); =20 --=20 2.34.1 From nobody Thu Oct 2 20:23:04 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2AE13375DE for ; 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Also update qmp_usbc struct to track DP-related resources and state. This enables support for USB/DP switchable Type-C PHYs that operate in either mode. Signed-off-by: Xiangxu Yin Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 54 +++++++++++++++++++++++++++-= ---- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 62920dd2aed39bbfddd54ba2682e3d45d65a09c8..de28c3464a40ea97740e16fe78c= ba4b927911d92 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -293,13 +293,18 @@ struct qmp_usbc_offsets { /* for PHYs with >=3D 2 lanes */ u16 tx2; u16 rx2; + + u16 dp_serdes; + u16 dp_txa; + u16 dp_txb; + u16 dp_dp_phy; }; =20 -/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_usbc; struct qmp_phy_cfg { const struct qmp_usbc_offsets *offsets; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + /* Init sequence for USB PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; const struct qmp_phy_init_tbl *tx_tbl; @@ -309,6 +314,27 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; =20 + /* Init sequence for DP PHY blocks - serdes, tx, rbr, hbr, hbr2 */ + const struct qmp_phy_init_tbl *dp_serdes_tbl; + int dp_serdes_tbl_num; + const struct qmp_phy_init_tbl *dp_tx_tbl; + int dp_tx_tbl_num; + const struct qmp_phy_init_tbl *serdes_tbl_rbr; + int serdes_tbl_rbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr; + int serdes_tbl_hbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr2; + int serdes_tbl_hbr2_num; + + const u8 (*swing_tbl)[4][4]; + const u8 (*pre_emphasis_tbl)[4][4]; + + /* DP PHY callbacks */ + void (*dp_aux_init)(struct qmp_usbc *qmp); + void (*configure_dp_tx)(struct qmp_usbc *qmp); + int (*configure_dp_phy)(struct qmp_usbc *qmp); + int (*calibrate_dp_phy)(struct qmp_usbc *qmp); + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -329,24 +355,36 @@ struct qmp_usbc { void __iomem *rx; void __iomem *tx2; void __iomem *rx2; - - struct regmap *tcsr_map; - u32 vls_clamp_reg; + void __iomem *dp_dp_phy; + void __iomem *dp_tx; + void __iomem *dp_tx2; + void __iomem *dp_serdes; =20 struct clk *pipe_clk; + struct clk_fixed_rate pipe_clk_fixed; + + struct clk_hw dp_link_hw; + struct clk_hw dp_pixel_hw; struct clk_bulk_data *clks; int num_clks; int num_resets; struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; =20 + struct regmap *tcsr_map; + u32 vls_clamp_reg; + u32 dp_phy_mode_reg; + struct mutex phy_mutex; =20 struct phy *usb_phy; enum phy_mode mode; unsigned int usb_init_count; =20 - struct clk_fixed_rate pipe_clk_fixed; + struct phy *dp_phy; + unsigned int dp_aux_cfg; + struct phy_configure_opts_dp dp_opts; + unsigned int dp_init_count; =20 struct typec_switch_dev *sw; enum typec_orientation orientation; @@ -689,7 +727,7 @@ static int __maybe_unused qmp_usbc_runtime_suspend(stru= ct device *dev) =20 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); =20 - if (!qmp->usb_init_count) { + if (!qmp->usb_init_count && !qmp->dp_init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); 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Add qcs615-qmp-usb3-dp-phy compatible string to associate QCS615 platform with its USB/DP switchable PHY configuration. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 141 +++++++++++++++++++++++++++= ++++ 1 file changed, 141 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index de28c3464a40ea97740e16fe78cba4b927911d92..791c7d86c51769bc9c7c5e1c736= 03c87fc71a820 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -284,6 +284,86 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), +}; + struct qmp_usbc_offsets { u16 serdes; u16 pcs; @@ -443,6 +523,34 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_= v3_qcm2290 =3D { .rx2 =3D 0x800, }; =20 +static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 =3D { + .serdes =3D 0x0, + .pcs =3D 0xc00, + .pcs_misc =3D 0xa00, + .tx =3D 0x200, + .rx =3D 0x400, + .tx2 =3D 0x600, + .rx2 =3D 0x800, + .dp_serdes =3D 0x1c00, + .dp_txa =3D 0x1400, + .dp_txb =3D 0x1800, + .dp_dp_phy =3D 0x1000, +}; + +static const u8 qmp_dp_pre_emphasis_hbr2_rbr[4][4] =3D { + {0x00, 0x0b, 0x12, 0xff}, + {0x00, 0x0a, 0x12, 0xff}, + {0x00, 0x0c, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + +static const u8 qmp_dp_voltage_swing_hbr2_rbr[4][4] =3D { + {0x07, 0x0f, 0x14, 0xff}, + {0x11, 0x1d, 0x1f, 0xff}, + {0x18, 0x1f, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, =20 @@ -491,6 +599,36 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg =3D { + .offsets =3D &qmp_usbc_usb3dp_offsets_qcs615, + + .serdes_tbl =3D qcm2290_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl =3D qcm2290_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl =3D qcm2290_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl =3D qcm2290_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + + .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, + + .dp_serdes_tbl =3D qcs615_qmp_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl), + .dp_tx_tbl =3D qcs615_qmp_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_tx_tbl), + + .serdes_tbl_rbr =3D qcs615_qmp_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qcs615_qmp_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qcs615_qmp_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr2), + + .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, + .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, +}; 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This patch introduces regulator definitions with proper init_load_uA values based on each chip's power grid design. QCS615 USB3 PHY was previously reusing qcm2290_usb3phy_cfg, but its regulator requirements differ. A new qcs615_usb3phy_cfg is added to reflect the correct settings. Signed-off-by: Xiangxu Yin Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 70 +++++++++++++++++++---------= ---- 1 file changed, 41 insertions(+), 29 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 791c7d86c51769bc9c7c5e1c73603c87fc71a820..23a0efa7fc4418f379ac4c02fd9= 2080c7755dead 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -416,7 +416,7 @@ struct qmp_phy_cfg { int (*calibrate_dp_phy)(struct qmp_usbc *qmp); =20 /* regulators to be requested */ - const char * const *vreg_list; + const struct regulator_bulk_data *vreg_list; int num_vregs; =20 /* array of registers with different offsets */ @@ -508,9 +508,19 @@ static const char * const usb3phy_reset_l[] =3D { "phy_phy", "phy", }; =20 -/* list of regulators */ -static const char * const qmp_phy_vreg_l[] =3D { - "vdda-phy", "vdda-pll", +static const struct regulator_bulk_data qmp_phy_msm8998_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 68600 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 14200 }, +}; + +static const struct regulator_bulk_data qmp_phy_sm2290_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 66100 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 13300 }, +}; + +static const struct regulator_bulk_data qmp_phy_qcs615_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 50000 }, + { .supply =3D "vdda-pll", .init_load_uA =3D 20000 }, }; =20 static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 =3D { @@ -562,8 +572,8 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(msm8998_usb3_rx_tbl), .pcs_tbl =3D msm8998_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(msm8998_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_msm8998_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_msm8998_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout, }; =20 @@ -578,8 +588,8 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_sm2290_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_sm2290_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 @@ -594,8 +604,24 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(sdm660_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list =3D qmp_phy_msm8998_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_msm8998_vreg_l), + .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, +}; + +static const struct qmp_phy_cfg qcs615_usb3phy_cfg =3D { + .offsets =3D &qmp_usbc_offsets_v3_qcm2290, + + .serdes_tbl =3D qcm2290_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl =3D qcm2290_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl =3D qcm2290_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl =3D qcm2290_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .vreg_list =3D qmp_phy_qcs615_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_qcs615_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 @@ -627,6 +653,8 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { =20 .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, + .vreg_list =3D qmp_phy_qcs615_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_qcs615_vreg_l), }; =20 static int qmp_usbc_com_init(struct phy *phy) @@ -911,23 +939,6 @@ static const struct dev_pm_ops qmp_usbc_pm_ops =3D { qmp_usbc_runtime_resume, NULL) }; =20 -static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) -{ - const struct qmp_phy_cfg *cfg =3D qmp->cfg; - struct device *dev =3D qmp->dev; - int num =3D cfg->num_vregs; - int i; - - qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); - if (!qmp->vregs) - return -ENOMEM; - - for (i =3D 0; i < num; i++) - qmp->vregs[i].supply =3D cfg->vreg_list[i]; - - return devm_regulator_bulk_get(dev, num, qmp->vregs); -} - static int qmp_usbc_reset_init(struct qmp_usbc *qmp, const char *const *reset_list, int num_resets) @@ -1235,7 +1246,8 @@ static int qmp_usbc_probe(struct platform_device *pde= v) =20 mutex_init(&qmp->phy_mutex); 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This enables per-PHY customization and simplifies initialization logic for USB-only and USB/DP switchable PHYs. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 56 ++++++++++++++++++----------= ---- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 23a0efa7fc4418f379ac4c02fd92080c7755dead..663024b8c09124f2991b8e0537a= 9feb60baaa686 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -415,7 +415,8 @@ struct qmp_phy_cfg { int (*configure_dp_phy)(struct qmp_usbc *qmp); int (*calibrate_dp_phy)(struct qmp_usbc *qmp); =20 - /* regulators to be requested */ + const char * const *reset_list; + int num_resets; const struct regulator_bulk_data *vreg_list; int num_vregs; =20 @@ -447,7 +448,6 @@ struct qmp_usbc { struct clk_hw dp_pixel_hw; struct clk_bulk_data *clks; int num_clks; - int num_resets; struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; =20 @@ -508,6 +508,10 @@ static const char * const usb3phy_reset_l[] =3D { "phy_phy", "phy", }; =20 +static const char * const usb3dpphy_reset_l[] =3D { + "phy_phy", "dp_phy", +}; + static const struct regulator_bulk_data qmp_phy_msm8998_vreg_l[] =3D { { .supply =3D "vdda-phy", .init_load_uA =3D 68600 }, { .supply =3D "vdda-pll", .init_load_uA =3D 14200 }, @@ -572,6 +576,8 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(msm8998_usb3_rx_tbl), .pcs_tbl =3D msm8998_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(msm8998_usb3_pcs_tbl), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), .vreg_list =3D qmp_phy_msm8998_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_msm8998_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout, @@ -588,6 +594,8 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), .vreg_list =3D qmp_phy_sm2290_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_sm2290_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, @@ -604,6 +612,8 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D { .rx_tbl_num =3D ARRAY_SIZE(sdm660_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), .vreg_list =3D qmp_phy_msm8998_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_msm8998_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, @@ -620,6 +630,8 @@ static const struct qmp_phy_cfg qcs615_usb3phy_cfg =3D { .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), .vreg_list =3D qmp_phy_qcs615_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_qcs615_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, @@ -653,6 +665,9 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { =20 .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, + + .reset_list =3D usb3dpphy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3dpphy_reset_l), .vreg_list =3D qmp_phy_qcs615_vreg_l, .num_vregs =3D ARRAY_SIZE(qmp_phy_qcs615_vreg_l), }; @@ -671,13 +686,13 @@ static int qmp_usbc_com_init(struct phy *phy) return ret; } =20 - ret =3D reset_control_bulk_assert(qmp->num_resets, qmp->resets); + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); if (ret) { dev_err(qmp->dev, "reset assert failed\n"); goto err_disable_regulators; } =20 - ret =3D reset_control_bulk_deassert(qmp->num_resets, qmp->resets); + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); if (ret) { dev_err(qmp->dev, "reset deassert failed\n"); goto err_disable_regulators; @@ -700,7 +715,7 @@ static int qmp_usbc_com_init(struct phy *phy) return 0; =20 err_assert_reset: - reset_control_bulk_assert(qmp->num_resets, qmp->resets); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -712,7 +727,7 @@ static int qmp_usbc_com_exit(struct phy *phy) struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - reset_control_bulk_assert(qmp->num_resets, qmp->resets); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 @@ -939,25 +954,22 @@ static const struct dev_pm_ops qmp_usbc_pm_ops =3D { qmp_usbc_runtime_resume, NULL) }; =20 -static int qmp_usbc_reset_init(struct qmp_usbc *qmp, - const char *const *reset_list, - int num_resets) +static int qmp_usbc_reset_init(struct qmp_usbc *qmp) { + const struct qmp_phy_cfg *cfg =3D qmp->cfg; struct device *dev =3D qmp->dev; int i; int ret; =20 - qmp->resets =3D devm_kcalloc(dev, num_resets, + qmp->resets =3D devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; =20 - for (i =3D 0; i < num_resets; i++) - qmp->resets[i].id =3D reset_list[i]; + for (i =3D 0; i < cfg->num_resets; i++) + qmp->resets[i].id =3D cfg->reset_list[i]; =20 - qmp->num_resets =3D num_resets; - - ret =3D devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->reset= s); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->= resets); 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These callbacks are registered via qmp_phy_cfg to enable DP mode on USB/DP switchable Type-C PHYs. Add register define for QMP_DP_PHY_V2 series. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h | 21 +++ drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 251 ++++++++++++++++++++++= ++++ 2 files changed, 272 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h b/drivers/phy/qu= alcomm/phy-qcom-qmp-dp-phy-v2.h new file mode 100644 index 0000000000000000000000000000000000000000..8b9572d3cdebb70a0f3811f129a= 40aa78e184638 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_DP_PHY_V2_H_ +#define QCOM_PHY_QMP_DP_PHY_V2_H_ + +// /* Only for QMP V2 PHY - DP PHY registers */ +#define QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK 0x048 +#define QSERDES_V2_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c +#define QSERDES_V2_DP_PHY_AUX_BIST_CFG 0x050 + +#define QSERDES_V2_DP_PHY_VCO_DIV 0x068 +#define QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL 0x06c +#define QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL 0x088 + +#define QSERDES_V2_DP_PHY_SPARE0 0x0ac +#define QSERDES_V2_DP_PHY_STATUS 0x0c0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 663024b8c09124f2991b8e0537a9feb60baaa686..7b2b47320cbb2d16e4f316b0f52= fdc1bd09fe656 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -28,6 +28,9 @@ #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-misc-v3.h" =20 +#include "phy-qcom-qmp-dp-phy.h" +#include "phy-qcom-qmp-dp-phy-v2.h" + #define PHY_INIT_COMPLETE_TIMEOUT 10000 =20 /* set of registers with offsets different per-PHY */ @@ -619,6 +622,11 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp); +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp); +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp); +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp); + static const struct qmp_phy_cfg qcs615_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, =20 @@ -666,6 +674,11 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, =20 + .dp_aux_init =3D qcs615_qmp_dp_aux_init, + .configure_dp_tx =3D qcs615_qmp_configure_dp_tx, + .configure_dp_phy =3D qcs615_qmp_configure_dp_phy, + .calibrate_dp_phy =3D qcs615_qmp_calibrate_dp_phy, + .reset_list =3D usb3dpphy_reset_l, .num_resets =3D ARRAY_SIZE(usb3dpphy_reset_l), .vreg_list =3D qmp_phy_qcs615_vreg_l, @@ -736,6 +749,244 @@ static int qmp_usbc_com_exit(struct phy *phy) return 0; } =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp) +{ + writel(DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); + qmp->dp_aux_cfg =3D 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qmp->dp_dp_phy + QSERDES_V2_DP_PHY_AUX_INTERRUPT_MASK); +} + +static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + unsigned int v_level =3D 0, p_level =3D 0; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + if (dp_opts->lanes > 4) { + dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes); + return -EINVAL; + } + + for (i =3D 0; i < dp_opts->lanes; i++) { + v_level =3D max(v_level, dp_opts->voltage[i]); + p_level =3D max(p_level, dp_opts->pre[i]); + } + + if (v_level > 4 || p_level > 4) { + dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n", + v_level, p_level); + return -EINVAL; + } + + voltage_swing_cfg =3D (*cfg->swing_tbl)[v_level][p_level]; + pre_emphasis_cfg =3D (*cfg->pre_emphasis_tbl)[v_level][p_level]; + + voltage_swing_cfg |=3D DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |=3D DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + if (voltage_swing_cfg =3D=3D 0xff && pre_emphasis_cfg =3D=3D 0xff) + return -EINVAL; + + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + return 0; +} + +static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp) +{ + bool reverse =3D (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE); + u32 val; + + val =3D DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_= CTL_LANE_2_3_PWRDN; + + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + if (reverse) + writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); + else + writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); +} + +static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + u32 phy_vco_div; + unsigned long pixel_freq; + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div =3D 0x1; + pixel_freq =3D 1620000000UL / 2; + break; + case 2700: + phy_vco_div =3D 0x1; + pixel_freq =3D 2700000000UL / 2; + break; + case 5400: + phy_vco_div =3D 0x2; + pixel_freq =3D 5400000000UL / 4; + break; + default: + dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate); + return -EINVAL; + } + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_VCO_DIV); + + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); + + return 0; +} + +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp) +{ + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + + /* program default setting first */ + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + qcs615_qmp_configure_dp_swing(qmp); +} + +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp) +{ + u32 status; + int ret; + + qmp_usbc_configure_dp_mode(qmp); + + writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qmp->dp_dp_phy + QSERDES_V2_DP_PHY_TX2_TX3_LANE_CTL); + + ret =3D qmp_usbc_configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) { + dev_err(qmp->dev, "C_READY not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "FREQ_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PLL_LOCKED not ready\n"); + return -ETIMEDOUT; + } + + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "TSYNC_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); + return -ETIMEDOUT; + } + + writel(0x3f, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx + QSERDES_V3_TX_TX_POL_INV); + writel(0x3f, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx2 + QSERDES_V3_TX_TX_POL_INV); + + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V2_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:56:27 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:55:05 +0800 Subject: [PATCH v4 08/13] phy: qcom: qmp-usbc: Add USB/DP switchable PHY clk register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-8-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602528; l=8666; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=wXS/j3wmI7/itl+1AHpADAOwiZSv4uoaae+ybvM0UTw=; b=G5XhJlaCZ4TKhO3hLxoZ839bkwwozIUamKmhlhmyvZxWYmOvz98Q7AsX4iHEqrThg91OZ/TTj ENGhHWVndYfAu/Vqrj4b4lbRYbsm4JNG/FopmFTTCMIDdxl36dQmNkm X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-ORIG-GUID: 9KmjVWUtu0SPbGiH2JDRWJval2vBSgFA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTEwMDE3NyBTYWx0ZWRfX4Bjk7LFwdvby i9b8E+daHtfOnCHo+23HZf0cJVG9TURkW2TSsosEzJmT6s3ZcXRZMspo0b4/GR4ocJD4RXtbkk+ lR+XvdGj+Pcx2SBYrjZevpMLi3rJaEjPBCtjBZMMnW8eVtVuk5jeTOOxDiKdyubEHTJB6HGjaZG 0IV7EVuoEQTMAxyksx6gXm/KH1IvWGxQpVqJdnc0P3Qxnj3gdP6Yj6kIRFMgyG2B1bcfOc5wibw cNupSGBtmiNbFQpTfzKW7i7TtnntsYh3zGBWMNOdiLCWp1zYwIWg+J9o7LQI1v/bzySEeSFwa/n mKa5rAJ1xZwdPeRQZjqxSCdGavG0GP42BH++sc2bviWKTzKh5+hYqSQSrN4Uj0yYkG8P3LuHIQe 672opHDN X-Authority-Analysis: v=2.4 cv=WPB/XmsR c=1 sm=1 tr=0 ts=68c2e31d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=LV3rUWBglltBUjuJGHkA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: 9KmjVWUtu0SPbGiH2JDRWJval2vBSgFA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509100177 Add USB/DP switchable PHY clock registration and DT parsing for DP offsets. Extend qmp_usbc_register_clocks and clock provider logic to support both USB and DP instances. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 208 +++++++++++++++++++++++++++= ++-- 1 file changed, 195 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 7b2b47320cbb2d16e4f316b0f52fdc1bd09fe656..95a099de908e7f3478eb1e18326= b21d4014d8da6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include "phy-qcom-qmp-common.h" =20 @@ -1245,9 +1246,23 @@ static int qmp_usbc_clk_init(struct qmp_usbc *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) +static struct clk_hw *qmp_usbc_clks_hw_get(struct of_phandle_args *clkspec= , void *data) { - of_clk_del_provider(res); + struct qmp_usbc *qmp =3D data; + + if (clkspec->args_count =3D=3D 0) + return &qmp->pipe_clk_fixed.hw; + + switch (clkspec->args[0]) { + case QMP_USB43DP_USB3_PIPE_CLK: + return &qmp->pipe_clk_fixed.hw; + case QMP_USB43DP_DP_LINK_CLK: + return &qmp->dp_link_hw; + case QMP_USB43DP_DP_VCO_DIV_CLK: + return &qmp->dp_pixel_hw; + } + + return ERR_PTR(-EINVAL); } =20 /* @@ -1276,8 +1291,11 @@ static int phy_pipe_clk_register(struct qmp_usbc *qm= p, struct device_node *np) =20 ret =3D of_property_read_string(np, "clock-output-names", &init.name); if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; + char name[64]; + + /* Clock name is not mandatory. */ + snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); + init.name =3D name; } =20 init.ops =3D &clk_fixed_rate_ops; @@ -1286,19 +1304,176 @@ static int phy_pipe_clk_register(struct qmp_usbc *= qmp, struct device_node *np) fixed->fixed_rate =3D 125000000; fixed->hw.init =3D &init; =20 - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) + return devm_clk_hw_register(qmp->dev, &fixed->hw); +} + + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_r= ate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsig= ned long parent_rate) +{ + const struct qmp_usbc *qmp; + const struct phy_configure_opts_dp *dp_opts; + + qmp =3D container_of(hw, struct qmp_usbc, dp_pixel_hw); + + dp_opts =3D &qmp->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_pixel_clk_ops =3D { + .determine_rate =3D qmp_dp_pixel_clk_determine_rate, + .recalc_rate =3D qmp_dp_pixel_clk_recalc_rate, +}; + +static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_ra= te_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + const struct qmp_usbc *qmp; + const struct phy_configure_opts_dp *dp_opts; + + qmp =3D container_of(hw, struct qmp_usbc, dp_link_hw); + dp_opts =3D &qmp->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_link_clk_ops =3D { + .determine_rate =3D qmp_dp_link_clk_determine_rate, + .recalc_rate =3D qmp_dp_link_clk_recalc_rate, +}; + +static int phy_dp_clks_register(struct qmp_usbc *qmp, struct device_node *= np) +{ + struct clk_init_data init =3D { }; + char name[64]; + int ret; + + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); + init.ops =3D &qmp_dp_link_clk_ops; + init.name =3D name; + qmp->dp_link_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); + if (ret < 0) { + dev_err(qmp->dev, "link clk reg fail ret=3D%d\n", ret); + return ret; + } + + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); + init.ops =3D &qmp_dp_pixel_clk_ops; + init.name =3D name; + qmp->dp_pixel_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); + if (ret) { + dev_err(qmp->dev, "pxl clk reg fail ret=3D%d\n", ret); return ret; + } + + return 0; +} + +static int qmp_usbc_register_clocks(struct qmp_usbc *qmp, struct device_no= de *np) +{ + int ret; =20 - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); + ret =3D phy_pipe_clk_register(qmp, np); if (ret) return ret; =20 - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + if (qmp->dp_serdes !=3D 0) { + ret =3D phy_dp_clks_register(qmp, np); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(qmp->dev, qmp_usbc_clks_hw_get, qmp); } =20 #if IS_ENABLED(CONFIG_TYPEC) @@ -1429,6 +1604,13 @@ static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) if (IS_ERR(base)) return PTR_ERR(base); =20 + if (offs->dp_serdes !=3D 0) { + qmp->dp_serdes =3D base + offs->dp_serdes; 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Move USB PHY-only register configuration from com_init to qmp_usbc_usb_power_on. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 47 ++++++++++++++++++++--------= ---- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 95a099de908e7f3478eb1e18326b21d4014d8da6..c57596fe0d5cd5c15105ad8183c= cdc047953e4d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -33,6 +33,8 @@ #include "phy-qcom-qmp-dp-phy-v2.h" =20 #define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define SW_PORTSELECT_VAL BIT(0) +#define SW_PORTSELECT_MUX BIT(1) =20 /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { @@ -686,12 +688,16 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg= =3D { .num_vregs =3D ARRAY_SIZE(qmp_phy_qcs615_vreg_l), }; =20 +static void qmp_usbc_set_phy_mode(struct qmp_usbc *qmp, bool is_dp) +{ + if (qmp->tcsr_map && qmp->dp_phy_mode_reg) + regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, is_dp); +} + static int qmp_usbc_com_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; - void __iomem *pcs =3D qmp->pcs; - u32 val =3D 0; int ret; =20 ret =3D regulator_bulk_enable(cfg->num_vregs, qmp->vregs); @@ -716,16 +722,6 @@ static int qmp_usbc_com_init(struct phy *phy) if (ret) goto err_assert_reset; =20 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); - -#define SW_PORTSELECT_VAL BIT(0) -#define SW_PORTSELECT_MUX BIT(1) - /* Use software based port select and switch on typec orientation */ - val =3D SW_PORTSELECT_MUX; - if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) - val |=3D SW_PORTSELECT_VAL; - writel(val, qmp->pcs_misc); - return 0; =20 err_assert_reset: @@ -996,6 +992,14 @@ static int qmp_usbc_usb_power_on(struct phy *phy) unsigned int val; int ret; =20 + qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); + + /* Use software based port select and switch on typec orientation */ + val =3D SW_PORTSELECT_MUX; + if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) + val |=3D SW_PORTSELECT_VAL; + writel(val, qmp->pcs_misc); + qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); =20 @@ -1068,6 +1072,8 @@ static int qmp_usbc_usb_enable(struct phy *phy) if (ret) goto out_unlock; =20 + qmp_usbc_set_phy_mode(qmp, false); + ret =3D qmp_usbc_usb_power_on(phy); if (ret) { qmp_usbc_com_exit(phy); @@ -1493,6 +1499,7 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, qmp_usbc_com_exit(qmp->usb_phy); =20 qmp_usbc_com_init(qmp->usb_phy); + qmp_usbc_set_phy_mode(qmp, false); qmp_usbc_usb_power_on(qmp->usb_phy); } =20 @@ -1634,15 +1641,16 @@ static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) return 0; } =20 -static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp) +static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) { struct of_phandle_args tcsr_args; struct device *dev =3D qmp->dev; - int ret; + int ret, args_count; =20 - /* for backwards compatibility ignore if there is no property */ - ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 0, - &tcsr_args); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:56:40 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:55:07 +0800 Subject: [PATCH v4 10/13] phy: qcom: qmp-usbc: Add DP PHY ops for USB/DP switchable Type-C PHYs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-10-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602528; l=6119; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=/Dzt0Flvv5Npb/x7UQOUvomYu5H4XAyEv6INMeuWHJM=; b=aUG1scQ9zlx0rLGfM/7k8UjbPUtwjpp63jx6PPo5a4Rcy/Ao2U72sV7tzRnBN07WzKs6OWuwZ QrlJTWS85QpAFXhdru3ZpNehE5NLDr9Zr0jCZp175nlwVVgoHBSAoKK X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=H7Dbw/Yi c=1 sm=1 tr=0 ts=68c2e32a cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=3aaRT45y716cZRsrHfIA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: ZybCwFbBOzaA5qi6WffMiSSD3T2tdhhS X-Proofpoint-ORIG-GUID: ZybCwFbBOzaA5qi6WffMiSSD3T2tdhhS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzOSBTYWx0ZWRfX4hgNfqjsdZvw eWReU6OrW8mJs4R0mAVhMMkRmd3uFPWVlO+PL8yaN3s9rGzk8HSsov+X877jTKqgdqeQV54gYwZ kHoG4jj4AY3ACh99uf+wahF2YTBb3rdN18kUH/ZVhCOdVnu7hq7bQGIjxDqJFSDY7SaPmV0YfGy knPcKOSbiSjQEnbUxoFRl2NO1GIazmdCT9IW2lrNmigggKimOkMNwHTP1W6Pd768m4uELL7OsOK 0bhkn1gKJ94w/O5jW84gCI3GfDUuepgPkB7l54e2iL+AURerei+Hek7ATBoK/0myYg/l/Boikyz mVzfxacUAOFC3L5T4mNEH6E7zolQCT8k7ztSpdP3zlBXqCyVrBDdSAP//NB7Mf/viyBHUZ49ZZh tJGcw5Bb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060039 Define qmp_usbc_dp_phy_ops struct to support DP mode on USB/DP switchable PHYs. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 192 +++++++++++++++++++++++++++= +++- 1 file changed, 191 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index c57596fe0d5cd5c15105ad8183ccdc047953e4d5..613239d15a6a3bba47a647db4e6= 63713f127c93e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -1108,6 +1108,159 @@ static int qmp_usbc_usb_set_mode(struct phy *phy, e= num phy_mode mode, int submod return 0; } =20 +static int qmp_usbc_dp_enable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret; + + if (qmp->dp_init_count) { + dev_err(qmp->dev, "DP already inited\n"); + return 0; + } + + mutex_lock(&qmp->phy_mutex); + + ret =3D qmp_usbc_com_init(phy); + if (ret) + goto dp_init_unlock; + + qmp_usbc_set_phy_mode(qmp, true); + + cfg->dp_aux_init(qmp); + + qmp->dp_init_count++; + +dp_init_unlock: + mutex_unlock(&qmp->phy_mutex); + return ret; +} + +static int qmp_usbc_dp_disable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_com_exit(phy); + + qmp->dp_init_count--; + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_configure(struct phy *phy, union phy_configure_opts= *opts) +{ + const struct phy_configure_opts_dp *dp_opts =3D &opts->dp; + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + + mutex_lock(&qmp->phy_mutex); + + memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qmp->dp_opts.set_voltages) { + cfg->configure_dp_tx(qmp); + qmp->dp_opts.set_voltages =3D 0; + } + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_calibrate(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret =3D 0; + + mutex_lock(&qmp->phy_mutex); + + if (cfg->calibrate_dp_phy) { + ret =3D cfg->calibrate_dp_phy(qmp); + if (ret) { + dev_err(qmp->dev, "dp calibrate err(%d)\n", ret); + mutex_unlock(&qmp->phy_mutex); + return ret; + } + } + + mutex_unlock(&qmp->phy_mutex); + return 0; +} + +static int qmp_usbc_dp_serdes_init(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *serdes =3D qmp->dp_serdes; + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + + qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, + cfg->dp_serdes_tbl_num); + + switch (dp_opts->link_rate) { + case 1620: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + return 0; +} + +static int qmp_usbc_dp_power_on(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_dp_serdes_init(qmp); + + qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); + qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); + + /* Configure special DP tx tunings */ + cfg->configure_dp_tx(qmp); + + /* Configure link rate, swing, etc. */ + cfg->configure_dp_phy(qmp); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_power_off(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + + mutex_lock(&qmp->phy_mutex); + + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + static const struct phy_ops qmp_usbc_usb_phy_ops =3D { .init =3D qmp_usbc_usb_enable, .exit =3D qmp_usbc_usb_disable, @@ -1115,6 +1268,16 @@ static const struct phy_ops qmp_usbc_usb_phy_ops =3D= { .owner =3D THIS_MODULE, }; =20 +static const struct phy_ops qmp_usbc_dp_phy_ops =3D { + .init =3D qmp_usbc_dp_enable, + .exit =3D qmp_usbc_dp_disable, + .configure =3D qmp_usbc_dp_configure, + .calibrate =3D qmp_usbc_dp_calibrate, + .power_on =3D qmp_usbc_dp_power_on, + .power_off =3D qmp_usbc_dp_power_off, + .owner =3D THIS_MODULE, +}; + static void qmp_usbc_enable_autonomous_mode(struct qmp_usbc *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -1669,6 +1832,23 @@ static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) return 0; } =20 +static struct phy *qmp_usbc_phy_xlate(struct device *dev, const struct of_= phandle_args *args) +{ + struct qmp_usbc *qmp =3D dev_get_drvdata(dev); + + if (args->args_count =3D=3D 0) + return qmp->usb_phy; + + switch (args->args[0]) { + case QMP_USB43DP_USB3_PHY: + return qmp->usb_phy; + case QMP_USB43DP_DP_PHY: + return qmp->dp_phy; + } + + return ERR_PTR(-EINVAL); +} + static int qmp_usbc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1743,9 +1923,19 @@ static int qmp_usbc_probe(struct platform_device *pd= ev) =20 phy_set_drvdata(qmp->usb_phy, qmp); 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Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 613239d15a6a3bba47a647db4e663713f127c93e..866277036089c588cf0c63204ef= b91bbec5430ae 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -1061,6 +1061,19 @@ static int qmp_usbc_usb_power_off(struct phy *phy) return 0; } =20 +static int qmp_check_mutex_phy(struct qmp_usbc *qmp, bool is_dp) +{ + if ((is_dp && qmp->usb_init_count) || + (!is_dp && qmp->dp_init_count)) { + dev_err(qmp->dev, + "PHY is configured for %s, can not enable %s\n", + is_dp ? "USB" : "DP", is_dp ? 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b54a387cd4bsm2107453a12.35.2025.09.11.07.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Sep 2025 07:56:53 -0700 (PDT) From: Xiangxu Yin Date: Thu, 11 Sep 2025 22:55:09 +0800 Subject: [PATCH v4 12/13] drm/msm/dp: move link-specific parsing from dp_panel to dp_link Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250911-add-displayport-support-for-qcs615-platform-v4-12-2702bdda14ed@oss.qualcomm.com> References: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> In-Reply-To: <20250911-add-displayport-support-for-qcs615-platform-v4-0-2702bdda14ed@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757602528; l=9507; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=AKC+Fuyxo1BkLI1wsbmYerpKOrwfA3p00G/GMwPZd9M=; b=Z3/U8IQnRXTX5zBDO/gGB5EMPCiYrBxhLu6qiMx/COvqagvbqZ+f9Ng0QAJM8Q274cylKYQVw RvCNF0MD2kjDZrVGTQZYftg34OpjDjyaZZLhmSbzJgsnGQ9Dv8XdHPd X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-ORIG-GUID: TUhvY0RB8arv4RYta_JqeS47XMYLQgC- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzNSBTYWx0ZWRfXwvXwJzm/sG0v Jb5HahZr/jAyDsyWxMY93emlg9xs+x0woz6B+41VvBAy8Msl2OJI15xMExFcfkQEFQClDtJ7ZbN zZFqO4Hvwi05RuGhZvVp/acZlyBqKsOlpIpyw/cBVoida9uJ4nKPlAAsETfvQiJ5n8IJXPVAGG9 1bmDQzqz5k770f1iXd+EHumL3HgD0KMZlHf7Jf8I6XgMILjIWw26aBEVhTXAjlGvPazfPO4CiPa fhMvZ5ecdK44B5Prk24N4SmejU2s4k0/dpYjFb8HsRRUZxChb9GZLPsIodXGu/bjeVaEzwnnYvD rDNXRtlm6ofarH3nB398b72vMeavNB+eO3jImn57zn5goTlZwUFuspofcMIFIpvHFbZGGGAyfN5 +Ijy8Py4 X-Proofpoint-GUID: TUhvY0RB8arv4RYta_JqeS47XMYLQgC- X-Authority-Analysis: v=2.4 cv=N8UpF39B c=1 sm=1 tr=0 ts=68c2e337 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=MCbuoQoIk7qV-7NvgO8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-11_01,2025-09-11_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060035 Since max_dp_lanes and max_dp_link_rate are link-specific parameters, move their parsing from dp_panel to dp_link for better separation of concerns. Signed-off-by: Xiangxu Yin Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_link.c | 63 +++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_link.h | 4 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 78 +++++------------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 3 -- 4 files changed, 76 insertions(+), 72 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index 66e1bbd80db3a28f5f16d083486752007ceaf3f7..caca947122c60abb2a01e295f3e= 254cf02e34502 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -6,12 +6,14 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ =20 #include +#include #include =20 #include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" =20 +#define DP_LINK_RATE_HBR2 540000 /* kbytes */ #define DP_TEST_REQUEST_MASK 0x7F =20 enum audio_sample_rate { @@ -37,6 +39,7 @@ struct msm_dp_link_request { =20 struct msm_dp_link_private { u32 prev_sink_count; + struct device *dev; struct drm_device *drm_dev; struct drm_dp_aux *aux; struct msm_dp_link msm_dp_link; @@ -1210,10 +1213,65 @@ u32 msm_dp_link_get_test_bits_depth(struct msm_dp_l= ink *msm_dp_link, u32 bpp) return tbd; } =20 +static u32 msm_dp_link_link_frequencies(struct device_node *of_node) +{ + struct device_node *endpoint; + u64 frequency =3D 0; + int cnt; + + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ + if (!endpoint) + return 0; + + cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); + + if (cnt > 0) + of_property_read_u64_index(endpoint, "link-frequencies", + cnt - 1, &frequency); + of_node_put(endpoint); + + do_div(frequency, + 10 * /* from symbol rate to link rate */ + 1000); /* kbytes */ + + return frequency; +} + +static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link) +{ + struct msm_dp_link_private *link; + struct device_node *of_node; + int cnt; + + link =3D container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_lin= k); + of_node =3D link->dev->of_node; + + /* + * data-lanes is the property of msm_dp_out endpoint + */ + cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); + if (cnt < 0) { + /* legacy code, data-lanes is the property of mdss_dp node */ + cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); + } + + if (cnt > 0) + msm_dp_link->max_dp_lanes =3D cnt; + else + msm_dp_link->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ + + msm_dp_link->max_dp_link_rate =3D msm_dp_link_link_frequencies(of_node); + if (!msm_dp_link->max_dp_link_rate) + msm_dp_link->max_dp_link_rate =3D DP_LINK_RATE_HBR2; + + return 0; +} + struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux = *aux) { struct msm_dp_link_private *link; struct msm_dp_link *msm_dp_link; + int ret; =20 if (!dev || !aux) { DRM_ERROR("invalid input\n"); @@ -1225,9 +1283,14 @@ struct msm_dp_link *msm_dp_link_get(struct device *d= ev, struct drm_dp_aux *aux) return ERR_PTR(-ENOMEM); =20 link->aux =3D aux; + link->dev =3D dev; =20 mutex_init(&link->psm_mutex); msm_dp_link =3D &link->msm_dp_link; =20 + ret =3D msm_dp_link_parse_dt(msm_dp_link); + if (ret) + return ERR_PTR(ret); + return msm_dp_link; } diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_l= ink.h index ba47c6d19fbfacfc58031263e4a2f5a6d9c2c229..0684a962d4ec93f7da764c4af2e= 2154c7050329c 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -12,6 +12,7 @@ #define DS_PORT_STATUS_CHANGED 0x200 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +#define DP_MAX_NUM_DP_LANES 4 =20 struct msm_dp_link_info { unsigned char revision; @@ -72,6 +73,9 @@ struct msm_dp_link { struct msm_dp_link_test_audio test_audio; struct msm_dp_link_phy_params phy_params; struct msm_dp_link_info link_params; + + u32 max_dp_lanes; + u32 max_dp_link_rate; }; =20 /** diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 15b7f6c7146e1176a80b5c9d25896b1c8ede3aed..ad5d55bf009dbe60e61ca4f4c10= 8116333129203 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -16,9 +16,6 @@ =20 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) =20 -#define DP_MAX_NUM_DP_LANES 4 -#define DP_LINK_RATE_HBR2 540000 /* kbytes */ - struct msm_dp_panel_private { struct device *dev; struct drm_device *drm_dev; @@ -91,6 +88,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *ms= m_dp_panel) int rc, max_lttpr_lanes, max_lttpr_rate; struct msm_dp_panel_private *panel; struct msm_dp_link_info *link_info; + struct msm_dp_link *link; u8 *dpcd, major, minor; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); @@ -105,16 +103,20 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel= *msm_dp_panel) major =3D (link_info->revision >> 4) & 0x0f; minor =3D link_info->revision & 0x0f; =20 + link =3D panel->link; + drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", + link->max_dp_lanes, link->max_dp_link_rate); + link_info->rate =3D drm_dp_max_link_rate(dpcd); link_info->num_lanes =3D drm_dp_max_lane_count(dpcd); =20 /* Limit data lanes from data-lanes of endpoint property of dtsi */ - if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) - link_info->num_lanes =3D msm_dp_panel->max_dp_lanes; + if (link_info->num_lanes > link->max_dp_lanes) + link_info->num_lanes =3D link->max_dp_lanes; =20 /* Limit link rate from link-frequencies of endpoint property of dtsi */ - if (link_info->rate > msm_dp_panel->max_dp_link_rate) - link_info->rate =3D msm_dp_panel->max_dp_link_rate; + if (link_info->rate > link->max_dp_link_rate) + link_info->rate =3D link->max_dp_link_rate; =20 /* Limit data lanes from LTTPR capabilities, if any */ max_lttpr_lanes =3D drm_dp_lttpr_max_lane_count(panel->link->lttpr_common= _caps); @@ -173,9 +175,6 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *ms= m_dp_panel, =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); =20 - drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", - msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate); - rc =3D msm_dp_panel_read_dpcd(msm_dp_panel); if (rc) { DRM_ERROR("read dpcd failed %d\n", rc); @@ -648,60 +647,6 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *= msm_dp_panel) return 0; } =20 -static u32 msm_dp_panel_link_frequencies(struct device_node *of_node) -{ - struct device_node *endpoint; - u64 frequency =3D 0; - int cnt; - - endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ - if (!endpoint) - return 0; - - cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); - - if (cnt > 0) - of_property_read_u64_index(endpoint, "link-frequencies", - cnt - 1, &frequency); - of_node_put(endpoint); - - do_div(frequency, - 10 * /* from symbol rate to link rate */ - 1000); /* kbytes */ - - return frequency; -} - -static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) -{ - struct msm_dp_panel_private *panel; - struct device_node *of_node; - int cnt; - - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - of_node =3D panel->dev->of_node; - - /* - * data-lanes is the property of msm_dp_out endpoint - */ - cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); - if (cnt < 0) { - /* legacy code, data-lanes is the property of mdss_dp node */ - cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); - } - - if (cnt > 0) - msm_dp_panel->max_dp_lanes =3D cnt; - else - msm_dp_panel->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ - - msm_dp_panel->max_dp_link_rate =3D msm_dp_panel_link_frequencies(of_node); - if (!msm_dp_panel->max_dp_link_rate) - msm_dp_panel->max_dp_link_rate =3D DP_LINK_RATE_HBR2; - - return 0; -} - struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, @@ -709,7 +654,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; - int ret; =20 if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); @@ -729,10 +673,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; =20 - ret =3D msm_dp_panel_parse_dt(msm_dp_panel); - if (ret) - return ERR_PTR(ret); - return msm_dp_panel; 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Unlike the standard mapping sequence <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit configuration via the data-lanes property in the device tree. This ensures correct signal routing between the DP controller and PHY. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 +++++----- drivers/gpu/drm/msm/dp/dp_link.c | 12 ++++++++++-- drivers/gpu/drm/msm/dp/dp_link.h | 1 + 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818= d20853ddec069 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) { - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 *lane_map =3D ctrl->link->lane_map; u32 ln_mapping; =20 - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + ln_mapping =3D lane_map[0] << LANE0_MAPPING_SHIFT; + ln_mapping |=3D lane_map[1] << LANE1_MAPPING_SHIFT; + ln_mapping |=3D lane_map[2] << LANE2_MAPPING_SHIFT; + ln_mapping |=3D lane_map[3] << LANE3_MAPPING_SHIFT; =20 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index caca947122c60abb2a01e295f3e254cf02e34502..7c7a4aa584eb42a0ca7c6ec45de= 585cde8639cb4 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -1242,6 +1242,7 @@ static int msm_dp_link_parse_dt(struct msm_dp_link *m= sm_dp_link) struct msm_dp_link_private *link; struct device_node *of_node; int cnt; + u32 lane_map[DP_MAX_NUM_DP_LANES] =3D {0}; =20 link =3D container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_lin= k); of_node =3D link->dev->of_node; @@ -1255,10 +1256,17 @@ static int msm_dp_link_parse_dt(struct msm_dp_link = *msm_dp_link) cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); } =20 - if (cnt > 0) + if (cnt > 0) { + struct device_node *endpoint; + msm_dp_link->max_dp_lanes =3D cnt; - else + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, -1); + of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt); + } else { msm_dp_link->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ + } + + memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeo= f(u32)); =20 msm_dp_link->max_dp_link_rate =3D msm_dp_link_link_frequencies(of_node); if (!msm_dp_link->max_dp_link_rate) diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_l= ink.h index 0684a962d4ec93f7da764c4af2e2154c7050329c..b1eb2de6d2a7693f17aa2f25665= 7110af839533d 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -74,6 +74,7 @@ struct msm_dp_link { struct msm_dp_link_phy_params phy_params; struct msm_dp_link_info link_params; =20 + u32 lane_map[DP_MAX_NUM_DP_LANES]; u32 max_dp_lanes; u32 max_dp_link_rate; }; --=20 2.34.1