From nobody Thu Oct 2 21:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCFE92D1F72; Wed, 10 Sep 2025 21:06:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757538396; cv=none; b=upADakddHXiJqkqYZTdZqrL/f+op8TIYJ3rmtzy7ew52g4hhtz+4f9zHYSzPQ7mmZ7dLMGZHcdZsB7FVMMfB40eWa70YTOnGbfrB7qbS5t6lMbtnPEfCe51/m386DCNAEeA1XbTEjnMxQKINztSi8HJubirlCm1k6Yh9oqZoCIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757538396; c=relaxed/simple; bh=nTrDeurMGxl2lF9oLF6Hn3KKDLdUdZ8Q5sKmSFjl8e0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=no7Rgc/TeyPbk6Zp4loihJw3RzV0gXHDRa+YWsST7Car3zxdyfcdUUgmRqZlPrVr4yVoHBLiWtDDKXObzJ1CrCYTv16RwmKfgFRBizD+a9JdnDHHni6lskVQByWfeibfGj+GHOZzw/qhbI8i6C6veJovP7b5eRpzGKwQ10/zcZM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ee6yNLo/; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ee6yNLo/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1757538395; x=1789074395; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=nTrDeurMGxl2lF9oLF6Hn3KKDLdUdZ8Q5sKmSFjl8e0=; b=Ee6yNLo/TM7j/tgSchCrtXhxMgnLCLEve/pbdl3dyuQ0K1HV2+rXdfLV 1VvN8XLeuBb5CVAGK+EoUo2ypNEX9Ffr4EA38CZCnWTs67QhuLKDG+hAS up5/dxv7pm22d9LHIih6x3fAeDG8Migjl/TInjGNs986pYPvww9E0EKRY qDOA8opWn6BUpO2eEn8oXUNbIzU6cOKt43zj/0lG0Xjt/awEGNU9ZOOxo f6d99YFUQa/KN1yW3ePaRdvE+ys8sQPjtao66uRvtkNEVo5s45fP71e9G EPI2qs9do48otpEEV6JZoZt2ICLz2FrZbgMlUznSEMfL7B9GjS1W/pPdd g==; X-CSE-ConnectionGUID: u/eorHAuTuuEpwoas477Cg== X-CSE-MsgGUID: sU6AUtZGSh2oIWy/4kieKg== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="82448478" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="82448478" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2025 14:06:34 -0700 X-CSE-ConnectionGUID: goxn+0jNRy+KNuQOs/eUfw== X-CSE-MsgGUID: SRV0chvSQpOWGAxbfxMgyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,255,1751266800"; d="scan'208";a="177842751" Received: from cmdeoliv-mobl4.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.232]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2025 14:06:33 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 1/5] platform/x86:intel/pmc: Enable SSRAM support for Lunar Lake Date: Wed, 10 Sep 2025 14:06:21 -0700 Message-ID: <20250910210629.11198-2-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910210629.11198-1-xi.pardee@linux.intel.com> References: <20250910210629.11198-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Enable Lunar Lake platforms to achieve PMC information from Intel PMC SSRAM Telemetry driver and substate requirements data from telemetry region. Signed-off-by: Xi Pardee Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/lnl.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/in= tel/pmc/lnl.c index da513c234714b..e08a77c778c2c 100644 --- a/drivers/platform/x86/intel/pmc/lnl.c +++ b/drivers/platform/x86/intel/pmc/lnl.c @@ -13,6 +13,10 @@ =20 #include "core.h" =20 +#define SOCM_LPM_REQ_GUID 0x15099748 + +static const u8 LNL_LPM_REG_INDEX[] =3D {0, 4, 5, 6, 8, 9, 10, 11, 12, 13,= 14, 15, 16, 20}; + static const struct pmc_bit_map lnl_ltr_show_map[] =3D { {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, @@ -528,6 +532,16 @@ static const struct pmc_reg_map lnl_socm_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, .s0ix_blocker_maps =3D lnl_blk_maps, .s0ix_blocker_offset =3D LNL_S0IX_BLOCKER_OFFSET, + .lpm_reg_index =3D LNL_LPM_REG_INDEX, +}; + +static struct pmc_info lnl_pmc_info_list[] =3D { + { + .guid =3D SOCM_LPM_REQ_GUID, + .devid =3D PMC_DEVID_LNL_SOCM, + .map =3D &lnl_socm_reg_map, + }, + {} }; =20 #define LNL_NPU_PCI_DEV 0x643e @@ -557,6 +571,8 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct= pmc_dev_info *pmc_dev_in } =20 struct pmc_dev_info lnl_pmc_dev =3D { + .pci_func =3D 2, + .regmap_list =3D lnl_pmc_info_list, .map =3D &lnl_socm_reg_map, .suspend =3D cnl_suspend, .resume =3D lnl_resume, --=20 2.43.0 From nobody Thu Oct 2 21:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2769A2FA0C4; Wed, 10 Sep 2025 21:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757538398; cv=none; b=IxQppvXMURoAiztQrWwZn7m/gA6fL+RZRPHSHfvS/Zu7QMIwe2tX9nveegST0mHVjB+93iK0JwQm8UtC2EHtbvnPR9INNT294KNulOGjetzGT67nAWOnSaIv/ivASyLXPBfsyz+gJF0PQLh6neeYRLLYJsDF5a5pqCS9mdDxB/4= ARC-Message-Signature: i=1; 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d="scan'208";a="177842752" Received: from cmdeoliv-mobl4.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.232]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2025 14:06:34 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 2/5] platform/x86:intel/pmc: Move telemetry endpoint register handling Date: Wed, 10 Sep 2025 14:06:22 -0700 Message-ID: <20250910210629.11198-3-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910210629.11198-1-xi.pardee@linux.intel.com> References: <20250910210629.11198-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Move telemetry endpoint handling to pmc_core_get_telem_info(). This is a preparation patch to introduce a new table to obtain Low Power Mode substate requirement data for platforms starting from Panther Lake. Signed-off-by: Xi Pardee Reviewed-by: Ilpo J=C3=A4rvinen --- drivers/platform/x86/intel/pmc/core.c | 51 +++++++++++++-------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index 7d55af8e303cf..a1ab0e31eca7b 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -1399,36 +1399,23 @@ static u32 pmc_core_find_guid(struct pmc_info *list= , const struct pmc_reg_map *m * +----+---------------------------------------------------------+ * */ -static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc, s= truct pci_dev *pcidev) +static int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pm= c, + struct telem_endpoint *ep) { - struct telem_endpoint *ep; const u8 *lpm_indices; int num_maps, mode_offset =3D 0; int ret, mode; int lpm_size; - u32 guid; =20 lpm_indices =3D pmc->map->lpm_reg_index; num_maps =3D pmc->map->lpm_num_maps; lpm_size =3D LPM_MAX_NUM_MODES * num_maps; =20 - guid =3D pmc_core_find_guid(pmcdev->regmap_list, pmc->map); - if (!guid) - return -ENXIO; - - ep =3D pmt_telem_find_and_register_endpoint(pcidev, guid, 0); - if (IS_ERR(ep)) { - dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %pe", ep); - return -EPROBE_DEFER; - } - pmc->lpm_req_regs =3D devm_kzalloc(&pmcdev->pdev->dev, lpm_size * sizeof(u32), GFP_KERNEL); - if (!pmc->lpm_req_regs) { - ret =3D -ENOMEM; - goto unregister_ep; - } + if (!pmc->lpm_req_regs) + return -ENOMEM; =20 mode_offset =3D LPM_HEADER_OFFSET + LPM_MODE_OFFSET; pmc_for_each_mode(mode, pmcdev) { @@ -1442,23 +1429,21 @@ static int pmc_core_get_lpm_req(struct pmc_dev *pmc= dev, struct pmc *pmc, struct if (ret) { dev_err(&pmcdev->pdev->dev, "couldn't read Low Power Mode requirements: %d\n", ret); - goto unregister_ep; + return ret; } ++req_offset; } mode_offset +=3D LPM_REG_COUNT + LPM_MODE_OFFSET; } - -unregister_ep: - pmt_telem_unregister_endpoint(ep); - return ret; } =20 -static int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev, int func) +static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, int func) { struct pci_dev *pcidev __free(pci_dev_put) =3D NULL; + struct telem_endpoint *ep; unsigned int i; + u32 guid; int ret; =20 pcidev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, func)); @@ -1466,10 +1451,24 @@ static int pmc_core_ssram_get_lpm_reqs(struct pmc_d= ev *pmcdev, int func) return -ENODEV; =20 for (i =3D 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) { - if (!pmcdev->pmcs[i]) + struct pmc *pmc; + + pmc =3D pmcdev->pmcs[i]; + if (!pmc) continue; =20 - ret =3D pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i], pcidev); + guid =3D pmc_core_find_guid(pmcdev->regmap_list, pmc->map); + if (!guid) + return -ENXIO; + + ep =3D pmt_telem_find_and_register_endpoint(pcidev, guid, 0); + if (IS_ERR(ep)) { + dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %pe", ep); + return -EPROBE_DEFER; + } + + ret =3D pmc_core_pmt_get_lpm_req(pmcdev, pmc, ep); + pmt_telem_unregister_endpoint(ep); if (ret) return ret; } @@ -1583,7 +1582,7 @@ int generic_core_init(struct pmc_dev *pmcdev, struct = pmc_dev_info *pmc_dev_info) pmc_core_punit_pmt_init(pmcdev, pmc_dev_info->dmu_guid); =20 if (ssram) { - ret =3D pmc_core_ssram_get_lpm_reqs(pmcdev, pmc_dev_info->pci_func); + ret =3D pmc_core_get_telem_info(pmcdev, pmc_dev_info->pci_func); if (ret) goto unmap_regbase; } --=20 2.43.0 From nobody Thu Oct 2 21:39:19 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 645352FF153; Wed, 10 Sep 2025 21:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757538398; cv=none; b=nYNojE1b3M9JopIsPmOybUFoH1icOt+hnX3FsE6NeYU59xegLz8dzyxdfN5Rhya12r7kWuCt6LxcG/nvotNbpJkWNDNiO8HhImUEs943ZTXDPpNbzBkEah6uFNL9pO+4s8C+xOE9UuoFP8FyHrYW5b8h11YV1YypD21x2bjuMFM= ARC-Message-Signature: i=1; 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d="scan'208";a="177842753" Received: from cmdeoliv-mobl4.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.232]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2025 14:06:35 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 3/5] platform/x86:intel/pmc: Improve function to show substate header Date: Wed, 10 Sep 2025 14:06:23 -0700 Message-ID: <20250910210629.11198-4-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910210629.11198-1-xi.pardee@linux.intel.com> References: <20250910210629.11198-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor pmc_core_substate_req_header_show() to accept a new argument. This is a preparation patch to introduce a new way to show Low Power Mode substate requirement data for platforms starting from Panther Lake. Increased the size for the name column as the Low Power Mode requirement register name is longer in newer platforms. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index a1ab0e31eca7b..b3e9ea31db9c6 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -11,6 +11,11 @@ =20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +enum header_type { + HEADER_STATUS, + HEADER_VALUE, +}; + #include #include #include @@ -828,17 +833,22 @@ static int pmc_core_substate_l_sts_regs_show(struct s= eq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); =20 -static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_= index) +static void pmc_core_substate_req_header_show(struct seq_file *s, int pmc_= index, + enum header_type type) { struct pmc_dev *pmcdev =3D s->private; int mode; =20 - seq_printf(s, "%30s |", "Element"); + seq_printf(s, "%40s |", "Element"); pmc_for_each_mode(mode, pmcdev) seq_printf(s, " %9s |", pmc_lpm_modes[mode]); =20 - seq_printf(s, " %9s |", "Status"); - seq_printf(s, " %11s |\n", "Live Status"); + if (type =3D=3D HEADER_STATUS) { + seq_printf(s, " %9s |", "Status"); + seq_printf(s, " %11s |\n", "Live Status"); + } else { + seq_printf(s, " %9s |\n", "Value"); + } } =20 static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unuse= d) @@ -872,7 +882,7 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) continue; =20 /* Display the header */ - pmc_core_substate_req_header_show(s, pmc_index); + pmc_core_substate_req_header_show(s, pmc_index, HEADER_STATUS); =20 /* Loop over maps */ for (mp =3D 0; mp < num_maps; mp++) { @@ -910,7 +920,7 @@ static int pmc_core_substate_req_regs_show(struct seq_f= ile *s, void *unused) } =20 /* Display the element name in the first column */ - seq_printf(s, "pmc%d: %26s |", pmc_index, map[i].name); + seq_printf(s, "pmc%d: %34s |", pmc_index, map[i].name); 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10 Sep 2025 14:06:36 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 4/5] platform/x86:intel/pmc: Show substate requirement for S0ix blockers Date: Wed, 10 Sep 2025 14:06:24 -0700 Message-ID: <20250910210629.11198-5-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910210629.11198-1-xi.pardee@linux.intel.com> References: <20250910210629.11198-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to read and show S0ix blocker substate requirements. Starting from Panther Lake, substate requirement data is provided based on S0ix blockers instead of all low power mode requirements. For platforms that support this new feature, add support to display substate requirements based on S0ix blockers. Change the "substate_requirements" attribute of Intel PMC Core driver to show the substate requirements for each S0ix blocker and the corresponding S0ix blocker value. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/arl.c | 4 + drivers/platform/x86/intel/pmc/core.c | 121 +++++++++++++++++++++++--- drivers/platform/x86/intel/pmc/core.h | 14 +++ drivers/platform/x86/intel/pmc/lnl.c | 2 + drivers/platform/x86/intel/pmc/mtl.c | 2 + 5 files changed, 133 insertions(+), 10 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/in= tel/pmc/arl.c index 9d66d65e75779..17ad87b392abe 100644 --- a/drivers/platform/x86/intel/pmc/arl.c +++ b/drivers/platform/x86/intel/pmc/arl.c @@ -725,9 +725,11 @@ struct pmc_dev_info arl_pmc_dev =3D { .dmu_guid =3D ARL_PMT_DMU_GUID, .regmap_list =3D arl_pmc_info_list, .map =3D &arl_socs_reg_map, + .sub_req_show =3D &pmc_core_substate_req_regs_fops, .suspend =3D cnl_suspend, .resume =3D arl_resume, .init =3D arl_core_init, + .sub_req =3D pmc_core_pmt_get_lpm_req, }; =20 struct pmc_dev_info arl_h_pmc_dev =3D { @@ -735,7 +737,9 @@ struct pmc_dev_info arl_h_pmc_dev =3D { .dmu_guid =3D ARL_PMT_DMU_GUID, .regmap_list =3D arl_pmc_info_list, .map =3D &mtl_socm_reg_map, + .sub_req_show =3D &pmc_core_substate_req_regs_fops, .suspend =3D cnl_suspend, .resume =3D arl_h_resume, .init =3D arl_h_core_init, + .sub_req =3D pmc_core_pmt_get_lpm_req, }; diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/i= ntel/pmc/core.c index b3e9ea31db9c6..3a44644909015 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -851,6 +851,68 @@ static void pmc_core_substate_req_header_show(struct s= eq_file *s, int pmc_index, } } =20 +static int pmc_core_substate_blk_req_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev =3D s->private; + unsigned int pmc_index; + + for (pmc_index =3D 0; pmc_index < ARRAY_SIZE(pmcdev->pmcs); pmc_index++) { + const struct pmc_bit_map **maps; + unsigned int arr_size, r_idx; + u32 offset, counter; + u32 *lpm_req_regs; + struct pmc *pmc; + + pmc =3D pmcdev->pmcs[pmc_index]; + if (!pmc || !pmc->lpm_req_regs) + continue; + + lpm_req_regs =3D pmc->lpm_req_regs; + maps =3D pmc->map->s0ix_blocker_maps; + offset =3D pmc->map->s0ix_blocker_offset; + arr_size =3D pmc_core_lpm_get_arr_size(maps); + + /* Display the header */ + pmc_core_substate_req_header_show(s, pmc_index, HEADER_VALUE); + + for (r_idx =3D 0; r_idx < arr_size; r_idx++) { + const struct pmc_bit_map *map; + + for (map =3D maps[r_idx]; map->name; map++) { + int mode; + + if (!map->blk) + continue; + + counter =3D pmc_core_reg_read(pmc, offset); + seq_printf(s, "pmc%u: %34s |", pmc_index, map->name); + pmc_for_each_mode(mode, pmcdev) { + bool required =3D *lpm_req_regs & BIT(mode); + + seq_printf(s, " %9s |", required ? "Required" : " "); + } + seq_printf(s, " %9u |\n", counter); + offset +=3D map->blk * S0IX_BLK_SIZE; + lpm_req_regs++; + } + } + } + return 0; +} + +static int pmc_core_substate_blk_req_open(struct inode *inode, struct file= *file) +{ + return single_open(file, pmc_core_substate_blk_req_show, inode->i_private= ); +} + +const struct file_operations pmc_core_substate_blk_req_fops =3D { + .owner =3D THIS_MODULE, + .open =3D pmc_core_substate_blk_req_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unuse= d) { struct pmc_dev *pmcdev =3D s->private; @@ -941,7 +1003,19 @@ static int pmc_core_substate_req_regs_show(struct seq= _file *s, void *unused) } return 0; } -DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs); + +static int pmc_core_substate_req_regs_open(struct inode *inode, struct fil= e *file) +{ + return single_open(file, pmc_core_substate_req_regs_show, inode->i_privat= e); +} + +const struct file_operations pmc_core_substate_req_regs_fops =3D { + .owner =3D THIS_MODULE, + .open =3D pmc_core_substate_req_regs_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; =20 static unsigned int pmc_core_get_crystal_freq(void) { @@ -1274,7 +1348,7 @@ static void pmc_core_dbgfs_unregister(struct pmc_dev = *pmcdev) debugfs_remove_recursive(pmcdev->dbgfs_dir); } =20 -static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) +static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev= _info *pmc_dev_info) { struct pmc *primary_pmc =3D pmcdev->pmcs[PMC_IDX_MAIN]; struct dentry *dir; @@ -1341,7 +1415,7 @@ static void pmc_core_dbgfs_register(struct pmc_dev *p= mcdev) if (primary_pmc->lpm_req_regs) { debugfs_create_file("substate_requirements", 0444, pmcdev->dbgfs_dir, pmcdev, - &pmc_core_substate_req_regs_fops); + pmc_dev_info->sub_req_show); } =20 if (primary_pmc->map->pson_residency_offset && pmc_core_is_pson_residency= _enabled(pmcdev)) { @@ -1409,8 +1483,7 @@ static u32 pmc_core_find_guid(struct pmc_info *list, = const struct pmc_reg_map *m * +----+---------------------------------------------------------+ * */ -static int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pm= c, - struct telem_endpoint *ep) +int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc, stru= ct telem_endpoint *ep) { const u8 *lpm_indices; int num_maps, mode_offset =3D 0; @@ -1448,7 +1521,35 @@ static int pmc_core_pmt_get_lpm_req(struct pmc_dev *= pmcdev, struct pmc *pmc, return ret; } =20 -static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, int func) +int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev, struct pmc *pmc, + struct telem_endpoint *ep) +{ + u32 num_blocker, sample_offset; + unsigned int index; + u32 *req_offset; + int ret; + + num_blocker =3D pmc->map->num_s0ix_blocker; + sample_offset =3D pmc->map->blocker_req_offset; + + pmc->lpm_req_regs =3D devm_kcalloc(&pmcdev->pdev->dev, num_blocker, + sizeof(u32), GFP_KERNEL); + if (!pmc->lpm_req_regs) + return -ENOMEM; + + req_offset =3D pmc->lpm_req_regs; + for (index =3D 0; index < num_blocker; index++, req_offset++) { + ret =3D pmt_telem_read32(ep, index + sample_offset, req_offset, 1); + if (ret) { + dev_err(&pmcdev->pdev->dev, + "couldn't read Low Power Mode requirements: %d\n", ret); + return ret; + } + } + return 0; +} + +static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, struct pmc_dev_= info *pmc_dev_info) { struct pci_dev *pcidev __free(pci_dev_put) =3D NULL; struct telem_endpoint *ep; @@ -1456,7 +1557,7 @@ static int pmc_core_get_telem_info(struct pmc_dev *pm= cdev, int func) u32 guid; int ret; =20 - pcidev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, func)); + pcidev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, pmc_dev_info->= pci_func)); if (!pcidev) return -ENODEV; =20 @@ -1477,7 +1578,7 @@ static int pmc_core_get_telem_info(struct pmc_dev *pm= cdev, int func) return -EPROBE_DEFER; } =20 - ret =3D pmc_core_pmt_get_lpm_req(pmcdev, pmc, ep); + ret =3D pmc_dev_info->sub_req(pmcdev, pmc, ep); pmt_telem_unregister_endpoint(ep); if (ret) return ret; @@ -1592,7 +1693,7 @@ int generic_core_init(struct pmc_dev *pmcdev, struct = pmc_dev_info *pmc_dev_info) pmc_core_punit_pmt_init(pmcdev, pmc_dev_info->dmu_guid); =20 if (ssram) { - ret =3D pmc_core_get_telem_info(pmcdev, pmc_dev_info->pci_func); + ret =3D pmc_core_get_telem_info(pmcdev, pmc_dev_info); if (ret) goto unmap_regbase; } @@ -1767,7 +1868,7 @@ static int pmc_core_probe(struct platform_device *pde= v) pmcdev->pmc_xram_read_bit =3D pmc_core_check_read_lock_bit(primary_pmc); pmc_core_do_dmi_quirks(primary_pmc); =20 - pmc_core_dbgfs_register(pmcdev); + pmc_core_dbgfs_register(pmcdev, pmc_dev_info); pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) * pmc_core_adjust_slp_s0_step(primary_pmc, 1)); =20 diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index 47101f0dd09ce..b554805db689d 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -351,6 +351,8 @@ struct pmc_bit_map { * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG* * @s0ix_blocker_offset PWRMBASE offset to S0ix blocker counter + * @num_s0ix_blocker: Number of S0ix blockers + * @blocker_req_offset: Telemetry offset to S0ix blocker low power mode su= bstate requirement table * * Each PCH has unique set of register offsets and bit indexes. This struc= ture * captures them to have a common implementation. @@ -376,6 +378,8 @@ struct pmc_reg_map { const u32 ltr_ignore_max; const u32 pm_vric1_offset; const u32 s0ix_blocker_offset; + const u32 num_s0ix_blocker; + const u32 blocker_req_offset; /* Low Power Mode registers */ const int lpm_num_maps; const int lpm_num_modes; @@ -481,18 +485,22 @@ enum pmc_index { * SSRAM support. * @map: Pointer to a pmc_reg_map struct that contains platform * specific attributes of the primary PMC + * @sub_req_show: File operations to show substate requirements * @suspend: Function to perform platform specific suspend * @resume: Function to perform platform specific resume * @init: Function to perform platform specific init action + * @sub_req: Function to achieve low power mode substate requirements */ struct pmc_dev_info { u8 pci_func; u32 dmu_guid; struct pmc_info *regmap_list; const struct pmc_reg_map *map; + const struct file_operations *sub_req_show; void (*suspend)(struct pmc_dev *pmcdev); int (*resume)(struct pmc_dev *pmcdev); int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info); + int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endp= oint *ep); }; =20 extern const struct pmc_bit_map msr_map[]; @@ -542,6 +550,12 @@ extern struct pmc_dev_info wcl_pmc_dev; =20 void cnl_suspend(struct pmc_dev *pmcdev); int cnl_resume(struct pmc_dev *pmcdev); +int pmc_core_pmt_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc, stru= ct telem_endpoint *ep); +int pmc_core_pmt_get_blk_sub_req(struct pmc_dev *pmcdev, struct pmc *pmc, + struct telem_endpoint *ep); + +extern const struct file_operations pmc_core_substate_req_regs_fops; +extern const struct file_operations pmc_core_substate_blk_req_fops; =20 #define pmc_for_each_mode(mode, pmcdev) \ for (unsigned int __i =3D 0, __cond; \ diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/in= tel/pmc/lnl.c index e08a77c778c2c..6fa027e7071f4 100644 --- a/drivers/platform/x86/intel/pmc/lnl.c +++ b/drivers/platform/x86/intel/pmc/lnl.c @@ -574,7 +574,9 @@ struct pmc_dev_info lnl_pmc_dev =3D { .pci_func =3D 2, .regmap_list =3D lnl_pmc_info_list, .map =3D &lnl_socm_reg_map, + .sub_req_show =3D &pmc_core_substate_req_regs_fops, .suspend =3D cnl_suspend, .resume =3D lnl_resume, .init =3D lnl_core_init, + .sub_req =3D pmc_core_pmt_get_lpm_req, }; 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10 Sep 2025 14:06:37 -0700 X-CSE-ConnectionGUID: /3VqNt5mR2mC3+b6bx44FA== X-CSE-MsgGUID: rBjPClj+TxG8OkMrRJ9Dcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,255,1751266800"; d="scan'208";a="177842755" Received: from cmdeoliv-mobl4.amr.corp.intel.com (HELO xpardee-desk.lan) ([10.125.110.232]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2025 14:06:37 -0700 From: Xi Pardee To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com, david.e.box@linux.intel.com, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v4 5/5] platform/x86:intel/pmc: Enable SSRAM support for Panther Lake Date: Wed, 10 Sep 2025 14:06:25 -0700 Message-ID: <20250910210629.11198-6-xi.pardee@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910210629.11198-1-xi.pardee@linux.intel.com> References: <20250910210629.11198-1-xi.pardee@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable Panther Lake platforms to achieve PMC information from Intel PMC SSRAM Telemetry driver and substate requirements data from telemetry region. Signed-off-by: Xi Pardee --- drivers/platform/x86/intel/pmc/core.h | 2 ++ drivers/platform/x86/intel/pmc/ptl.c | 31 +++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/i= ntel/pmc/core.h index b554805db689d..f4dadb696a314 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -297,6 +297,8 @@ enum ppfear_regs { #define PTL_PMC_LTR_CUR_ASLT 0x1C28 #define PTL_PMC_LTR_CUR_PLT 0x1C2C #define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8 +#define PTL_NUM_S0IX_BLOCKER 106 +#define PTL_BLK_REQ_OFFSET 55 =20 /* Wildcat Lake */ #define WCL_PMC_LTR_RESERVED 0x1B64 diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/in= tel/pmc/ptl.c index 1bbec9856867d..1b35b84e06fa2 100644 --- a/drivers/platform/x86/intel/pmc/ptl.c +++ b/drivers/platform/x86/intel/pmc/ptl.c @@ -10,6 +10,17 @@ =20 #include "core.h" =20 +/* PMC SSRAM PMT Telemetry GUIDS */ +#define PCDP_LPM_REQ_GUID 0x47179370 + +/* + * Die Mapping to Product. + * Product PCDDie + * PTL-H PCD-H + * PTL-P PCD-P + * PTL-U PCD-P + */ + static const struct pmc_bit_map ptl_pcdp_pfear_map[] =3D { {"PMC_0", BIT(0)}, {"FUSE_OSSE", BIT(1)}, @@ -515,6 +526,22 @@ static const struct pmc_reg_map ptl_pcdp_reg_map =3D { .lpm_live_status_offset =3D MTL_LPM_LIVE_STATUS_OFFSET, .s0ix_blocker_maps =3D ptl_pcdp_blk_maps, .s0ix_blocker_offset =3D LNL_S0IX_BLOCKER_OFFSET, + .num_s0ix_blocker =3D PTL_NUM_S0IX_BLOCKER, + .blocker_req_offset =3D PTL_BLK_REQ_OFFSET, +}; + +static struct pmc_info ptl_pmc_info_list[] =3D { + { + .guid =3D PCDP_LPM_REQ_GUID, + .devid =3D PMC_DEVID_PTL_PCDH, + .map =3D &ptl_pcdp_reg_map, + }, + { + .guid =3D PCDP_LPM_REQ_GUID, + .devid =3D PMC_DEVID_PTL_PCDP, + .map =3D &ptl_pcdp_reg_map, + }, + {} }; =20 #define PTL_NPU_PCI_DEV 0xb03e @@ -543,8 +570,12 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struc= t pmc_dev_info *pmc_dev_in } =20 struct pmc_dev_info ptl_pmc_dev =3D { + .pci_func =3D 2, + .regmap_list =3D ptl_pmc_info_list, .map =3D &ptl_pcdp_reg_map, + .sub_req_show =3D &pmc_core_substate_blk_req_fops, .suspend =3D cnl_suspend, .resume =3D ptl_resume, .init =3D ptl_core_init, + .sub_req =3D pmc_core_pmt_get_blk_sub_req, }; --=20 2.43.0