From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2DA7F2F39B0; Wed, 10 Sep 2025 20:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537017; cv=none; b=oYFRimTFMz2D3SQjRqrZ89O2FZdGWJI6wyYZNp9UCX5sFCnIj86NUO8GIdCYztWsrLVqna1w2bX7GizfZn7gB+a0zG09FG1hJC8gpbXDfiPiSHR6uiWcvIQTSWKoYZsmAaF1tWrohpdk9MQBNmCqVITah3sK/zurLQrqk/7qnzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537017; c=relaxed/simple; bh=J7WYIMJ1B9F/M8R47YvJRLWbsBezK+JVZ5VEORwUi5U=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Af9Q6fTkVFcQPCIuPaGFWydeMsVZ73BNTyUlo9DOCvR2W2V7aXkTXoBMp94eeiQF6A4LgtvmadHNQbFLl45pCxW2jWNpwt5fHoTOBBL7Iq5cfCkNiNu6G2gND9AXVWcxLxRQP/9WLwjizTwQa5wNnrc6yknkeCMGMjly7ZjYOPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F1E9B1C0A; Wed, 10 Sep 2025 13:43:25 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AB7803F63F; Wed, 10 Sep 2025 13:43:29 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 01/29] ACPI / PPTT: Add a helper to fill a cpumask from a processor container Date: Wed, 10 Sep 2025 20:42:41 +0000 Message-Id: <20250910204309.20751-2-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ACPI MPAM table uses the UID of a processor container specified in the PPTT to indicate the subset of CPUs and cache topology that can access each MPAM System Component (MSC). This information is not directly useful to the kernel. The equivalent cpumask is needed instead. Add a helper to find the processor container by its id, then walk the possible CPUs to fill a cpumask with the CPUs that have this processor container as a parent. CC: Dave Martin Reviewed-by: Sudeep Holla Signed-off-by: James Morse Reviewed-by: Fenghua Yu Reviewed-by: Jonathan Cameron --- Changes since v1: * Replaced commit message with wording from Dave. * Fixed a stray plural. * Moved further down in the file to make use of get_pptt() helper. * Added a break to exit the loop early. Changes since RFC: * Removed leaf_flag local variable from acpi_pptt_get_cpus_from_container() Changes since RFC: * Dropped has_leaf_flag dodging of acpi_pptt_leaf_node() * Added missing : in kernel-doc * Made helper return void as this never actually returns an error. --- drivers/acpi/pptt.c | 83 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/acpi.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 54676e3d82dd..1728545d90b2 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -817,3 +817,86 @@ int find_acpi_cpu_topology_hetero_id(unsigned int cpu) return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE, ACPI_PPTT_ACPI_IDENTICAL); } + +/** + * acpi_pptt_get_child_cpus() - Find all the CPUs below a PPTT processor n= ode + * @table_hdr: A reference to the PPTT table. + * @parent_node: A pointer to the processor node in the @table_hdr. + * @cpus: A cpumask to fill with the CPUs below @parent_node. + * + * Walks up the PPTT from every possible CPU to find if the provided + * @parent_node is a parent of this CPU. + */ +static void acpi_pptt_get_child_cpus(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *parent_node, + cpumask_t *cpus) +{ + struct acpi_pptt_processor *cpu_node; + u32 acpi_id; + int cpu; + + cpumask_clear(cpus); + + for_each_possible_cpu(cpu) { + acpi_id =3D get_acpi_id_for_cpu(cpu); + cpu_node =3D acpi_find_processor_node(table_hdr, acpi_id); + + while (cpu_node) { + if (cpu_node =3D=3D parent_node) { + cpumask_set_cpu(cpu, cpus); + break; + } + cpu_node =3D fetch_pptt_node(table_hdr, cpu_node->parent); + } + } +} + +/** + * acpi_pptt_get_cpus_from_container() - Populate a cpumask with all CPUs = in a + * processor container + * @acpi_cpu_id: The UID of the processor container. + * @cpus: The resulting CPU mask. + * + * Find the specified Processor Container, and fill @cpus with all the cpus + * below it. + * + * Not all 'Processor' entries in the PPTT are either a CPU or a Processor + * Container, they may exist purely to describe a Private resource. CPUs + * have to be leaves, so a Processor Container is a non-leaf that has the + * 'ACPI Processor ID valid' flag set. + * + * Return: 0 for a complete walk, or an error if the mask is incomplete. + */ +void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus) +{ + struct acpi_pptt_processor *cpu_node; + struct acpi_table_header *table_hdr; + struct acpi_subtable_header *entry; + unsigned long table_end; + u32 proc_sz; + + cpumask_clear(cpus); + + table_hdr =3D acpi_get_pptt(); + if (!table_hdr) + return; + + table_end =3D (unsigned long)table_hdr + table_hdr->length; + entry =3D ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, + sizeof(struct acpi_table_pptt)); + proc_sz =3D sizeof(struct acpi_pptt_processor); + while ((unsigned long)entry + proc_sz <=3D table_end) { + cpu_node =3D (struct acpi_pptt_processor *)entry; + if (entry->type =3D=3D ACPI_PPTT_TYPE_PROCESSOR && + cpu_node->flags & ACPI_PPTT_ACPI_PROCESSOR_ID_VALID) { + if (!acpi_pptt_leaf_node(table_hdr, cpu_node)) { + if (cpu_node->acpi_processor_id =3D=3D acpi_cpu_id) { + acpi_pptt_get_child_cpus(table_hdr, cpu_node, cpus); + break; + } + } + } + entry =3D ACPI_ADD_PTR(struct acpi_subtable_header, entry, + entry->length); + } +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 1c5bb1e887cd..f97a9ff678cc 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1541,6 +1541,7 @@ int find_acpi_cpu_topology(unsigned int cpu, int leve= l); int find_acpi_cpu_topology_cluster(unsigned int cpu); int find_acpi_cpu_topology_package(unsigned int cpu); int find_acpi_cpu_topology_hetero_id(unsigned int cpu); +void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus); #else static inline int acpi_pptt_cpu_is_thread(unsigned int cpu) { @@ -1562,6 +1563,8 @@ static inline int find_acpi_cpu_topology_hetero_id(un= signed int cpu) { return -EINVAL; } +static inline void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, + cpumask_t *cpus) { } #endif =20 void acpi_arch_init(void); --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F11CE2FE596; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E8019153B; Wed, 10 Sep 2025 13:43:30 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0ED03F63F; Wed, 10 Sep 2025 13:43:34 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 02/29] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels Date: Wed, 10 Sep 2025 20:42:42 +0000 Message-Id: <20250910204309.20751-3-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In acpi_count_levels(), the initial value of *levels passed by the caller is really an implementation detail of acpi_count_levels(), so it is unreasonable to expect the callers of this function to know what to pass in for this parameter. The only sensible initial value is 0, which is what the only upstream caller (acpi_get_cache_info()) passes. Use a local variable for the starting cache level in acpi_count_levels(), and pass the result back to the caller via the function return value. Gid rid of the levels parameter, which has no remaining purpose. Fix acpi_get_cache_info() to match. Suggested-by: Jonathan Cameron Signed-off-by: James Morse Reviewed-by: Lorenzo Pieralisi Reviewed-by: Fenghua Yu Reviewed-by: Jonathan Cameron --- Changes since v1: * Rewritten commit message from Dave. * Minor changes to kernel doc comment. * Keep the much loved typo. Changes since RFC: * Made acpi_count_levels() return the levels value. --- drivers/acpi/pptt.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 1728545d90b2..7af7d62597df 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -177,14 +177,14 @@ acpi_find_cache_level(struct acpi_table_header *table= _hdr, } =20 /** - * acpi_count_levels() - Given a PPTT table, and a CPU node, count the cac= he - * levels and split cache levels (data/instruction). + * acpi_count_levels() - Given a PPTT table, and a CPU node, count the + * total number of levels and split cache levels (data/instruction). * @table_hdr: Pointer to the head of the PPTT table * @cpu_node: processor node we wish to count caches for - * @levels: Number of levels if success. * @split_levels: Number of split cache levels (data/instruction) if * success. Can by NULL. * + * Return: number of levels. * Given a processor node containing a processing unit, walk into it and c= ount * how many levels exist solely for it, and then walk up each level until = we hit * the root node (ignore the package level because it may be possible to h= ave @@ -192,14 +192,18 @@ acpi_find_cache_level(struct acpi_table_header *table= _hdr, * split cache levels (data/instruction) that exist at each level on the w= ay * up. */ -static void acpi_count_levels(struct acpi_table_header *table_hdr, - struct acpi_pptt_processor *cpu_node, - unsigned int *levels, unsigned int *split_levels) +static int acpi_count_levels(struct acpi_table_header *table_hdr, + struct acpi_pptt_processor *cpu_node, + unsigned int *split_levels) { + int starting_level =3D 0; + do { - acpi_find_cache_level(table_hdr, cpu_node, levels, split_levels, 0, 0); + acpi_find_cache_level(table_hdr, cpu_node, &starting_level, split_levels= , 0, 0); cpu_node =3D fetch_pptt_node(table_hdr, cpu_node->parent); } while (cpu_node); + + return starting_level; } =20 /** @@ -645,7 +649,7 @@ int acpi_get_cache_info(unsigned int cpu, unsigned int = *levels, if (!cpu_node) return -ENOENT; =20 - acpi_count_levels(table, cpu_node, levels, split_levels); + *levels =3D acpi_count_levels(table, cpu_node, split_levels); =20 pr_debug("Cache Setup: last_level=3D%d split_levels=3D%d\n", *levels, split_levels ? *split_levels : -1); --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C80B12FFDD7; Wed, 10 Sep 2025 20:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537026; cv=none; b=hh2OZDWamlppjU8v4iZ8TQcRJ3juoSvj6JhspgoTlEmmhC+B/Eo7pNHK2jsz4bNh1oHAu4iWOqYC2nqnK5TtEvjUm6D9e0+s+/xTT7+fQEcQJirlvzVaTB0ReY2xtaXmZNecynt7VzhbacS1qScAAH3SvP1NX5k4QbTeR1CDyJ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537026; c=relaxed/simple; bh=gBE6N6A/djmpRHltVB4CBWxBxh2eVJE7nJXFynkAxoA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sbO25K7TzpnHQGFx+3MuRcEWUC/Q4Zs0TFIBlxNy0N1AZ0YHf7PC+zDhiWZDxNv10D9pKXCJpV3uLxOEspyLaLS0w0DwvKie0CzgqGOf/sTyPbK1YcO84lrAnfGuOb5ZNEJKcv+50pDywREuO6RrnTHuf5EPmkYD32tx/2apB4s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDD251D34; Wed, 10 Sep 2025 13:43:35 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 981623F63F; Wed, 10 Sep 2025 13:43:39 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 03/29] ACPI / PPTT: Find cache level by cache-id Date: Wed, 10 Sep 2025 20:42:43 +0000 Message-Id: <20250910204309.20751-4-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MPAM table identifies caches by id. The MPAM driver also wants to know the cache level to determine if the platform is of the shape that can be managed via resctrl. Cacheinfo has this information, but only for CPUs that are online. Waiting for all CPUs to come online is a problem for platforms where CPUs are brought online late by user-space. Add a helper that walks every possible cache, until it finds the one identified by cache-id, then return the level. Signed-off-by: James Morse Reviewed-by: Fenghua Yu Reviewed-by: Lorenzo Pieralisi --- Changes since v1: * Droppeed the cleanup based table freeing, use acpi_get_pptt() instead. * Removed a confusing comment. * Clarified the kernel doc. Changes since RFC: * acpi_count_levels() now returns a value. * Converted the table-get stuff to use Jonathan's cleanup helper. * Dropped Sudeep's Review tag due to the cleanup change. --- drivers/acpi/pptt.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/acpi.h | 5 ++++ 2 files changed, 67 insertions(+) diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index 7af7d62597df..c5f2a51d280b 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -904,3 +904,65 @@ void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id= , cpumask_t *cpus) entry->length); } } + +/* + * find_acpi_cache_level_from_id() - Get the level of the specified cache + * @cache_id: The id field of the unified cache + * + * Determine the level relative to any CPU for the unified cache identifie= d by + * cache_id. This allows the property to be found even if the CPUs are off= line. + * + * The returned level can be used to group unified caches that are peers. + * + * The PPTT table must be rev 3 or later, + * + * If one CPUs L2 is shared with another as L3, this function will return + * an unpredictable value. + * + * Return: -ENOENT if the PPTT doesn't exist, the revision isn't supported= or + * the cache cannot be found. + * Otherwise returns a value which represents the level of the specified c= ache. + */ +int find_acpi_cache_level_from_id(u32 cache_id) +{ + u32 acpi_cpu_id; + int level, cpu, num_levels; + struct acpi_pptt_cache *cache; + struct acpi_table_header *table; + struct acpi_pptt_cache_v1 *cache_v1; + struct acpi_pptt_processor *cpu_node; + + table =3D acpi_get_pptt(); + if (!table) + return -ENOENT; + + if (table->revision < 3) + return -ENOENT; + + for_each_possible_cpu(cpu) { + acpi_cpu_id =3D get_acpi_id_for_cpu(cpu); + cpu_node =3D acpi_find_processor_node(table, acpi_cpu_id); + if (!cpu_node) + return -ENOENT; + num_levels =3D acpi_count_levels(table, cpu_node, NULL); + + /* Start at 1 for L1 */ + for (level =3D 1; level <=3D num_levels; level++) { + cache =3D acpi_find_cache_node(table, acpi_cpu_id, + ACPI_PPTT_CACHE_TYPE_UNIFIED, + level, &cpu_node); + if (!cache) + continue; + + cache_v1 =3D ACPI_ADD_PTR(struct acpi_pptt_cache_v1, + cache, + sizeof(struct acpi_pptt_cache)); + + if (cache->flags & ACPI_PPTT_CACHE_ID_VALID && + cache_v1->cache_id =3D=3D cache_id) + return level; + } + } + + return -ENOENT; +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index f97a9ff678cc..5bdca5546697 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1542,6 +1542,7 @@ int find_acpi_cpu_topology_cluster(unsigned int cpu); int find_acpi_cpu_topology_package(unsigned int cpu); int find_acpi_cpu_topology_hetero_id(unsigned int cpu); void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus); +int find_acpi_cache_level_from_id(u32 cache_id); #else static inline int acpi_pptt_cpu_is_thread(unsigned int cpu) { @@ -1565,6 +1566,10 @@ static inline int find_acpi_cpu_topology_hetero_id(u= nsigned int cpu) } static inline void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus) { } +static inline int find_acpi_cache_level_from_id(u32 cache_id) +{ + return -EINVAL; +} #endif =20 void acpi_arch_init(void); --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DE0C53019B5; Wed, 10 Sep 2025 20:43:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537031; cv=none; b=uoKNrGjLlIweDCyayyzDTz+fUCYp55uDYTf0nrcmT5iJ1mZWrjFWftHkStz7e2hzESOzq5lNIMGx7CY3M1Nj2ll+YHC62yTPm/SKwSmVnzNK/Nyf+a/GDPIKedzycuGCUQIegnIA/L2TI63vuPALOaxr8vfjGdQBn4TTcvyE1gQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 10 Sep 2025 13:43:44 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Rohit Mathew Subject: [PATCH v2 04/29] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id Date: Wed, 10 Sep 2025 20:42:44 +0000 Message-Id: <20250910204309.20751-5-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPAM identifies CPUs by the cache_id in the PPTT cache structure. The driver needs to know which CPUs are associated with the cache. The CPUs may not all be online, so cacheinfo does not have the information. Add a helper to pull this information out of the PPTT. CC: Rohit Mathew Signed-off-by: James Morse Reviewed-by: Sudeep Holla --- Changes since v1: * Added punctuation to the commit message. * Removed a comment about an alternative implementaion. * Made the loop continue with a warning if a CPU is missing from the PPTT. Changes since RFC: * acpi_count_levels() now returns a value. * Converted the table-get stuff to use Jonathan's cleanup helper. * Dropped Sudeep's Review tag due to the cleanup change. --- drivers/acpi/pptt.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ include/linux/acpi.h | 6 +++++ 2 files changed, 65 insertions(+) diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c index c5f2a51d280b..c379a9952b00 100644 --- a/drivers/acpi/pptt.c +++ b/drivers/acpi/pptt.c @@ -966,3 +966,62 @@ int find_acpi_cache_level_from_id(u32 cache_id) =20 return -ENOENT; } + +/** + * acpi_pptt_get_cpumask_from_cache_id() - Get the cpus associated with the + * specified cache + * @cache_id: The id field of the unified cache + * @cpus: Where to build the cpumask + * + * Determine which CPUs are below this cache in the PPTT. This allows the = property + * to be found even if the CPUs are offline. + * + * The PPTT table must be rev 3 or later, + * + * Return: -ENOENT if the PPTT doesn't exist, or the cache cannot be found. + * Otherwise returns 0 and sets the cpus in the provided cpumask. + */ +int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus) +{ + u32 acpi_cpu_id; + int level, cpu, num_levels; + struct acpi_pptt_cache *cache; + struct acpi_pptt_cache_v1 *cache_v1; + struct acpi_pptt_processor *cpu_node; + struct acpi_table_header *table __free(acpi_table) =3D acpi_get_table_ret= (ACPI_SIG_PPTT, 0); + + cpumask_clear(cpus); + + if (IS_ERR(table)) + return -ENOENT; + + if (table->revision < 3) + return -ENOENT; + + for_each_possible_cpu(cpu) { + acpi_cpu_id =3D get_acpi_id_for_cpu(cpu); + cpu_node =3D acpi_find_processor_node(table, acpi_cpu_id); + if (WARN_ON_ONCE(!cpu_node)) + continue; + num_levels =3D acpi_count_levels(table, cpu_node, NULL); + + /* Start at 1 for L1 */ + for (level =3D 1; level <=3D num_levels; level++) { + cache =3D acpi_find_cache_node(table, acpi_cpu_id, + ACPI_PPTT_CACHE_TYPE_UNIFIED, + level, &cpu_node); + if (!cache) + continue; + + cache_v1 =3D ACPI_ADD_PTR(struct acpi_pptt_cache_v1, + cache, + sizeof(struct acpi_pptt_cache)); + + if (cache->flags & ACPI_PPTT_CACHE_ID_VALID && + cache_v1->cache_id =3D=3D cache_id) + cpumask_set_cpu(cpu, cpus); + } + } + + return 0; +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 5bdca5546697..c5fd92cda487 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1543,6 +1543,7 @@ int find_acpi_cpu_topology_package(unsigned int cpu); int find_acpi_cpu_topology_hetero_id(unsigned int cpu); void acpi_pptt_get_cpus_from_container(u32 acpi_cpu_id, cpumask_t *cpus); int find_acpi_cache_level_from_id(u32 cache_id); +int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, cpumask_t *cpus); #else static inline int acpi_pptt_cpu_is_thread(unsigned int cpu) { @@ -1570,6 +1571,11 @@ static inline int find_acpi_cache_level_from_id(u32 = cache_id) { return -EINVAL; } +static inline int acpi_pptt_get_cpumask_from_cache_id(u32 cache_id, + cpumask_t *cpus) +{ + return -ENOENT; +} #endif =20 void acpi_arch_init(void); --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A1EE130216E; Wed, 10 Sep 2025 20:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537036; cv=none; b=YHYoo0NUyWNCtPRyQevR+TMjBgaE7SgxNzqITDF3bROupBsrkzIp2B8TRp8oWeej1iOf5kRFgWYCt5UNahZtZUx0BsmmDZzKNGIghtTd+5ggGEpisCS7Ri3pFP9ixRinHAOdNe643Lvjfg4FMGX1XwwJChPV2St0ewUA0cyklik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537036; c=relaxed/simple; bh=r/wErF3yjFa7BVljNh0RpUp11qxWDP8PxpBepFYisIg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dS2aC2sR82X0lIETnvP42WHO4yALhGoUzKjjEWtAFH+O1Nl6DGS4MiiNzxjGvbLSYf2tPKC/eBNvqmI2Wf3+cr91/X+U+OvMcdyS/DqHYvHPSHjejoraSCtfJbohivpd7ZIGtVyptV0PPmWSxHnO6JGgNsDJ0tYSJoKGR95OW6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB3B41D34; Wed, 10 Sep 2025 13:43:45 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A1F083F63F; Wed, 10 Sep 2025 13:43:49 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 05/29] arm64: kconfig: Add Kconfig entry for MPAM Date: Wed, 10 Sep 2025 20:42:45 +0000 Message-Id: <20250910204309.20751-6-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The bulk of the MPAM driver lives outside the arch code because it largely manages MMIO devices that generate interrupts. The driver needs a Kconfig symbol to enable it. As MPAM is only found on arm64 platforms, the arm64 tree is the most natural home for the Kconfig option. This Kconfig option will later be used by the arch code to enable or disable the MPAM context-switch code, and to register properties of CPUs with the MPAM driver. Signed-off-by: James Morse Reviewed-by: Jonathan Cameron CC: Dave Martin Reviewed-by: Ben Horgan Reviewed-by: Fenghua Yu --- Changes since v1: * Help text rewritten by Dave. --- arch/arm64/Kconfig | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index e9bbfacc35a6..4be8a13505bf 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2060,6 +2060,29 @@ config ARM64_TLB_RANGE ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a range of input addresses. =20 +config ARM64_MPAM + bool "Enable support for MPAM" + help + Memory System Resource Partitioning and Monitoring (MPAM) is an + optional extension to the Arm architecture that allows each + transaction issued to the memory system to be labelled with a + Partition identifier (PARTID) and Performance Monitoring Group + identifier (PMG). + + Memory system components, such as the caches, can be configured with + policies to control how much of various physical resources (such as + memory bandwidth or cache memory) the transactions labelled with each + PARTID can consume. Depending on the capabilities of the hardware, + the PARTID and PMG can also be used as filtering criteria to measure + the memory system resource consumption of different parts of a + workload. + + Use of this extension requires CPU support, support in the + Memory System Components (MSC), and a description from firmware + of where the MSCs are in the address space. + + MPAM is exposed to user-space via the resctrl pseudo filesystem. + endmenu # "ARMv8.4 architectural features" =20 menu "ARMv8.5 architectural features" --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36F6E305043; Wed, 10 Sep 2025 20:43:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537042; cv=none; b=kPZKMrURXLFW9eXK/oVAhKlwKVeFo72WQUuPf1F/OgjJpuOy5rZKSO/X6AoDTNRBb0r2EQ/d47zYtNY19liehzTdT9C0XFqLYL83msHlkIoSXkjTimStCoIg3CmpUHw27GOLG3N6CaFQrf7+IqkzyLME9Oip68id4l0KkvtsDXs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537042; c=relaxed/simple; bh=vmlO4Y/VGqKozy4neA0bH3KzEg4QV7PxxdO6i/UCsus=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=blfFPrYSTnP/hkAYlrY4/jkFb+Qbdsus0Kd87rA4haSU50nLL2M0tkfErzfl5RcSXTuYAlZSdybF6G+Z7RAVEH5bK44d4Gzw/SNN45VfZS7OfIITcpduwaUm4Dryh2rxfImLslc7/BZELi8Ze2887vLJ+5n0mwpA1EVQV1tzz68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3801D1EDB; Wed, 10 Sep 2025 13:43:51 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C31C13F63F; Wed, 10 Sep 2025 13:43:54 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 06/29] ACPI / MPAM: Parse the MPAM table Date: Wed, 10 Sep 2025 20:42:46 +0000 Message-Id: <20250910204309.20751-7-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add code to parse the arm64 specific MPAM table, looking up the cache level from the PPTT and feeding the end result into the MPAM driver. For now the MPAM hook mpam_ris_create() is stubbed out, but will update the MPAM driver with optional discovered data. CC: Carl Worth Link: https://developer.arm.com/documentation/den0065/3-0bet/?lang=3Den Signed-off-by: James Morse Reviewed-by: Lorenzo Pieralisi --- Changes since v1: * Whitespace. * Gave GLOBAL_AFFINITY a pre-processor'd name. * Fixed assumption that there are zero functional dependencies. * Bounds check walking of the MSC RIS. * More bounds checking in the main table walk. * Check for nonsense numbers of function dependencies. * Smattering of pr_debug() to help folk feeding line-noise to the parser. * Changed the comment flavour on the SPDX string. * Removed additional table check. * More comment wrangling. Changes since RFC: * Used DEFINE_RES_IRQ_NAMED() and friends macros. * Additional error handling. * Check for zero sized MSC. * Allow table revisions greater than 1. (no spec for revision 0!) * Use cleanup helpers to retrive ACPI tables, which allows some functions to be folded together. --- arch/arm64/Kconfig | 1 + drivers/acpi/arm64/Kconfig | 3 + drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/mpam.c | 361 ++++++++++++++++++++++++++++++++++++ drivers/acpi/tables.c | 2 +- include/linux/acpi.h | 12 ++ include/linux/arm_mpam.h | 48 +++++ 7 files changed, 427 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/arm64/mpam.c create mode 100644 include/linux/arm_mpam.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4be8a13505bf..6487c511bdc6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2062,6 +2062,7 @@ config ARM64_TLB_RANGE =20 config ARM64_MPAM bool "Enable support for MPAM" + select ACPI_MPAM if ACPI help Memory System Resource Partitioning and Monitoring (MPAM) is an optional extension to the Arm architecture that allows each diff --git a/drivers/acpi/arm64/Kconfig b/drivers/acpi/arm64/Kconfig index b3ed6212244c..f2fd79f22e7d 100644 --- a/drivers/acpi/arm64/Kconfig +++ b/drivers/acpi/arm64/Kconfig @@ -21,3 +21,6 @@ config ACPI_AGDI =20 config ACPI_APMT bool + +config ACPI_MPAM + bool diff --git a/drivers/acpi/arm64/Makefile b/drivers/acpi/arm64/Makefile index 05ecde9eaabe..9390b57cb564 100644 --- a/drivers/acpi/arm64/Makefile +++ b/drivers/acpi/arm64/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ACPI_APMT) +=3D apmt.o obj-$(CONFIG_ACPI_FFH) +=3D ffh.o obj-$(CONFIG_ACPI_GTDT) +=3D gtdt.o obj-$(CONFIG_ACPI_IORT) +=3D iort.o +obj-$(CONFIG_ACPI_MPAM) +=3D mpam.o obj-$(CONFIG_ACPI_PROCESSOR_IDLE) +=3D cpuidle.o obj-$(CONFIG_ARM_AMBA) +=3D amba.o obj-y +=3D dma.o init.o diff --git a/drivers/acpi/arm64/mpam.c b/drivers/acpi/arm64/mpam.c new file mode 100644 index 000000000000..fd9cfa143676 --- /dev/null +++ b/drivers/acpi/arm64/mpam.c @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. + +/* Parse the MPAM ACPI table feeding the discovered nodes into the driver = */ + +#define pr_fmt(fmt) "ACPI MPAM: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +/* + * Flags for acpi_table_mpam_msc.*_interrupt_flags. + * See 2.1.1 Interrupt Flags, Table 5, of DEN0065B_MPAM_ACPI_3.0-bet. + */ +#define ACPI_MPAM_MSC_IRQ_MODE_MASK BIT(0) +#define ACPI_MPAM_MSC_IRQ_TYPE_MASK GENMASK(2, 1) +#define ACPI_MPAM_MSC_IRQ_TYPE_WIRED 0 +#define ACPI_MPAM_MSC_IRQ_AFFINITY_PROCESSOR_CONTAINER BIT(3) +#define ACPI_MPAM_MSC_IRQ_AFFINITY_VALID BIT(4) + +static bool acpi_mpam_register_irq(struct platform_device *pdev, int intid, + u32 flags, int *irq, + u32 processor_container_uid) +{ + int sense; + + if (!intid) + return false; + + if (FIELD_GET(ACPI_MPAM_MSC_IRQ_TYPE_MASK, flags) !=3D + ACPI_MPAM_MSC_IRQ_TYPE_WIRED) + return false; + + sense =3D FIELD_GET(ACPI_MPAM_MSC_IRQ_MODE_MASK, flags); + + if (16 <=3D intid && intid < 32 && processor_container_uid !=3D GLOBAL_AF= FINITY) { + pr_err_once("Partitioned interrupts not supported\n"); + return false; + } + + *irq =3D acpi_register_gsi(&pdev->dev, intid, sense, ACPI_ACTIVE_HIGH); + if (*irq <=3D 0) { + pr_err_once("Failed to register interrupt 0x%x with ACPI\n", + intid); + return false; + } + + return true; +} + +static void acpi_mpam_parse_irqs(struct platform_device *pdev, + struct acpi_mpam_msc_node *tbl_msc, + struct resource *res, int *res_idx) +{ + u32 flags, aff; + int irq; + + flags =3D tbl_msc->overflow_interrupt_flags; + if (flags & ACPI_MPAM_MSC_IRQ_AFFINITY_VALID && + flags & ACPI_MPAM_MSC_IRQ_AFFINITY_PROCESSOR_CONTAINER) + aff =3D tbl_msc->overflow_interrupt_affinity; + else + aff =3D GLOBAL_AFFINITY; + if (acpi_mpam_register_irq(pdev, tbl_msc->overflow_interrupt, flags, &irq= , aff)) + res[(*res_idx)++] =3D DEFINE_RES_IRQ_NAMED(irq, "overflow"); + + flags =3D tbl_msc->error_interrupt_flags; + if (flags & ACPI_MPAM_MSC_IRQ_AFFINITY_VALID && + flags & ACPI_MPAM_MSC_IRQ_AFFINITY_PROCESSOR_CONTAINER) + aff =3D tbl_msc->error_interrupt_affinity; + else + aff =3D GLOBAL_AFFINITY; + if (acpi_mpam_register_irq(pdev, tbl_msc->error_interrupt, flags, &irq, a= ff)) + res[(*res_idx)++] =3D DEFINE_RES_IRQ_NAMED(irq, "error"); +} + +static int acpi_mpam_parse_resource(struct mpam_msc *msc, + struct acpi_mpam_resource_node *res) +{ + int level, nid; + u32 cache_id; + + switch (res->locator_type) { + case ACPI_MPAM_LOCATION_TYPE_PROCESSOR_CACHE: + cache_id =3D res->locator.cache_locator.cache_reference; + level =3D find_acpi_cache_level_from_id(cache_id); + if (level <=3D 0) { + pr_err_once("Bad level (%u) for cache with id %u\n", level, cache_id); + return -EINVAL; + } + return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_CACHE, + level, cache_id); + case ACPI_MPAM_LOCATION_TYPE_MEMORY: + nid =3D pxm_to_node(res->locator.memory_locator.proximity_domain); + if (nid =3D=3D NUMA_NO_NODE) + nid =3D 0; + return mpam_ris_create(msc, res->ris_index, MPAM_CLASS_MEMORY, + 255, nid); + default: + /* These get discovered later and treated as unknown */ + return 0; + } +} + +int acpi_mpam_parse_resources(struct mpam_msc *msc, + struct acpi_mpam_msc_node *tbl_msc) +{ + int i, err; + char *ptr, *table_end; + struct acpi_mpam_resource_node *resource; + + ptr =3D (char *)(tbl_msc + 1); + table_end =3D ptr + tbl_msc->length; + for (i =3D 0; i < tbl_msc->num_resource_nodes; i++) { + u64 max_deps, remaining_table; + + if (ptr + sizeof(*resource) > table_end) + return -EINVAL; + + resource =3D (struct acpi_mpam_resource_node *)ptr; + + remaining_table =3D table_end - ptr; + max_deps =3D remaining_table / sizeof(struct acpi_mpam_func_deps); + if (resource->num_functional_deps > max_deps) { + pr_debug("MSC has impossible number of functional dependencies\n"); + return -EINVAL; + } + + err =3D acpi_mpam_parse_resource(msc, resource); + if (err) + return err; + + ptr +=3D sizeof(*resource); + ptr +=3D resource->num_functional_deps * sizeof(struct acpi_mpam_func_de= ps); + } + + return 0; +} + +static bool __init parse_msc_pm_link(struct acpi_mpam_msc_node *tbl_msc, + struct platform_device *pdev, + u32 *acpi_id) +{ + char hid[sizeof(tbl_msc->hardware_id_linked_device) + 1]; + bool acpi_id_valid =3D false; + struct acpi_device *buddy; + char uid[11]; + int err; + + memset(&hid, 0, sizeof(hid)); + memcpy(hid, &tbl_msc->hardware_id_linked_device, + sizeof(tbl_msc->hardware_id_linked_device)); + + if (!strcmp(hid, ACPI_PROCESSOR_CONTAINER_HID)) { + *acpi_id =3D tbl_msc->instance_id_linked_device; + acpi_id_valid =3D true; + } + + err =3D snprintf(uid, sizeof(uid), "%u", + tbl_msc->instance_id_linked_device); + if (err >=3D sizeof(uid)) { + pr_debug("Failed to convert uid of device for power management."); + return acpi_id_valid; + } + + buddy =3D acpi_dev_get_first_match_dev(hid, uid, -1); + if (buddy) + device_link_add(&pdev->dev, &buddy->dev, DL_FLAG_STATELESS); + + return acpi_id_valid; +} + +static int decode_interface_type(struct acpi_mpam_msc_node *tbl_msc, + enum mpam_msc_iface *iface) +{ + switch (tbl_msc->interface_type) { + case 0: + *iface =3D MPAM_IFACE_MMIO; + return 0; + case 0xa: + *iface =3D MPAM_IFACE_PCC; + return 0; + default: + return -EINVAL; + } +} + +static int __init acpi_mpam_parse(void) +{ + struct acpi_table_header *table __free(acpi_table) =3D acpi_get_table_ret= (ACPI_SIG_MPAM, 0); + char *table_end, *table_offset =3D (char *)(table + 1); + struct property_entry props[4]; /* needs a sentinel */ + struct acpi_mpam_msc_node *tbl_msc; + int next_res, next_prop, err =3D 0; + struct acpi_device *companion; + struct platform_device *pdev; + enum mpam_msc_iface iface; + struct resource res[3]; + char uid[16]; + u32 acpi_id; + + if (acpi_disabled || !system_supports_mpam() || IS_ERR(table)) + return 0; + + if (table->revision < 1) + return 0; + + table_end =3D (char *)table + table->length; + + while (table_offset < table_end) { + tbl_msc =3D (struct acpi_mpam_msc_node *)table_offset; + table_offset +=3D tbl_msc->length; + + if (table_offset > table_end) { + pr_debug("MSC entry overlaps end of ACPI table\n"); + break; + } + + /* + * If any of the reserved fields are set, make no attempt to + * parse the MSC structure. This MSC will still be counted, + * meaning the MPAM driver can't probe against all MSC, and + * will never be enabled. There is no way to enable it safely, + * because we cannot determine safe system-wide partid and pmg + * ranges in this situation. + */ + if (tbl_msc->reserved || tbl_msc->reserved1 || tbl_msc->reserved2) { + pr_err_once("Unrecognised MSC, MPAM not usable\n"); + pr_debug("MSC.%u: reserved field set\n", tbl_msc->identifier); + continue; + } + + if (!tbl_msc->mmio_size) { + pr_debug("MSC.%u: marked as disabled\n", tbl_msc->identifier); + continue; + } + + if (decode_interface_type(tbl_msc, &iface)) { + pr_debug("MSC.%u: unknown interface type\n", tbl_msc->identifier); + continue; + } + + next_res =3D 0; + next_prop =3D 0; + memset(res, 0, sizeof(res)); + memset(props, 0, sizeof(props)); + + pdev =3D platform_device_alloc("mpam_msc", tbl_msc->identifier); + if (!pdev) { + err =3D -ENOMEM; + break; + } + + if (tbl_msc->length < sizeof(*tbl_msc)) { + err =3D -EINVAL; + break; + } + + /* Some power management is described in the namespace: */ + err =3D snprintf(uid, sizeof(uid), "%u", tbl_msc->identifier); + if (err > 0 && err < sizeof(uid)) { + companion =3D acpi_dev_get_first_match_dev("ARMHAA5C", uid, -1); + if (companion) + ACPI_COMPANION_SET(&pdev->dev, companion); + else + pr_debug("MSC.%u: missing namespace entry\n", tbl_msc->identifier); + } + + if (iface =3D=3D MPAM_IFACE_MMIO) { + res[next_res++] =3D DEFINE_RES_MEM_NAMED(tbl_msc->base_address, + tbl_msc->mmio_size, + "MPAM:MSC"); + } else if (iface =3D=3D MPAM_IFACE_PCC) { + props[next_prop++] =3D PROPERTY_ENTRY_U32("pcc-channel", + tbl_msc->base_address); + next_prop++; + } + + acpi_mpam_parse_irqs(pdev, tbl_msc, res, &next_res); + err =3D platform_device_add_resources(pdev, res, next_res); + if (err) + break; + + props[next_prop++] =3D PROPERTY_ENTRY_U32("arm,not-ready-us", + tbl_msc->max_nrdy_usec); + + /* + * The MSC's CPU affinity is described via its linked power + * management device, but only if it points at a Processor or + * Processor Container. + */ + if (parse_msc_pm_link(tbl_msc, pdev, &acpi_id)) { + props[next_prop++] =3D PROPERTY_ENTRY_U32("cpu_affinity", + acpi_id); + } + + err =3D device_create_managed_software_node(&pdev->dev, props, + NULL); + if (err) + break; + + /* Come back later if you want the RIS too */ + err =3D platform_device_add_data(pdev, tbl_msc, tbl_msc->length); + if (err) + break; + + err =3D platform_device_add(pdev); + if (err) + break; + } + + if (err) + platform_device_put(pdev); + + return err; +} + +int acpi_mpam_count_msc(void) +{ + struct acpi_table_header *table __free(acpi_table) =3D acpi_get_table_ret= (ACPI_SIG_MPAM, 0); + char *table_end, *table_offset =3D (char *)(table + 1); + struct acpi_mpam_msc_node *tbl_msc; + int count =3D 0; + + if (IS_ERR(table)) + return 0; + + if (table->revision < 1) + return 0; + + table_end =3D (char *)table + table->length; + + while (table_offset < table_end) { + tbl_msc =3D (struct acpi_mpam_msc_node *)table_offset; + if (!tbl_msc->mmio_size) + continue; + + if (tbl_msc->length < sizeof(*tbl_msc)) + return -EINVAL; + if (tbl_msc->length > table_end - table_offset) + return -EINVAL; + table_offset +=3D tbl_msc->length; + + count++; + } + + return count; +} + +/* + * Call after ACPI devices have been created, which happens behind acpi_sc= an_init() + * called from subsys_initcall(). PCC requires the mailbox driver, which is + * initialised from postcore_initcall(). + */ +subsys_initcall_sync(acpi_mpam_parse); diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index fa9bb8c8ce95..835e3795ede3 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -408,7 +408,7 @@ static const char table_sigs[][ACPI_NAMESEG_SIZE] __non= string_array __initconst ACPI_SIG_PSDT, ACPI_SIG_RSDT, ACPI_SIG_XSDT, ACPI_SIG_SSDT, ACPI_SIG_IORT, ACPI_SIG_NFIT, ACPI_SIG_HMAT, ACPI_SIG_PPTT, ACPI_SIG_NHLT, ACPI_SIG_AEST, ACPI_SIG_CEDT, ACPI_SIG_AGDI, - ACPI_SIG_NBFT }; + ACPI_SIG_NBFT, ACPI_SIG_MPAM }; =20 #define ACPI_HEADER_SIZE sizeof(struct acpi_table_header) =20 diff --git a/include/linux/acpi.h b/include/linux/acpi.h index c5fd92cda487..af449964426b 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -8,6 +8,7 @@ #ifndef _LINUX_ACPI_H #define _LINUX_ACPI_H =20 +#include #include #include /* for struct resource */ #include @@ -221,6 +222,17 @@ void acpi_reserve_initial_tables (void); void acpi_table_init_complete (void); int acpi_table_init (void); =20 +static inline struct acpi_table_header *acpi_get_table_ret(char *signature= , u32 instance) +{ + struct acpi_table_header *table; + int status =3D acpi_get_table(signature, instance, &table); + + if (ACPI_FAILURE(status)) + return ERR_PTR(-ENOENT); + return table; +} +DEFINE_FREE(acpi_table, struct acpi_table_header *, if (!IS_ERR(_T)) acpi_= put_table(_T)) + int acpi_table_parse(char *id, acpi_tbl_table_handler handler); int __init_or_acpilib acpi_table_parse_entries(char *id, unsigned long table_size, int entry_id, diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h new file mode 100644 index 000000000000..3d6c39c667c3 --- /dev/null +++ b/include/linux/arm_mpam.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2025 Arm Ltd. */ + +#ifndef __LINUX_ARM_MPAM_H +#define __LINUX_ARM_MPAM_H + +#include +#include + +#define GLOBAL_AFFINITY ~0 + +struct mpam_msc; + +enum mpam_msc_iface { + MPAM_IFACE_MMIO, /* a real MPAM MSC */ + MPAM_IFACE_PCC, /* a fake MPAM MSC */ +}; + +enum mpam_class_types { + MPAM_CLASS_CACHE, /* Well known caches, e.g. L2 */ + MPAM_CLASS_MEMORY, /* Main memory */ + MPAM_CLASS_UNKNOWN, /* Everything else, e.g. SMMU */ +}; + +#ifdef CONFIG_ACPI_MPAM +/* Parse the ACPI description of resources entries for this MSC. */ +int acpi_mpam_parse_resources(struct mpam_msc *msc, + struct acpi_mpam_msc_node *tbl_msc); + +int acpi_mpam_count_msc(void); +#else +static inline int acpi_mpam_parse_resources(struct mpam_msc *msc, + struct acpi_mpam_msc_node *tbl_msc) +{ + return -EINVAL; +} + +static inline int acpi_mpam_count_msc(void) { return -EINVAL; } +#endif + +static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, + enum mpam_class_types type, u8 class_id, + int component_id) +{ + return -EINVAL; +} + +#endif /* __LINUX_ARM_MPAM_H */ --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 51441306481; Wed, 10 Sep 2025 20:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 507BA22EA; Wed, 10 Sep 2025 13:43:56 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF0CA3F63F; Wed, 10 Sep 2025 13:43:59 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 07/29] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate Date: Wed, 10 Sep 2025 20:42:47 +0000 Message-Id: <20250910204309.20751-8-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Probing MPAM is convoluted. MSCs that are integrated with a CPU may only be accessible from those CPUs, and they may not be online. Touching the hardware early is pointless as MPAM can't be used until the system-wide common values for num_partid and num_pmg have been discovered. Start with driver probe/remove and mapping the MSC. CC: Carl Worth Signed-off-by: James Morse --- Changes since v1: * Avoid selecting driver on other architectrues. * Removed PCC support stub. * Use for_each_available_child_of_node_scoped() and of_property_read_reg() * Clarified a comment. * Stopped using mpam_num_msc as an id,a and made it atomic. * Size of -1 returned from cache_of_calculate_id() * Renamed some struct members. * Made a bunch of pr_err() dev_err_ocne(). * Used more cleanup magic. * Inlined a print message. * Fixed error propagation from mpam_dt_parse_resources(). * Moved cache accessibility checks earlier. Changes since RFC: * Check for status=3Dbroken DT devices. * Moved all the files around. * Made Kconfig symbols depend on EXPERT --- arch/arm64/Kconfig | 1 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/resctrl/Kconfig | 14 +++ drivers/resctrl/Makefile | 4 + drivers/resctrl/mpam_devices.c | 180 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 65 ++++++++++++ 7 files changed, 267 insertions(+) create mode 100644 drivers/resctrl/Kconfig create mode 100644 drivers/resctrl/Makefile create mode 100644 drivers/resctrl/mpam_devices.c create mode 100644 drivers/resctrl/mpam_internal.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 6487c511bdc6..93e563e1cce4 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2062,6 +2062,7 @@ config ARM64_TLB_RANGE =20 config ARM64_MPAM bool "Enable support for MPAM" + select ARM64_MPAM_DRIVER if EXPERT select ACPI_MPAM if ACPI help Memory System Resource Partitioning and Monitoring (MPAM) is an diff --git a/drivers/Kconfig b/drivers/Kconfig index 4915a63866b0..3054b50a2f4c 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -251,4 +251,6 @@ source "drivers/hte/Kconfig" =20 source "drivers/cdx/Kconfig" =20 +source "drivers/resctrl/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index b5749cf67044..f41cf4eddeba 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -194,5 +194,6 @@ obj-$(CONFIG_HTE) +=3D hte/ obj-$(CONFIG_DRM_ACCEL) +=3D accel/ obj-$(CONFIG_CDX_BUS) +=3D cdx/ obj-$(CONFIG_DPLL) +=3D dpll/ +obj-y +=3D resctrl/ =20 obj-$(CONFIG_S390) +=3D s390/ diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig new file mode 100644 index 000000000000..c30532a3a3a4 --- /dev/null +++ b/drivers/resctrl/Kconfig @@ -0,0 +1,14 @@ +menuconfig ARM64_MPAM_DRIVER + bool "MPAM driver" + depends on ARM64 && ARM64_MPAM && EXPERT + help + MPAM driver for System IP, e,g. caches and memory controllers. + +if ARM64_MPAM_DRIVER +config ARM64_MPAM_DRIVER_DEBUG + bool "Enable debug messages from the MPAM driver" + depends on ARM64_MPAM_DRIVER + help + Say yes here to enable debug messages from the MPAM driver. + +endif diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile new file mode 100644 index 000000000000..92b48fa20108 --- /dev/null +++ b/drivers/resctrl/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARM64_MPAM_DRIVER) +=3D mpam.o +mpam-y +=3D mpam_devices.o + +cflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) +=3D -DDEBUG diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c new file mode 100644 index 000000000000..efc4738e3b4d --- /dev/null +++ b/drivers/resctrl/mpam_devices.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2025 Arm Ltd. + +#define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mpam_internal.h" + +/* + * mpam_list_lock protects the SRCU lists when writing. Once the + * mpam_enabled key is enabled these lists are read-only, + * unless the error interrupt disables the driver. + */ +static DEFINE_MUTEX(mpam_list_lock); +static LIST_HEAD(mpam_all_msc); + +static struct srcu_struct mpam_srcu; + +/* + * Number of MSCs that have been probed. Once all MSC have been probed MPAM + * can be enabled. + */ +static atomic_t mpam_num_msc; + +/* + * An MSC can control traffic from a set of CPUs, but may only be accessib= le + * from a (hopefully wider) set of CPUs. The common reason for this is pow= er + * management. If all the CPUs in a cluster are in PSCI:CPU_SUSPEND, the + * corresponding cache may also be powered off. By making accesses from + * one of those CPUs, we ensure this isn't the case. + */ +static int update_msc_accessibility(struct mpam_msc *msc) +{ + u32 affinity_id; + int err; + + err =3D device_property_read_u32(&msc->pdev->dev, "cpu_affinity", + &affinity_id); + if (err) + cpumask_copy(&msc->accessibility, cpu_possible_mask); + else + acpi_pptt_get_cpus_from_container(affinity_id, + &msc->accessibility); + + return 0; + + return err; +} + +static int fw_num_msc; + +static void mpam_msc_drv_remove(struct platform_device *pdev) +{ + struct mpam_msc *msc =3D platform_get_drvdata(pdev); + + if (!msc) + return; + + mutex_lock(&mpam_list_lock); + platform_set_drvdata(pdev, NULL); + list_del_rcu(&msc->all_msc_list); + synchronize_srcu(&mpam_srcu); + mutex_unlock(&mpam_list_lock); +} + +static int mpam_msc_drv_probe(struct platform_device *pdev) +{ + int err; + struct mpam_msc *msc; + struct resource *msc_res; + struct device *dev =3D &pdev->dev; + void *plat_data =3D pdev->dev.platform_data; + + mutex_lock(&mpam_list_lock); + do { + msc =3D devm_kzalloc(&pdev->dev, sizeof(*msc), GFP_KERNEL); + if (!msc) { + err =3D -ENOMEM; + break; + } + + mutex_init(&msc->probe_lock); + mutex_init(&msc->part_sel_lock); + mutex_init(&msc->outer_mon_sel_lock); + raw_spin_lock_init(&msc->inner_mon_sel_lock); + msc->id =3D pdev->id; + msc->pdev =3D pdev; + INIT_LIST_HEAD_RCU(&msc->all_msc_list); + INIT_LIST_HEAD_RCU(&msc->ris); + + err =3D update_msc_accessibility(msc); + if (err) + break; + if (cpumask_empty(&msc->accessibility)) { + dev_err_once(dev, "MSC is not accessible from any CPU!"); + err =3D -EINVAL; + break; + } + + if (device_property_read_u32(&pdev->dev, "pcc-channel", + &msc->pcc_subspace_id)) + msc->iface =3D MPAM_IFACE_MMIO; + else + msc->iface =3D MPAM_IFACE_PCC; + + if (msc->iface =3D=3D MPAM_IFACE_MMIO) { + void __iomem *io; + + io =3D devm_platform_get_and_ioremap_resource(pdev, 0, + &msc_res); + if (IS_ERR(io)) { + dev_err_once(dev, "Failed to map MSC base address\n"); + err =3D PTR_ERR(io); + break; + } + msc->mapped_hwpage_sz =3D msc_res->end - msc_res->start; + msc->mapped_hwpage =3D io; + } + + list_add_rcu(&msc->all_msc_list, &mpam_all_msc); + platform_set_drvdata(pdev, msc); + } while (0); + mutex_unlock(&mpam_list_lock); + + if (!err) { + /* Create RIS entries described by firmware */ + err =3D acpi_mpam_parse_resources(msc, plat_data); + } + + if (err && msc) + mpam_msc_drv_remove(pdev); + + if (!err && atomic_add_return(1, &mpam_num_msc) =3D=3D fw_num_msc) + pr_info("Discovered all MSC\n"); + + return err; +} + +static struct platform_driver mpam_msc_driver =3D { + .driver =3D { + .name =3D "mpam_msc", + }, + .probe =3D mpam_msc_drv_probe, + .remove =3D mpam_msc_drv_remove, +}; + +static int __init mpam_msc_driver_init(void) +{ + if (!system_supports_mpam()) + return -EOPNOTSUPP; + + init_srcu_struct(&mpam_srcu); + + fw_num_msc =3D acpi_mpam_count_msc(); + + if (fw_num_msc <=3D 0) { + pr_err("No MSC devices found in firmware\n"); + return -EINVAL; + } + + return platform_driver_register(&mpam_msc_driver); +} +subsys_initcall(mpam_msc_driver_init); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h new file mode 100644 index 000000000000..7c63d590fc98 --- /dev/null +++ b/drivers/resctrl/mpam_internal.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (C) 2025 Arm Ltd. + +#ifndef MPAM_INTERNAL_H +#define MPAM_INTERNAL_H + +#include +#include +#include +#include +#include +#include +#include + +struct mpam_msc { + /* member of mpam_all_msc */ + struct list_head all_msc_list; + + int id; + struct platform_device *pdev; + + /* Not modified after mpam_is_enabled() becomes true */ + enum mpam_msc_iface iface; + u32 pcc_subspace_id; + struct mbox_client pcc_cl; + struct pcc_mbox_chan *pcc_chan; + u32 nrdy_usec; + cpumask_t accessibility; + + /* + * probe_lock is only taken during discovery. After discovery these + * properties become read-only and the lists are protected by SRCU. + */ + struct mutex probe_lock; + unsigned long ris_idxs; + u32 ris_max; + + /* mpam_msc_ris of this component */ + struct list_head ris; + + /* + * part_sel_lock protects access to the MSC hardware registers that are + * affected by MPAMCFG_PART_SEL. (including the ID registers that vary + * by RIS). + * If needed, take msc->probe_lock first. + */ + struct mutex part_sel_lock; + + /* + * mon_sel_lock protects access to the MSC hardware registers that are + * affected by MPAMCFG_MON_SEL. + * If needed, take msc->probe_lock first. + */ + struct mutex outer_mon_sel_lock; + raw_spinlock_t inner_mon_sel_lock; + unsigned long inner_mon_sel_flags; + + void __iomem *mapped_hwpage; + size_t mapped_hwpage_sz; +}; + +int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, + cpumask_t *affinity); + +#endif /* MPAM_INTERNAL_H */ --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 570CB3081C4; Wed, 10 Sep 2025 20:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537052; cv=none; b=t1Dz9Cy7XA1xIgC4KGXSXpmBJAd2oQNMfocBCmiY0sS9hpFcfcDTYfKvGqzf1pQgfoTyRZ6sHtsJOhgMx5Dt1N8kOkuIEtRPg14162fhXjnbVwAmelAPBl6ELYXemaRa6uoWW5JKH3aJgZt8XfDc9iJF4akuMygqujJB+Rn67Kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537052; c=relaxed/simple; bh=0QjO27crpiS2IQzvSc2rgqC+HgK1p98kFjGTFvY2VTk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=A6RPUN19lSkRpRQe6JzmEkJjp2Gn36faikQ5SCiaSW4yfzQO0A36KLUgQiH1YPc06zAC8KV+zWzN26waFgnjDAY8R+mWlYUkhHeExxMIBEjcE2kztJX1vhOKmaeF33o17fNeFZMvBiqFQjKkMKY1kOGxr2FpakbX+wUrwQZB4EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8025622EA; Wed, 10 Sep 2025 13:44:01 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 18DAC3F63F; Wed, 10 Sep 2025 13:44:04 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 08/29] arm_mpam: Add the class and component structures for firmware described ris Date: Wed, 10 Sep 2025 20:42:48 +0000 Message-Id: <20250910204309.20751-9-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" An MSC is a container of resources, each identified by their RIS index. Some RIS are described by firmware to provide their position in the system. Others are discovered when the driver probes the hardware. To configure a resource it needs to be found by its class, e.g. 'L2'. There are two kinds of grouping, a class is a set of components, which are visible to user-space as there are likely to be multiple instances of the L2 cache. (e.g. one per cluster or package) Add support for creating and destroying structures to allow a hierarchy of resources to be created. CC: Ben Horgan Signed-off-by: James Morse --- Changes since v1: * Fixed a comp/vmsc typo. * Removed duplicate description from the commit message. * Moved parenthesis in the add_to_garbage() macro. * Check for out of range ris_idx when creating ris. * Removed GFP as probe_lock is no longer a spin lock. * Removed alloc flag as ended up searching the lists itself. * Added a comment about affinity masks not overlapping. Changes since RFC: * removed a pr_err() debug message that crept in. --- drivers/resctrl/mpam_devices.c | 406 +++++++++++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 90 +++++++ include/linux/arm_mpam.h | 8 +- 3 files changed, 493 insertions(+), 11 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index efc4738e3b4d..c7f4981b3545 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -18,7 +18,6 @@ #include #include #include -#include #include =20 #include "mpam_internal.h" @@ -31,7 +30,7 @@ static DEFINE_MUTEX(mpam_list_lock); static LIST_HEAD(mpam_all_msc); =20 -static struct srcu_struct mpam_srcu; +struct srcu_struct mpam_srcu; =20 /* * Number of MSCs that have been probed. Once all MSC have been probed MPAM @@ -39,6 +38,402 @@ static struct srcu_struct mpam_srcu; */ static atomic_t mpam_num_msc; =20 +/* + * An MSC is a physical container for controls and monitors, each identifi= ed by + * their RIS index. These share a base-address, interrupts and some MMIO + * registers. A vMSC is a virtual container for RIS in an MSC that control= or + * monitor the same thing. Members of a vMSC are all RIS in the same MSC, = but + * not all RIS in an MSC share a vMSC. + * Components are a group of vMSC that control or monitor the same thing b= ut + * are from different MSC, so have different base-address, interrupts etc. + * Classes are the set components of the same type. + * + * The features of a vMSC is the union of the RIS it contains. + * The features of a Class and Component are the common subset of the vMSC + * they contain. + * + * e.g. The system cache may have bandwidth controls on multiple interface= s, + * for regulating traffic from devices independently of traffic from CPUs. + * If these are two RIS in one MSC, they will be treated as controlling + * different things, and will not share a vMSC/component/class. + * + * e.g. The L2 may have one MSC and two RIS, one for cache-controls another + * for bandwidth. These two RIS are members of the same vMSC. + * + * e.g. The set of RIS that make up the L2 are grouped as a component. The= se + * are sometimes termed slices. They should be configured the same, as if = there + * were only one. + * + * e.g. The SoC probably has more than one L2, each attached to a distinct= set + * of CPUs. All the L2 components are grouped as a class. + * + * When creating an MSC, struct mpam_msc is added to the all mpam_all_msc = list, + * then linked via struct mpam_ris to a vmsc, component and class. + * The same MSC may exist under different class->component->vmsc paths, bu= t the + * RIS index will be unique. + */ +LIST_HEAD(mpam_classes); + +/* List of all objects that can be free()d after synchronise_srcu() */ +static LLIST_HEAD(mpam_garbage); + +#define init_garbage(x) init_llist_node(&(x)->garbage.llist) + +static struct mpam_vmsc * +mpam_vmsc_alloc(struct mpam_component *comp, struct mpam_msc *msc) +{ + struct mpam_vmsc *vmsc; + + lockdep_assert_held(&mpam_list_lock); + + vmsc =3D kzalloc(sizeof(*vmsc), GFP_KERNEL); + if (!vmsc) + return ERR_PTR(-ENOMEM); + init_garbage(vmsc); + + INIT_LIST_HEAD_RCU(&vmsc->ris); + INIT_LIST_HEAD_RCU(&vmsc->comp_list); + vmsc->comp =3D comp; + vmsc->msc =3D msc; + + list_add_rcu(&vmsc->comp_list, &comp->vmsc); + + return vmsc; +} + +static struct mpam_vmsc *mpam_vmsc_get(struct mpam_component *comp, + struct mpam_msc *msc) +{ + struct mpam_vmsc *vmsc; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(vmsc, &comp->vmsc, comp_list) { + if (vmsc->msc->id =3D=3D msc->id) + return vmsc; + } + + return mpam_vmsc_alloc(comp, msc); +} + +static struct mpam_component * +mpam_component_alloc(struct mpam_class *class, int id) +{ + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + comp =3D kzalloc(sizeof(*comp), GFP_KERNEL); + if (!comp) + return ERR_PTR(-ENOMEM); + init_garbage(comp); + + comp->comp_id =3D id; + INIT_LIST_HEAD_RCU(&comp->vmsc); + /* affinity is updated when ris are added */ + INIT_LIST_HEAD_RCU(&comp->class_list); + comp->class =3D class; + + list_add_rcu(&comp->class_list, &class->components); + + return comp; +} + +static struct mpam_component * +mpam_component_get(struct mpam_class *class, int id) +{ + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(comp, &class->components, class_list) { + if (comp->comp_id =3D=3D id) + return comp; + } + + return mpam_component_alloc(class, id); +} + +static struct mpam_class * +mpam_class_alloc(u8 level_idx, enum mpam_class_types type) +{ + struct mpam_class *class; + + lockdep_assert_held(&mpam_list_lock); + + class =3D kzalloc(sizeof(*class), GFP_KERNEL); + if (!class) + return ERR_PTR(-ENOMEM); + init_garbage(class); + + INIT_LIST_HEAD_RCU(&class->components); + /* affinity is updated when ris are added */ + class->level =3D level_idx; + class->type =3D type; + INIT_LIST_HEAD_RCU(&class->classes_list); + + list_add_rcu(&class->classes_list, &mpam_classes); + + return class; +} + +static struct mpam_class * +mpam_class_get(u8 level_idx, enum mpam_class_types type) +{ + bool found =3D false; + struct mpam_class *class; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(class, &mpam_classes, classes_list) { + if (class->type =3D=3D type && class->level =3D=3D level_idx) { + found =3D true; + break; + } + } + + if (found) + return class; + + return mpam_class_alloc(level_idx, type); +} + +#define add_to_garbage(x) \ +do { \ + __typeof__(x) _x =3D (x); \ + _x->garbage.to_free =3D _x; \ + llist_add(&_x->garbage.llist, &mpam_garbage); \ +} while (0) + +static void mpam_class_destroy(struct mpam_class *class) +{ + lockdep_assert_held(&mpam_list_lock); + + list_del_rcu(&class->classes_list); + add_to_garbage(class); +} + +static void mpam_comp_destroy(struct mpam_component *comp) +{ + struct mpam_class *class =3D comp->class; + + lockdep_assert_held(&mpam_list_lock); + + list_del_rcu(&comp->class_list); + add_to_garbage(comp); + + if (list_empty(&class->components)) + mpam_class_destroy(class); +} + +static void mpam_vmsc_destroy(struct mpam_vmsc *vmsc) +{ + struct mpam_component *comp =3D vmsc->comp; + + lockdep_assert_held(&mpam_list_lock); + + list_del_rcu(&vmsc->comp_list); + add_to_garbage(vmsc); + + if (list_empty(&comp->vmsc)) + mpam_comp_destroy(comp); +} + +static void mpam_ris_destroy(struct mpam_msc_ris *ris) +{ + struct mpam_vmsc *vmsc =3D ris->vmsc; + struct mpam_msc *msc =3D vmsc->msc; + struct platform_device *pdev =3D msc->pdev; + struct mpam_component *comp =3D vmsc->comp; + struct mpam_class *class =3D comp->class; + + lockdep_assert_held(&mpam_list_lock); + + /* + * It is assumed affinities don't overlap. If they do the class becomes + * unusable immediately. + */ + cpumask_andnot(&comp->affinity, &comp->affinity, &ris->affinity); + cpumask_andnot(&class->affinity, &class->affinity, &ris->affinity); + clear_bit(ris->ris_idx, &msc->ris_idxs); + list_del_rcu(&ris->vmsc_list); + list_del_rcu(&ris->msc_list); + add_to_garbage(ris); + ris->garbage.pdev =3D pdev; + + if (list_empty(&vmsc->ris)) + mpam_vmsc_destroy(vmsc); +} + +/* + * There are two ways of reaching a struct mpam_msc_ris. Via the + * class->component->vmsc->ris, or via the msc. + * When destroying the msc, the other side needs unlinking and cleaning up= too. + */ +static void mpam_msc_destroy(struct mpam_msc *msc) +{ + struct platform_device *pdev =3D msc->pdev; + struct mpam_msc_ris *ris, *tmp; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry_safe(ris, tmp, &msc->ris, msc_list) + mpam_ris_destroy(ris); + + list_del_rcu(&msc->all_msc_list); + platform_set_drvdata(pdev, NULL); + + add_to_garbage(msc); + msc->garbage.pdev =3D pdev; +} + +static void mpam_free_garbage(void) +{ + struct mpam_garbage *iter, *tmp; + struct llist_node *to_free =3D llist_del_all(&mpam_garbage); + + if (!to_free) + return; + + synchronize_srcu(&mpam_srcu); + + llist_for_each_entry_safe(iter, tmp, to_free, llist) { + if (iter->pdev) + devm_kfree(&iter->pdev->dev, iter->to_free); + else + kfree(iter->to_free); + } +} + +/* + * The cacheinfo structures are only populated when CPUs are online. + */ +int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, + cpumask_t *affinity) +{ + return acpi_pptt_get_cpumask_from_cache_id(cache_id, affinity); +} + +/* + * cpumask_of_node() only knows about online CPUs. This can't tell us whet= her + * a class is represented on all possible CPUs. + */ +static void get_cpumask_from_node_id(u32 node_id, cpumask_t *affinity) +{ + int cpu; + + for_each_possible_cpu(cpu) { + if (node_id =3D=3D cpu_to_node(cpu)) + cpumask_set_cpu(cpu, affinity); + } +} + +static int mpam_ris_get_affinity(struct mpam_msc *msc, cpumask_t *affinity, + enum mpam_class_types type, + struct mpam_class *class, + struct mpam_component *comp) +{ + int err; + + switch (type) { + case MPAM_CLASS_CACHE: + err =3D mpam_get_cpumask_from_cache_id(comp->comp_id, class->level, + affinity); + if (err) + return err; + + if (cpumask_empty(affinity)) + pr_warn_once("%s no CPUs associated with cache node", + dev_name(&msc->pdev->dev)); + + break; + case MPAM_CLASS_MEMORY: + get_cpumask_from_node_id(comp->comp_id, affinity); + /* affinity may be empty for CPU-less memory nodes */ + break; + case MPAM_CLASS_UNKNOWN: + return 0; + } + + cpumask_and(affinity, affinity, &msc->accessibility); + + return 0; +} + +static int mpam_ris_create_locked(struct mpam_msc *msc, u8 ris_idx, + enum mpam_class_types type, u8 class_id, + int component_id) +{ + int err; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + struct mpam_class *class; + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + if (ris_idx > MPAM_MSC_MAX_NUM_RIS) + return -EINVAL; + + if (test_and_set_bit(ris_idx, &msc->ris_idxs)) + return -EBUSY; + + ris =3D devm_kzalloc(&msc->pdev->dev, sizeof(*ris), GFP_KERNEL); + if (!ris) + return -ENOMEM; + init_garbage(ris); + + class =3D mpam_class_get(class_id, type); + if (IS_ERR(class)) + return PTR_ERR(class); + + comp =3D mpam_component_get(class, component_id); + if (IS_ERR(comp)) { + if (list_empty(&class->components)) + mpam_class_destroy(class); + return PTR_ERR(comp); + } + + vmsc =3D mpam_vmsc_get(comp, msc); + if (IS_ERR(vmsc)) { + if (list_empty(&comp->vmsc)) + mpam_comp_destroy(comp); + return PTR_ERR(vmsc); + } + + err =3D mpam_ris_get_affinity(msc, &ris->affinity, type, class, comp); + if (err) { + if (list_empty(&vmsc->ris)) + mpam_vmsc_destroy(vmsc); + return err; + } + + ris->ris_idx =3D ris_idx; + INIT_LIST_HEAD_RCU(&ris->vmsc_list); + ris->vmsc =3D vmsc; + + cpumask_or(&comp->affinity, &comp->affinity, &ris->affinity); + cpumask_or(&class->affinity, &class->affinity, &ris->affinity); + list_add_rcu(&ris->vmsc_list, &vmsc->ris); + + return 0; +} + +int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, + enum mpam_class_types type, u8 class_id, int component_id) +{ + int err; + + mutex_lock(&mpam_list_lock); + err =3D mpam_ris_create_locked(msc, ris_idx, type, class_id, + component_id); + mutex_unlock(&mpam_list_lock); + if (err) + mpam_free_garbage(); + + return err; +} + /* * An MSC can control traffic from a set of CPUs, but may only be accessib= le * from a (hopefully wider) set of CPUs. The common reason for this is pow= er @@ -74,10 +469,10 @@ static void mpam_msc_drv_remove(struct platform_device= *pdev) return; =20 mutex_lock(&mpam_list_lock); - platform_set_drvdata(pdev, NULL); - list_del_rcu(&msc->all_msc_list); - synchronize_srcu(&mpam_srcu); + mpam_msc_destroy(msc); mutex_unlock(&mpam_list_lock); + + mpam_free_garbage(); } =20 static int mpam_msc_drv_probe(struct platform_device *pdev) @@ -95,6 +490,7 @@ static int mpam_msc_drv_probe(struct platform_device *pd= ev) err =3D -ENOMEM; break; } + init_garbage(msc); =20 mutex_init(&msc->probe_lock); mutex_init(&msc->part_sel_lock); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 7c63d590fc98..02e9576ece6b 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -7,10 +7,29 @@ #include #include #include +#include #include #include #include #include +#include + +#define MPAM_MSC_MAX_NUM_RIS 16 + +/* + * Structures protected by SRCU may not be freed for a surprising amount of + * time (especially if perf is running). To ensure the MPAM error interrup= t can + * tear down all the structures, build a list of objects that can be gargb= age + * collected once synchronize_srcu() has returned. + * If pdev is non-NULL, use devm_kfree(). + */ +struct mpam_garbage { + /* member of mpam_garbage */ + struct llist_node llist; + + void *to_free; + struct platform_device *pdev; +}; =20 struct mpam_msc { /* member of mpam_all_msc */ @@ -57,8 +76,79 @@ struct mpam_msc { =20 void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; + + struct mpam_garbage garbage; }; =20 +struct mpam_class { + /* mpam_components in this class */ + struct list_head components; + + cpumask_t affinity; + + u8 level; + enum mpam_class_types type; + + /* member of mpam_classes */ + struct list_head classes_list; + + struct mpam_garbage garbage; +}; + +struct mpam_component { + u32 comp_id; + + /* mpam_vmsc in this component */ + struct list_head vmsc; + + cpumask_t affinity; + + /* member of mpam_class:components */ + struct list_head class_list; + + /* parent: */ + struct mpam_class *class; + + struct mpam_garbage garbage; +}; + +struct mpam_vmsc { + /* member of mpam_component:vmsc_list */ + struct list_head comp_list; + + /* mpam_msc_ris in this vmsc */ + struct list_head ris; + + /* All RIS in this vMSC are members of this MSC */ + struct mpam_msc *msc; + + /* parent: */ + struct mpam_component *comp; + + struct mpam_garbage garbage; +}; + +struct mpam_msc_ris { + u8 ris_idx; + + cpumask_t affinity; + + /* member of mpam_vmsc:ris */ + struct list_head vmsc_list; + + /* member of mpam_msc:ris */ + struct list_head msc_list; + + /* parent: */ + struct mpam_vmsc *vmsc; + + struct mpam_garbage garbage; +}; + +/* List of all classes - protected by srcu*/ +extern struct srcu_struct mpam_srcu; +extern struct list_head mpam_classes; + int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 3d6c39c667c3..3206f5ddc147 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -38,11 +38,7 @@ static inline int acpi_mpam_parse_resources(struct mpam_= msc *msc, static inline int acpi_mpam_count_msc(void) { return -EINVAL; } #endif =20 -static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, - enum mpam_class_types type, u8 class_id, - int component_id) -{ - return -EINVAL; -} +int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, + enum mpam_class_types type, u8 class_id, int component_id); =20 #endif /* __LINUX_ARM_MPAM_H */ --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5AE063090E1; Wed, 10 Sep 2025 20:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537057; cv=none; b=CZ99f70PmqVgU9em0tOx6h7oQJ1rwsBHsai6f+/82mV+v8v2TYQL0qpIRQ84OR/4FBQ19zxrIWdVsgANPvRGCnXO4imGwo2Cu2pDQqmWROpkrc5TTqU/IDv9D63G25xgBOueUMl3Qk/VpZzh54fBRVHVGUJGfJynk1ECBlTBGcY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537057; c=relaxed/simple; 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Wed, 10 Sep 2025 13:44:10 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 09/29] arm_mpam: Add MPAM MSC register layout definitions Date: Wed, 10 Sep 2025 20:42:49 +0000 Message-Id: <20250910204309.20751-10-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Memory Partitioning and Monitoring (MPAM) has memory mapped devices (MSCs) with an identity/configuration page. Add the definitions for these registers as offset within the page(s). Link: https://developer.arm.com/documentation/ihi0099/latest/ Signed-off-by: James Morse Reviewed-by: Ben Horgan --- Changes since v1: * Whitespace. * Added constants for CASSOC and XCL. * Merged FLT/CTL defines. * Fixed MSMON_CFG_CSU_CTL_TYPE_CSU definition. Changes since RFC: * Renamed MSMON_CFG_MBWU_CTL_TYPE_CSU as MSMON_CFG_CSU_CTL_TYPE_CSU * Whitepsace churn. * Cite a more recent document. * Removed some stale feature, fixed some names etc. --- drivers/resctrl/mpam_internal.h | 267 ++++++++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 02e9576ece6b..109f03df46c2 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -152,4 +152,271 @@ extern struct list_head mpam_classes; int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 +/* + * MPAM MSCs have the following register layout. See: + * Arm Memory System Resource Partitioning and Monitoring (MPAM) System + * Component Specification. + * https://developer.arm.com/documentation/ihi0099/latest/ + */ +#define MPAM_ARCHITECTURE_V1 0x10 + +/* Memory mapped control pages: */ +/* ID Register offsets in the memory mapped page */ +#define MPAMF_IDR 0x0000 /* features id register */ +#define MPAMF_MSMON_IDR 0x0080 /* performance monitoring features */ +#define MPAMF_IMPL_IDR 0x0028 /* imp-def partitioning */ +#define MPAMF_CPOR_IDR 0x0030 /* cache-portion partitioning */ +#define MPAMF_CCAP_IDR 0x0038 /* cache-capacity partitioning */ +#define MPAMF_MBW_IDR 0x0040 /* mem-bw partitioning */ +#define MPAMF_PRI_IDR 0x0048 /* priority partitioning */ +#define MPAMF_CSUMON_IDR 0x0088 /* cache-usage monitor */ +#define MPAMF_MBWUMON_IDR 0x0090 /* mem-bw usage monitor */ +#define MPAMF_PARTID_NRW_IDR 0x0050 /* partid-narrowing */ +#define MPAMF_IIDR 0x0018 /* implementer id register */ +#define MPAMF_AIDR 0x0020 /* architectural id register */ + +/* Configuration and Status Register offsets in the memory mapped page */ +#define MPAMCFG_PART_SEL 0x0100 /* partid to configure: */ +#define MPAMCFG_CPBM 0x1000 /* cache-portion config */ +#define MPAMCFG_CMAX 0x0108 /* cache-capacity config */ +#define MPAMCFG_CMIN 0x0110 /* cache-capacity config */ +#define MPAMCFG_CASSOC 0x0118 /* cache-associativity config */ +#define MPAMCFG_MBW_MIN 0x0200 /* min mem-bw config */ +#define MPAMCFG_MBW_MAX 0x0208 /* max mem-bw config */ +#define MPAMCFG_MBW_WINWD 0x0220 /* mem-bw accounting window config */ +#define MPAMCFG_MBW_PBM 0x2000 /* mem-bw portion bitmap config */ +#define MPAMCFG_PRI 0x0400 /* priority partitioning config */ +#define MPAMCFG_MBW_PROP 0x0500 /* mem-bw stride config */ +#define MPAMCFG_INTPARTID 0x0600 /* partid-narrowing config */ + +#define MSMON_CFG_MON_SEL 0x0800 /* monitor selector */ +#define MSMON_CFG_CSU_FLT 0x0810 /* cache-usage monitor filter */ +#define MSMON_CFG_CSU_CTL 0x0818 /* cache-usage monitor config */ +#define MSMON_CFG_MBWU_FLT 0x0820 /* mem-bw monitor filter */ +#define MSMON_CFG_MBWU_CTL 0x0828 /* mem-bw monitor config */ +#define MSMON_CSU 0x0840 /* current cache-usage */ +#define MSMON_CSU_CAPTURE 0x0848 /* last cache-usage value captured */ +#define MSMON_MBWU 0x0860 /* current mem-bw usage value */ +#define MSMON_MBWU_CAPTURE 0x0868 /* last mem-bw value captured */ +#define MSMON_MBWU_L 0x0880 /* current long mem-bw usage value */ +#define MSMON_MBWU_CAPTURE_L 0x0890 /* last long mem-bw value captured */ +#define MSMON_CAPT_EVNT 0x0808 /* signal a capture event */ +#define MPAMF_ESR 0x00F8 /* error status register */ +#define MPAMF_ECR 0x00F0 /* error control register */ + +/* MPAMF_IDR - MPAM features ID register */ +#define MPAMF_IDR_PARTID_MAX GENMASK(15, 0) +#define MPAMF_IDR_PMG_MAX GENMASK(23, 16) +#define MPAMF_IDR_HAS_CCAP_PART BIT(24) +#define MPAMF_IDR_HAS_CPOR_PART BIT(25) +#define MPAMF_IDR_HAS_MBW_PART BIT(26) +#define MPAMF_IDR_HAS_PRI_PART BIT(27) +#define MPAMF_IDR_EXT BIT(28) +#define MPAMF_IDR_HAS_IMPL_IDR BIT(29) +#define MPAMF_IDR_HAS_MSMON BIT(30) +#define MPAMF_IDR_HAS_PARTID_NRW BIT(31) +#define MPAMF_IDR_HAS_RIS BIT(32) +#define MPAMF_IDR_HAS_EXTD_ESR BIT(38) +#define MPAMF_IDR_HAS_ESR BIT(39) +#define MPAMF_IDR_RIS_MAX GENMASK(59, 56) + +/* MPAMF_MSMON_IDR - MPAM performance monitoring ID register */ +#define MPAMF_MSMON_IDR_MSMON_CSU BIT(16) +#define MPAMF_MSMON_IDR_MSMON_MBWU BIT(17) +#define MPAMF_MSMON_IDR_HAS_LOCAL_CAPT_EVNT BIT(31) + +/* MPAMF_CPOR_IDR - MPAM features cache portion partitioning ID register */ +#define MPAMF_CPOR_IDR_CPBM_WD GENMASK(15, 0) + +/* MPAMF_CCAP_IDR - MPAM features cache capacity partitioning ID register = */ +#define MPAMF_CCAP_IDR_CMAX_WD GENMASK(5, 0) +#define MPAMF_CCAP_IDR_CASSOC_WD GENMASK(12, 8) +#define MPAMF_CCAP_IDR_HAS_CASSOC BIT(28) +#define MPAMF_CCAP_IDR_HAS_CMIN BIT(29) +#define MPAMF_CCAP_IDR_NO_CMAX BIT(30) +#define MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM BIT(31) + +/* MPAMF_MBW_IDR - MPAM features memory bandwidth partitioning ID register= */ +#define MPAMF_MBW_IDR_BWA_WD GENMASK(5, 0) +#define MPAMF_MBW_IDR_HAS_MIN BIT(10) +#define MPAMF_MBW_IDR_HAS_MAX BIT(11) +#define MPAMF_MBW_IDR_HAS_PBM BIT(12) +#define MPAMF_MBW_IDR_HAS_PROP BIT(13) +#define MPAMF_MBW_IDR_WINDWR BIT(14) +#define MPAMF_MBW_IDR_BWPBM_WD GENMASK(28, 16) + +/* MPAMF_PRI_IDR - MPAM features priority partitioning ID register */ +#define MPAMF_PRI_IDR_HAS_INTPRI BIT(0) +#define MPAMF_PRI_IDR_INTPRI_0_IS_LOW BIT(1) +#define MPAMF_PRI_IDR_INTPRI_WD GENMASK(9, 4) +#define MPAMF_PRI_IDR_HAS_DSPRI BIT(16) +#define MPAMF_PRI_IDR_DSPRI_0_IS_LOW BIT(17) +#define MPAMF_PRI_IDR_DSPRI_WD GENMASK(25, 20) + +/* MPAMF_CSUMON_IDR - MPAM cache storage usage monitor ID register */ +#define MPAMF_CSUMON_IDR_NUM_MON GENMASK(15, 0) +#define MPAMF_CSUMON_IDR_HAS_OFLOW_CAPT BIT(24) +#define MPAMF_CSUMON_IDR_HAS_CEVNT_OFLW BIT(25) +#define MPAMF_CSUMON_IDR_HAS_OFSR BIT(26) +#define MPAMF_CSUMON_IDR_HAS_OFLOW_LNKG BIT(27) +#define MPAMF_CSUMON_IDR_HAS_XCL BIT(29) +#define MPAMF_CSUMON_IDR_CSU_RO BIT(30) +#define MPAMF_CSUMON_IDR_HAS_CAPTURE BIT(31) + +/* MPAMF_MBWUMON_IDR - MPAM memory bandwidth usage monitor ID register */ +#define MPAMF_MBWUMON_IDR_NUM_MON GENMASK(15, 0) +#define MPAMF_MBWUMON_IDR_HAS_RWBW BIT(28) +#define MPAMF_MBWUMON_IDR_LWD BIT(29) +#define MPAMF_MBWUMON_IDR_HAS_LONG BIT(30) +#define MPAMF_MBWUMON_IDR_HAS_CAPTURE BIT(31) + +/* MPAMF_PARTID_NRW_IDR - MPAM PARTID narrowing ID register */ +#define MPAMF_PARTID_NRW_IDR_INTPARTID_MAX GENMASK(15, 0) + +/* MPAMF_IIDR - MPAM implementation ID register */ +#define MPAMF_IIDR_PRODUCTID GENMASK(31, 20) +#define MPAMF_IIDR_PRODUCTID_SHIFT 20 +#define MPAMF_IIDR_VARIANT GENMASK(19, 16) +#define MPAMF_IIDR_VARIANT_SHIFT 16 +#define MPAMF_IIDR_REVISON GENMASK(15, 12) +#define MPAMF_IIDR_REVISON_SHIFT 12 +#define MPAMF_IIDR_IMPLEMENTER GENMASK(11, 0) +#define MPAMF_IIDR_IMPLEMENTER_SHIFT 0 + +/* MPAMF_AIDR - MPAM architecture ID register */ +#define MPAMF_AIDR_ARCH_MAJOR_REV GENMASK(7, 4) +#define MPAMF_AIDR_ARCH_MINOR_REV GENMASK(3, 0) + +/* MPAMCFG_PART_SEL - MPAM partition configuration selection register */ +#define MPAMCFG_PART_SEL_PARTID_SEL GENMASK(15, 0) +#define MPAMCFG_PART_SEL_INTERNAL BIT(16) +#define MPAMCFG_PART_SEL_RIS GENMASK(27, 24) + +/* MPAMCFG_CASSOC - MPAM cache maximum associativity partition configurati= on register */ +#define MPAMCFG_CASSOC_CASSOC GENMASK(15, 0) + +/* MPAMCFG_CMAX - MPAM cache capacity configuration register */ +#define MPAMCFG_CMAX_SOFTLIM BIT(31) +#define MPAMCFG_CMAX_CMAX GENMASK(15, 0) + +/* MPAMCFG_CMIN - MPAM cache capacity configuration register */ +#define MPAMCFG_CMIN_CMIN GENMASK(15, 0) + +/* + * MPAMCFG_MBW_MIN - MPAM memory minimum bandwidth partitioning configurat= ion + * register + */ +#define MPAMCFG_MBW_MIN_MIN GENMASK(15, 0) + +/* + * MPAMCFG_MBW_MAX - MPAM memory maximum bandwidth partitioning configurat= ion + * register + */ +#define MPAMCFG_MBW_MAX_MAX GENMASK(15, 0) +#define MPAMCFG_MBW_MAX_HARDLIM BIT(31) + +/* + * MPAMCFG_MBW_WINWD - MPAM memory bandwidth partitioning window width + * register + */ +#define MPAMCFG_MBW_WINWD_US_FRAC GENMASK(7, 0) +#define MPAMCFG_MBW_WINWD_US_INT GENMASK(23, 8) + +/* MPAMCFG_PRI - MPAM priority partitioning configuration register */ +#define MPAMCFG_PRI_INTPRI GENMASK(15, 0) +#define MPAMCFG_PRI_DSPRI GENMASK(31, 16) + +/* + * MPAMCFG_MBW_PROP - Memory bandwidth proportional stride partitioning + * configuration register + */ +#define MPAMCFG_MBW_PROP_STRIDEM1 GENMASK(15, 0) +#define MPAMCFG_MBW_PROP_EN BIT(31) + +/* + * MPAMCFG_INTPARTID - MPAM internal partition narrowing configuration reg= ister + */ +#define MPAMCFG_INTPARTID_INTPARTID GENMASK(15, 0) +#define MPAMCFG_INTPARTID_INTERNAL BIT(16) + +/* MSMON_CFG_MON_SEL - Memory system performance monitor selection registe= r */ +#define MSMON_CFG_MON_SEL_MON_SEL GENMASK(15, 0) +#define MSMON_CFG_MON_SEL_RIS GENMASK(27, 24) + +/* MPAMF_ESR - MPAM Error Status Register */ +#define MPAMF_ESR_PARTID_MON GENMASK(15, 0) +#define MPAMF_ESR_PMG GENMASK(23, 16) +#define MPAMF_ESR_ERRCODE GENMASK(27, 24) +#define MPAMF_ESR_OVRWR BIT(31) +#define MPAMF_ESR_RIS GENMASK(35, 32) + +/* MPAMF_ECR - MPAM Error Control Register */ +#define MPAMF_ECR_INTEN BIT(0) + +/* Error conditions in accessing memory mapped registers */ +#define MPAM_ERRCODE_NONE 0 +#define MPAM_ERRCODE_PARTID_SEL_RANGE 1 +#define MPAM_ERRCODE_REQ_PARTID_RANGE 2 +#define MPAM_ERRCODE_MSMONCFG_ID_RANGE 3 +#define MPAM_ERRCODE_REQ_PMG_RANGE 4 +#define MPAM_ERRCODE_MONITOR_RANGE 5 +#define MPAM_ERRCODE_INTPARTID_RANGE 6 +#define MPAM_ERRCODE_UNEXPECTED_INTERNAL 7 + +/* + * MSMON_CFG_CSU_CTL - Memory system performance monitor configure cache s= torage + * usage monitor control register + * MSMON_CFG_MBWU_CTL - Memory system performance monitor configure memory + * bandwidth usage monitor control register + */ +#define MSMON_CFG_x_CTL_TYPE GENMASK(7, 0) +#define MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L BIT(15) +#define MSMON_CFG_x_CTL_MATCH_PARTID BIT(16) +#define MSMON_CFG_x_CTL_MATCH_PMG BIT(17) +#define MSMON_CFG_x_CTL_SCLEN BIT(19) +#define MSMON_CFG_x_CTL_SUBTYPE GENMASK(22, 20) +#define MSMON_CFG_x_CTL_OFLOW_FRZ BIT(24) +#define MSMON_CFG_x_CTL_OFLOW_INTR BIT(25) +#define MSMON_CFG_x_CTL_OFLOW_STATUS BIT(26) +#define MSMON_CFG_x_CTL_CAPT_RESET BIT(27) +#define MSMON_CFG_x_CTL_CAPT_EVNT GENMASK(30, 28) +#define MSMON_CFG_x_CTL_EN BIT(31) + +#define MSMON_CFG_MBWU_CTL_TYPE_MBWU 0x42 +#define MSMON_CFG_CSU_CTL_TYPE_CSU 0x43 + +/* + * MSMON_CFG_CSU_FLT - Memory system performance monitor configure cache = storage + * usage monitor filter register + * MSMON_CFG_MBWU_FLT - Memory system performance monitor configure memory + * bandwidth usage monitor filter register + */ +#define MSMON_CFG_x_FLT_PARTID GENMASK(15, 0) +#define MSMON_CFG_x_FLT_PMG GENMASK(23, 16) + +#define MSMON_CFG_MBWU_FLT_RWBW GENMASK(31, 30) +#define MSMON_CFG_CSU_FLT_XCL BIT(31) + +/* + * MSMON_CSU - Memory system performance monitor cache storage usage monit= or + * register + * MSMON_CSU_CAPTURE - Memory system performance monitor cache storage us= age + * capture register + * MSMON_MBWU - Memory system performance monitor memory bandwidth usage + * monitor register + * MSMON_MBWU_CAPTURE - Memory system performance monitor memory bandwidth= usage + * capture register + */ +#define MSMON___VALUE GENMASK(30, 0) +#define MSMON___NRDY BIT(31) +#define MSMON___NRDY_L BIT(63) +#define MSMON___L_VALUE GENMASK(43, 0) +#define MSMON___LWD_VALUE GENMASK(62, 0) + +/* + * MSMON_CAPT_EVNT - Memory system performance monitoring capture event + * generation register + */ +#define MSMON_CAPT_EVNT_NOW BIT(0) + #endif /* MPAM_INTERNAL_H */ --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8FBE130AACC; Wed, 10 Sep 2025 20:44:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537062; cv=none; b=iLdVue9J5MirBmSRLcYq55A7T+vbqagk2AfInyNp8ZQO9MqCQYq1sCpLLYTdWCRbVcGHbTq+DTbUhXHMg17F4ob884Y9iil89X5ENKxSPEwwGp1Mh9eXO497s0Xxm4ntJdr5HnkFWStn5veQIprfTOD/fI5pEpZw4pEf01iPia0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537062; c=relaxed/simple; bh=1DaYWnI5xlh9G7vTYH9KyIFwMZBmSH2lxHYTiQgI/1s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q0+LdisxWeu5HKDahBvjWRqsuL6wnP1JmoM5NUwE15o0qh+dMDulTMMeTfJcDkRCt6e7V8s0TZLobrbckhsufw7oqPqA7cTCotvmf4gXp9XBaBzXqSyLFKMmx2AEEzCAlZdoOlvzqX2aAuwQB5korHJRpPt7qMKtIKLz7B7358Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C6201153B; Wed, 10 Sep 2025 13:44:11 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6019A3F63F; Wed, 10 Sep 2025 13:44:15 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Lecopzer Chen Subject: [PATCH v2 10/29] arm_mpam: Add cpuhp callbacks to probe MSC hardware Date: Wed, 10 Sep 2025 20:42:50 +0000 Message-Id: <20250910204309.20751-11-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Because an MSC can only by accessed from the CPUs in its cpu-affinity set we need to be running on one of those CPUs to probe the MSC hardware. Do this work in the cpuhp callback. Probing the hardware will only happen before MPAM is enabled, walk all the MSCs and probe those we can reach that haven't already been probed as each CPU's online call is made. This adds the low-level MSC register accessors. Once all MSCs reported by the firmware have been probed from a CPU in their respective cpu-affinity set, the probe-time cpuhp callbacks are replaced. The replacement callbacks will ultimately need to handle save/restore of the runtime MSC state across power transitions, but for now there is nothing to do in them: so do nothing. The architecture's context switch code will be enabled by a static-key, this can be set by mpam_enable(), but must be done from process context, not a cpuhp callback because both take the cpuhp lock. Whenever a new MSC has been probed, the mpam_enable() work is scheduled to test if all the MSCs have been probed. If probing fails, mpam_disable() is scheduled to unregister the cpuhp callbacks and free memory. CC: Lecopzer Chen Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- Changes since v1: * Removed register bounds check. If the firmware tables are wrong the resulting translation fault should be enough to debug this. * Removed '&' in front of a function pointer. * Pulled mpam_disable() into this patch. * Disable mpam when probing fails to avoid extra work on broken platforms. * Added mpam_disbale_reason as there are now two non-debug reasons for this to happen. --- drivers/resctrl/mpam_devices.c | 173 +++++++++++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 5 + 2 files changed, 177 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index c7f4981b3545..c265376d936b 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -4,6 +4,7 @@ #define pr_fmt(fmt) "%s:%s: " fmt, KBUILD_MODNAME, __func__ =20 #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include =20 #include "mpam_internal.h" =20 @@ -38,6 +40,22 @@ struct srcu_struct mpam_srcu; */ static atomic_t mpam_num_msc; =20 +static int mpam_cpuhp_state; +static DEFINE_MUTEX(mpam_cpuhp_state_lock); + +/* + * mpam is enabled once all devices have been probed from CPU online callb= acks, + * scheduled via this work_struct. If access to an MSC depends on a CPU th= at + * was not brought online at boot, this can happen surprisingly late. + */ +static DECLARE_WORK(mpam_enable_work, &mpam_enable); + +/* + * All mpam error interrupts indicate a software bug. On receipt, disable = the + * driver. + */ +static DECLARE_WORK(mpam_broken_work, &mpam_disable); + /* * An MSC is a physical container for controls and monitors, each identifi= ed by * their RIS index. These share a base-address, interrupts and some MMIO @@ -77,6 +95,24 @@ LIST_HEAD(mpam_classes); /* List of all objects that can be free()d after synchronise_srcu() */ static LLIST_HEAD(mpam_garbage); =20 +/* When mpam is disabled, the printed reason to aid debugging */ +static char *mpam_disable_reason; + +static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg) +{ + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); + + return readl_relaxed(msc->mapped_hwpage + reg); +} + +static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg) +{ + lockdep_assert_held_once(&msc->part_sel_lock); + return __mpam_read_reg(msc, reg); +} + +#define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc,= MPAMF_##reg) + #define init_garbage(x) init_llist_node(&(x)->garbage.llist) =20 static struct mpam_vmsc * @@ -434,6 +470,86 @@ int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, return err; } =20 +static int mpam_msc_hw_probe(struct mpam_msc *msc) +{ + u64 idr; + struct device *dev =3D &msc->pdev->dev; + + lockdep_assert_held(&msc->probe_lock); + + idr =3D __mpam_read_reg(msc, MPAMF_AIDR); + if ((idr & MPAMF_AIDR_ARCH_MAJOR_REV) !=3D MPAM_ARCHITECTURE_V1) { + dev_err_once(dev, "MSC does not match MPAM architecture v1.x\n"); + return -EIO; + } + + msc->probed =3D true; + + return 0; +} + +static int mpam_cpu_online(unsigned int cpu) +{ + return 0; +} + +/* Before mpam is enabled, try to probe new MSC */ +static int mpam_discovery_cpu_online(unsigned int cpu) +{ + int err =3D 0; + struct mpam_msc *msc; + bool new_device_probed =3D false; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + if (!cpumask_test_cpu(cpu, &msc->accessibility)) + continue; + + mutex_lock(&msc->probe_lock); + if (!msc->probed) + err =3D mpam_msc_hw_probe(msc); + mutex_unlock(&msc->probe_lock); + + if (!err) + new_device_probed =3D true; + else + break; + } + + if (new_device_probed && !err) + schedule_work(&mpam_enable_work); + if (err) { + mpam_disable_reason =3D "error during probing"; + schedule_work(&mpam_broken_work); + } + + return err; +} + +static int mpam_cpu_offline(unsigned int cpu) +{ + return 0; +} + +static void mpam_register_cpuhp_callbacks(int (*online)(unsigned int onlin= e), + int (*offline)(unsigned int offline)) +{ + mutex_lock(&mpam_cpuhp_state_lock); + if (mpam_cpuhp_state) { + cpuhp_remove_state(mpam_cpuhp_state); + mpam_cpuhp_state =3D 0; + } + + mpam_cpuhp_state =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mpam:online", + online, offline); + if (mpam_cpuhp_state <=3D 0) { + pr_err("Failed to register cpuhp callbacks"); + mpam_cpuhp_state =3D 0; + } + mutex_unlock(&mpam_cpuhp_state_lock); +} + /* * An MSC can control traffic from a set of CPUs, but may only be accessib= le * from a (hopefully wider) set of CPUs. The common reason for this is pow= er @@ -544,7 +660,7 @@ static int mpam_msc_drv_probe(struct platform_device *p= dev) mpam_msc_drv_remove(pdev); =20 if (!err && atomic_add_return(1, &mpam_num_msc) =3D=3D fw_num_msc) - pr_info("Discovered all MSC\n"); + mpam_register_cpuhp_callbacks(mpam_discovery_cpu_online, NULL); =20 return err; } @@ -557,6 +673,61 @@ static struct platform_driver mpam_msc_driver =3D { .remove =3D mpam_msc_drv_remove, }; =20 +static void mpam_enable_once(void) +{ + mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline); + + pr_info("MPAM enabled\n"); +} + +void mpam_disable(struct work_struct *ignored) +{ + struct mpam_msc *msc, *tmp; + + mutex_lock(&mpam_cpuhp_state_lock); + if (mpam_cpuhp_state) { + cpuhp_remove_state(mpam_cpuhp_state); + mpam_cpuhp_state =3D 0; + } + mutex_unlock(&mpam_cpuhp_state_lock); + + mutex_lock(&mpam_list_lock); + list_for_each_entry_safe(msc, tmp, &mpam_all_msc, all_msc_list) + mpam_msc_destroy(msc); + mutex_unlock(&mpam_list_lock); + mpam_free_garbage(); + + pr_err_once("MPAM disabled due to %s\n", mpam_disable_reason); +} + +/* + * Enable mpam once all devices have been probed. + * Scheduled by mpam_discovery_cpu_online() once all devices have been cre= ated. + * Also scheduled when new devices are probed when new CPUs come online. + */ +void mpam_enable(struct work_struct *work) +{ + static atomic_t once; + struct mpam_msc *msc; + bool all_devices_probed =3D true; + + /* Have we probed all the hw devices? */ + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + mutex_lock(&msc->probe_lock); + if (!msc->probed) + all_devices_probed =3D false; + mutex_unlock(&msc->probe_lock); + + if (!all_devices_probed) + break; + } + + if (all_devices_probed && !atomic_fetch_inc(&once)) + mpam_enable_once(); +} + static int __init mpam_msc_driver_init(void) { if (!system_supports_mpam()) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 109f03df46c2..d4f3febc7a50 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -51,6 +51,7 @@ struct mpam_msc { * properties become read-only and the lists are protected by SRCU. */ struct mutex probe_lock; + bool probed; unsigned long ris_idxs; u32 ris_max; =20 @@ -149,6 +150,10 @@ struct mpam_msc_ris { extern struct srcu_struct mpam_srcu; extern struct list_head mpam_classes; =20 +/* Scheduled work callback to enable mpam once all MSC have been probed */ +void mpam_enable(struct work_struct *work); +void mpam_disable(struct work_struct *work); + int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B809630DEB7; Wed, 10 Sep 2025 20:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537067; cv=none; b=h/OF9kvHtSp0EVgGy8Lrrlu08QG0j7vClb9VIh6tzwGiRqKZrEiLYbUgzx0g2HvwNkrySCtETDQJrrOANKG7NAjrNyO4qx6EJfmWDtgwsjJTiCIJLdA1rm75QoNl98GsB8LMG1vgffDn2nam0mmac/jeG/ZQanYquWgurnCLC4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537067; c=relaxed/simple; bh=7navXBxHShagp690G26Rw3K20P7L6z3qPg9baxtqTos=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sKpxn8MS5J40Zr9CquthLmrZ1M4/gEaY4JGeKGoBwsCyplAeCycrLWU4R3mP501qiYHWddN0vd0yI3OuamZ6HT+oj6o3/VFucNRfi2vhFEYTP3pJaUZ+sXu/py+k/g9wHM8Y80/Y9DFicXioRmBao0TyK3+9CvLqpCe9+TgAF8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B994F153B; Wed, 10 Sep 2025 13:44:16 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 71C0D3F63F; Wed, 10 Sep 2025 13:44:20 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 11/29] arm_mpam: Probe hardware to find the supported partid/pmg values Date: Wed, 10 Sep 2025 20:42:51 +0000 Message-Id: <20250910204309.20751-12-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CPUs can generate traffic with a range of PARTID and PMG values, but each MSC may also have its own maximum size for these fields. Before MPAM can be used, the driver needs to probe each RIS on each MSC, to find the system-wide smallest value that can be used. The limits from requestors (e.g. CPUs) also need taking into account. While doing this, RIS entries that firmware didn't describe are created under MPAM_CLASS_UNKNOWN. While we're here, implement the mpam_register_requestor() call for the arch code to register the CPU limits. Future callers of this will tell us about the SMMU and ITS. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- Changes since v1: * Change to lock ordering now that the list-lock mutex isn't held from the cpuhp call. * Removed irq-unmaksed assert in requestor register. * Changed captialisation in print message. --- drivers/resctrl/mpam_devices.c | 150 +++++++++++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 6 ++ include/linux/arm_mpam.h | 14 +++ 3 files changed, 169 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index c265376d936b..24dc81c15ec8 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,15 @@ static atomic_t mpam_num_msc; static int mpam_cpuhp_state; static DEFINE_MUTEX(mpam_cpuhp_state_lock); =20 +/* + * The smallest common values for any CPU or MSC in the system. + * Generating traffic outside this range will result in screaming interrup= ts. + */ +u16 mpam_partid_max; +u8 mpam_pmg_max; +static bool partid_max_init, partid_max_published; +static DEFINE_SPINLOCK(partid_max_lock); + /* * mpam is enabled once all devices have been probed from CPU online callb= acks, * scheduled via this work_struct. If access to an MSC depends on a CPU th= at @@ -113,6 +123,72 @@ static inline u32 _mpam_read_partsel_reg(struct mpam_m= sc *msc, u16 reg) =20 #define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc,= MPAMF_##reg) =20 +static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val) +{ + WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz); + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); + + writel_relaxed(val, msc->mapped_hwpage + reg); +} + +static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, = u32 val) +{ + lockdep_assert_held_once(&msc->part_sel_lock); + __mpam_write_reg(msc, reg, val); +} +#define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc= , MPAMCFG_##reg, val) + +static u64 mpam_msc_read_idr(struct mpam_msc *msc) +{ + u64 idr_high =3D 0, idr_low; + + lockdep_assert_held(&msc->part_sel_lock); + + idr_low =3D mpam_read_partsel_reg(msc, IDR); + if (FIELD_GET(MPAMF_IDR_EXT, idr_low)) + idr_high =3D mpam_read_partsel_reg(msc, IDR + 4); + + return (idr_high << 32) | idr_low; +} + +static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc) +{ + lockdep_assert_held(&msc->part_sel_lock); + + mpam_write_partsel_reg(msc, PART_SEL, partsel); +} + +static void __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc) +{ + u32 partsel =3D FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) | + FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, partid); + + __mpam_part_sel_raw(partsel, msc); +} + +int mpam_register_requestor(u16 partid_max, u8 pmg_max) +{ + int err =3D 0; + + spin_lock(&partid_max_lock); + if (!partid_max_init) { + mpam_partid_max =3D partid_max; + mpam_pmg_max =3D pmg_max; + partid_max_init =3D true; + } else if (!partid_max_published) { + mpam_partid_max =3D min(mpam_partid_max, partid_max); + mpam_pmg_max =3D min(mpam_pmg_max, pmg_max); + } else { + /* New requestors can't lower the values */ + if (partid_max < mpam_partid_max || pmg_max < mpam_pmg_max) + err =3D -EBUSY; + } + spin_unlock(&partid_max_lock); + + return err; +} +EXPORT_SYMBOL(mpam_register_requestor); + #define init_garbage(x) init_llist_node(&(x)->garbage.llist) =20 static struct mpam_vmsc * @@ -451,6 +527,7 @@ static int mpam_ris_create_locked(struct mpam_msc *msc,= u8 ris_idx, cpumask_or(&comp->affinity, &comp->affinity, &ris->affinity); cpumask_or(&class->affinity, &class->affinity, &ris->affinity); list_add_rcu(&ris->vmsc_list, &vmsc->ris); + list_add_rcu(&ris->msc_list, &msc->ris); =20 return 0; } @@ -470,9 +547,37 @@ int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, return err; } =20 +static struct mpam_msc_ris *mpam_get_or_create_ris(struct mpam_msc *msc, + u8 ris_idx) +{ + int err; + struct mpam_msc_ris *ris, *found =3D ERR_PTR(-ENOENT); + + lockdep_assert_held(&mpam_list_lock); + + if (!test_bit(ris_idx, &msc->ris_idxs)) { + err =3D mpam_ris_create_locked(msc, ris_idx, MPAM_CLASS_UNKNOWN, + 0, 0); + if (err) + return ERR_PTR(err); + } + + list_for_each_entry(ris, &msc->ris, msc_list) { + if (ris->ris_idx =3D=3D ris_idx) { + found =3D ris; + break; + } + } + + return found; +} + static int mpam_msc_hw_probe(struct mpam_msc *msc) { u64 idr; + u16 partid_max; + u8 ris_idx, pmg_max; + struct mpam_msc_ris *ris; struct device *dev =3D &msc->pdev->dev; =20 lockdep_assert_held(&msc->probe_lock); @@ -483,6 +588,39 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) return -EIO; } =20 + /* Grab an IDR value to find out how many RIS there are */ + mutex_lock(&msc->part_sel_lock); + idr =3D mpam_msc_read_idr(msc); + mutex_unlock(&msc->part_sel_lock); + msc->ris_max =3D FIELD_GET(MPAMF_IDR_RIS_MAX, idr); + + /* Use these values so partid/pmg always starts with a valid value */ + msc->partid_max =3D FIELD_GET(MPAMF_IDR_PARTID_MAX, idr); + msc->pmg_max =3D FIELD_GET(MPAMF_IDR_PMG_MAX, idr); + + for (ris_idx =3D 0; ris_idx <=3D msc->ris_max; ris_idx++) { + mutex_lock(&msc->part_sel_lock); + __mpam_part_sel(ris_idx, 0, msc); + idr =3D mpam_msc_read_idr(msc); + mutex_unlock(&msc->part_sel_lock); + + partid_max =3D FIELD_GET(MPAMF_IDR_PARTID_MAX, idr); + pmg_max =3D FIELD_GET(MPAMF_IDR_PMG_MAX, idr); + msc->partid_max =3D min(msc->partid_max, partid_max); + msc->pmg_max =3D min(msc->pmg_max, pmg_max); + + mutex_lock(&mpam_list_lock); + ris =3D mpam_get_or_create_ris(msc, ris_idx); + mutex_unlock(&mpam_list_lock); + if (IS_ERR(ris)) + return PTR_ERR(ris); + } + + spin_lock(&partid_max_lock); + mpam_partid_max =3D min(mpam_partid_max, msc->partid_max); + mpam_pmg_max =3D min(mpam_pmg_max, msc->pmg_max); + spin_unlock(&partid_max_lock); + msc->probed =3D true; =20 return 0; @@ -675,9 +813,18 @@ static struct platform_driver mpam_msc_driver =3D { =20 static void mpam_enable_once(void) { + /* + * Once the cpuhp callbacks have been changed, mpam_partid_max can no + * longer change. + */ + spin_lock(&partid_max_lock); + partid_max_published =3D true; + spin_unlock(&partid_max_lock); + mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline); =20 - pr_info("MPAM enabled\n"); + printk(KERN_INFO "MPAM enabled with %u PARTIDs and %u PMGs\n", + mpam_partid_max + 1, mpam_pmg_max + 1); } =20 void mpam_disable(struct work_struct *ignored) @@ -744,4 +891,5 @@ static int __init mpam_msc_driver_init(void) =20 return platform_driver_register(&mpam_msc_driver); } +/* Must occur after arm64_mpam_register_cpus() from arch_initcall() */ subsys_initcall(mpam_msc_driver_init); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index d4f3febc7a50..828ce93c95d5 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -52,6 +52,8 @@ struct mpam_msc { */ struct mutex probe_lock; bool probed; + u16 partid_max; + u8 pmg_max; unsigned long ris_idxs; u32 ris_max; =20 @@ -150,6 +152,10 @@ struct mpam_msc_ris { extern struct srcu_struct mpam_srcu; extern struct list_head mpam_classes; =20 +/* System wide partid/pmg values */ +extern u16 mpam_partid_max; +extern u8 mpam_pmg_max; + /* Scheduled work callback to enable mpam once all MSC have been probed */ void mpam_enable(struct work_struct *work); void mpam_disable(struct work_struct *work); diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index 3206f5ddc147..cb6e6cfbea0b 100644 --- a/include/linux/arm_mpam.h +++ b/include/linux/arm_mpam.h @@ -41,4 +41,18 @@ static inline int acpi_mpam_count_msc(void) { return -EI= NVAL; } int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, enum mpam_class_types type, u8 class_id, int component_id); =20 +/** + * mpam_register_requestor() - Register a requestor with the MPAM driver + * @partid_max: The maximum PARTID value the requestor can generate. + * @pmg_max: The maximum PMG value the requestor can generate. + * + * Registers a requestor with the MPAM driver to ensure the chosen system-= wide + * minimum PARTID and PMG values will allow the requestors features to be = used. + * + * Returns an error if the registration is too late, and a larger PARTID/P= MG + * value has been advertised to user-space. In this case the requestor sho= uld + * not use its MPAM features. Returns 0 on success. + */ +int mpam_register_requestor(u16 partid_max, u8 pmg_max); + #endif /* __LINUX_ARM_MPAM_H */ --=20 2.39.5 From nobody Thu Oct 2 21:40:06 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A789C30F552; Wed, 10 Sep 2025 20:44:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537072; cv=none; b=O36NFY2WSubSOkJJTjxMKeX7kMbQZj9KHDpviNKFHzA7emlJpJ6A2oCzu2PG3W4RElKnceizgr8pgt+8JfnGoqST2u5q+piQgxcneVSlapqD+usd79CKe2Q+DyJLr0Lws4t2CQKTBIdrIj7kwsLwTIp/vgZvdUQc3TLlE+5z0Lk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537072; c=relaxed/simple; bh=WOR048v1sYnJX4tzPXnoQkCKMQ7y6xK61e6TsW9XslA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UU4MYm8C5e1ZRc9VhI8XKtPrz6ym74UC9v3cZMW31R7GBDjL/NmJ/uu0nRgPQ//J6Wxka+lemlI0eoZsjVnLDRDV+n1XJjZrZc1U4hiXR7H6tGQ9ePDzsdRqG8VEY5EJLTUmte2O2oxtaXBymoY3Vt3hwYOf3p8LqiuVHRMnTH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1D991C0A; Wed, 10 Sep 2025 13:44:21 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7BB463F63F; Wed, 10 Sep 2025 13:44:25 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 12/29] arm_mpam: Add helpers for managing the locking around the mon_sel registers Date: Wed, 10 Sep 2025 20:42:52 +0000 Message-Id: <20250910204309.20751-13-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MSC MON_SEL register needs to be accessed from hardirq for the overflow interrupt, and when taking an IPI to access these registers on platforms where MSC are not accesible from every CPU. This makes an irqsave spinlock the obvious lock to protect these registers. On systems with SCMI mailboxes it must be able to sleep, meaning a mutex must be used. The SCMI platforms can't support an overflow interrupt. Clearly these two can't exist for one MSC at the same time. Add helpers for the MON_SEL locking. The outer lock must be taken in a pre-emptible context before the inner lock can be taken. On systems with SCMI mailboxes where the MON_SEL accesses must sleep - the inner lock will fail to be 'taken' if the caller is unable to sleep. This will allow callers to fail without having to explicitly check the interface type of each MSC. Signed-off-by: James Morse --- Change since v1: * Made accesses to outer_lock_held READ_ONCE() for torn values in the fail= ure case. --- drivers/resctrl/mpam_devices.c | 3 +-- drivers/resctrl/mpam_internal.h | 37 +++++++++++++++++++++++++++++---- 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 24dc81c15ec8..a26b012452e2 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -748,8 +748,7 @@ static int mpam_msc_drv_probe(struct platform_device *p= dev) =20 mutex_init(&msc->probe_lock); mutex_init(&msc->part_sel_lock); - mutex_init(&msc->outer_mon_sel_lock); - raw_spin_lock_init(&msc->inner_mon_sel_lock); + mpam_mon_sel_lock_init(msc); msc->id =3D pdev->id; msc->pdev =3D pdev; INIT_LIST_HEAD_RCU(&msc->all_msc_list); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 828ce93c95d5..4cc44d4e21c4 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -70,12 +70,17 @@ struct mpam_msc { =20 /* * mon_sel_lock protects access to the MSC hardware registers that are - * affected by MPAMCFG_MON_SEL. + * affected by MPAMCFG_MON_SEL, and the mbwu_state. + * Access to mon_sel is needed from both process and interrupt contexts, + * but is complicated by firmware-backed platforms that can't make any + * access unless they can sleep. + * Always use the mpam_mon_sel_lock() helpers. + * Accessed to mon_sel need to be able to fail if they occur in the wrong + * context. * If needed, take msc->probe_lock first. */ - struct mutex outer_mon_sel_lock; - raw_spinlock_t inner_mon_sel_lock; - unsigned long inner_mon_sel_flags; + raw_spinlock_t _mon_sel_lock; + unsigned long _mon_sel_flags; =20 void __iomem *mapped_hwpage; size_t mapped_hwpage_sz; @@ -83,6 +88,30 @@ struct mpam_msc { struct mpam_garbage garbage; }; =20 +/* Returning false here means accesses to mon_sel must fail and report an = error. */ +static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc) +{ + WARN_ON_ONCE(msc->iface !=3D MPAM_IFACE_MMIO); + + raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags); + return true; +} + +static inline void mpam_mon_sel_unlock(struct mpam_msc *msc) +{ + raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags); +} + +static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc) +{ + lockdep_assert_held_once(&msc->_mon_sel_lock); +} + +static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc) +{ + raw_spin_lock_init(&msc->_mon_sel_lock); +} + struct mpam_class { /* mpam_components in this class */ struct list_head components; --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CE8E831282F; Wed, 10 Sep 2025 20:44:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537077; cv=none; b=s1JIpduVXYEis0DdBCx76jYicHflX5mpRP8V1kML9o96zBiBXlSyQdeAQx26SkwVjpEyp9T+OuUdQkmxjdpo1WinfH5Wc/IyNXhsiHP4BaI7Xg6FjnfEPh/kVme5yJRM2qnfSZmZq8YaQ15nXsgXxcHE7XZk/SAV31+xtO+HUAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537077; c=relaxed/simple; bh=2pm1X/5a38nCseAqRXion9V7YZpSRZoQaCaZ8H7HxUQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nhMjSLg1XEFo6phHEvQJ8W5biZNib2jocQLeg/DdwuMjgihOvsKV0VSc+IPc7xspFkoiqCcAtBTd+h5OQgqDatloNVnbXyEa7quhsJa6J2ogOwIBHlhzOJ/g+ffkWSWuSwZDdIwgBSRDNtWdfNsURFDoy+Co6t+p20TAnjTnCOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DBB431D34; Wed, 10 Sep 2025 13:44:26 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 73E003F63F; Wed, 10 Sep 2025 13:44:30 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Dave Martin Subject: [PATCH v2 13/29] arm_mpam: Probe the hardware features resctrl supports Date: Wed, 10 Sep 2025 20:42:53 +0000 Message-Id: <20250910204309.20751-14-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Expand the probing support with the control and monitor types we can use with resctrl. CC: Dave Martin Signed-off-by: James Morse Reviewed-by: Jonathan Cameron --- Changes since v1: * added an underscore to a variable name. Changes since RFC: * Made mpam_ris_hw_probe_hw_nrdy() more in C. * Added static assert on features bitmap size. --- drivers/resctrl/mpam_devices.c | 151 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 53 +++++++++++ 2 files changed, 204 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index a26b012452e2..ba8e8839cdc4 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -138,6 +138,20 @@ static inline void _mpam_write_partsel_reg(struct mpam= _msc *msc, u16 reg, u32 va } #define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc= , MPAMCFG_##reg, val) =20 +static inline u32 _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg) +{ + mpam_mon_sel_lock_held(msc); + return __mpam_read_reg(msc, reg); +} +#define mpam_read_monsel_reg(msc, reg) _mpam_read_monsel_reg(msc, MSMON_##= reg) + +static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u= 32 val) +{ + mpam_mon_sel_lock_held(msc); + __mpam_write_reg(msc, reg, val); +} +#define mpam_write_monsel_reg(msc, reg, val) _mpam_write_monsel_reg(msc,= MSMON_##reg, val) + static u64 mpam_msc_read_idr(struct mpam_msc *msc) { u64 idr_high =3D 0, idr_low; @@ -572,6 +586,136 @@ static struct mpam_msc_ris *mpam_get_or_create_ris(st= ruct mpam_msc *msc, return found; } =20 +/* + * IHI009A.a has this nugget: "If a monitor does not support automatic beh= aviour + * of NRDY, software can use this bit for any purpose" - so hardware might= not + * implement this - but it isn't RES0. + * + * Try and see what values stick in this bit. If we can write either value, + * its probably not implemented by hardware. + */ +static bool _mpam_ris_hw_probe_hw_nrdy(struct mpam_msc_ris * ris, u32 mon_= reg) +{ + u32 now; + u64 mon_sel; + bool can_set, can_clear; + struct mpam_msc *msc =3D ris->vmsc->msc; + + if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + return false; + + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, 0) | + FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); + _mpam_write_monsel_reg(msc, mon_reg, mon_sel); + + _mpam_write_monsel_reg(msc, mon_reg, MSMON___NRDY); + now =3D _mpam_read_monsel_reg(msc, mon_reg); + can_set =3D now & MSMON___NRDY; + + _mpam_write_monsel_reg(msc, mon_reg, 0); + now =3D _mpam_read_monsel_reg(msc, mon_reg); + can_clear =3D !(now & MSMON___NRDY); + mpam_mon_sel_unlock(msc); + + return (!can_set || !can_clear); +} + +#define mpam_ris_hw_probe_hw_nrdy(_ris, _mon_reg) \ + _mpam_ris_hw_probe_hw_nrdy(_ris, MSMON_##_mon_reg) + +static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) +{ + int err; + struct mpam_msc *msc =3D ris->vmsc->msc; + struct device *dev =3D &msc->pdev->dev; + struct mpam_props *props =3D &ris->props; + + lockdep_assert_held(&msc->probe_lock); + lockdep_assert_held(&msc->part_sel_lock); + + /* Cache Portion partitioning */ + if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) { + u32 cpor_features =3D mpam_read_partsel_reg(msc, CPOR_IDR); + + props->cpbm_wd =3D FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features); + if (props->cpbm_wd) + mpam_set_feature(mpam_feat_cpor_part, props); + } + + /* Memory bandwidth partitioning */ + if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) { + u32 mbw_features =3D mpam_read_partsel_reg(msc, MBW_IDR); + + /* portion bitmap resolution */ + props->mbw_pbm_bits =3D FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features); + if (props->mbw_pbm_bits && + FIELD_GET(MPAMF_MBW_IDR_HAS_PBM, mbw_features)) + mpam_set_feature(mpam_feat_mbw_part, props); + + props->bwa_wd =3D FIELD_GET(MPAMF_MBW_IDR_BWA_WD, mbw_features); + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features)) + mpam_set_feature(mpam_feat_mbw_max, props); + } + + /* Performance Monitoring */ + if (FIELD_GET(MPAMF_IDR_HAS_MSMON, ris->idr)) { + u32 msmon_features =3D mpam_read_partsel_reg(msc, MSMON_IDR); + + /* + * If the firmware max-nrdy-us property is missing, the + * CSU counters can't be used. Should we wait forever? + */ + err =3D device_property_read_u32(&msc->pdev->dev, + "arm,not-ready-us", + &msc->nrdy_usec); + + if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_CSU, msmon_features)) { + u32 csumonidr; + + csumonidr =3D mpam_read_partsel_reg(msc, CSUMON_IDR); + props->num_csu_mon =3D FIELD_GET(MPAMF_CSUMON_IDR_NUM_MON, csumonidr); + if (props->num_csu_mon) { + bool hw_managed; + + mpam_set_feature(mpam_feat_msmon_csu, props); + + /* Is NRDY hardware managed? */ + hw_managed =3D mpam_ris_hw_probe_hw_nrdy(ris, CSU); + if (hw_managed) + mpam_set_feature(mpam_feat_msmon_csu_hw_nrdy, props); + } + + /* + * Accept the missing firmware property if NRDY appears + * un-implemented. + */ + if (err && mpam_has_feature(mpam_feat_msmon_csu_hw_nrdy, props)) + dev_err_once(dev, "Counters are not usable because not-ready timeout w= as not provided by firmware."); + } + if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_MBWU, msmon_features)) { + bool hw_managed; + u32 mbwumon_idr =3D mpam_read_partsel_reg(msc, MBWUMON_IDR); + + props->num_mbwu_mon =3D FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_id= r); + if (props->num_mbwu_mon) + mpam_set_feature(mpam_feat_msmon_mbwu, props); + + if (FIELD_GET(MPAMF_MBWUMON_IDR_HAS_RWBW, mbwumon_idr)) + mpam_set_feature(mpam_feat_msmon_mbwu_rwbw, props); + + /* Is NRDY hardware managed? */ + hw_managed =3D mpam_ris_hw_probe_hw_nrdy(ris, MBWU); + if (hw_managed) + mpam_set_feature(mpam_feat_msmon_mbwu_hw_nrdy, props); + + /* + * Don't warn about any missing firmware property for + * MBWU NRDY - it doesn't make any sense! + */ + } + } +} + static int mpam_msc_hw_probe(struct mpam_msc *msc) { u64 idr; @@ -592,6 +736,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) mutex_lock(&msc->part_sel_lock); idr =3D mpam_msc_read_idr(msc); mutex_unlock(&msc->part_sel_lock); + msc->ris_max =3D FIELD_GET(MPAMF_IDR_RIS_MAX, idr); =20 /* Use these values so partid/pmg always starts with a valid value */ @@ -614,6 +759,12 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) mutex_unlock(&mpam_list_lock); if (IS_ERR(ris)) return PTR_ERR(ris); + ris->idr =3D idr; + + mutex_lock(&msc->part_sel_lock); + __mpam_part_sel(ris_idx, 0, msc); + mpam_ris_hw_probe(ris); + mutex_unlock(&msc->part_sel_lock); } =20 spin_lock(&partid_max_lock); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 4cc44d4e21c4..5ae5d4eee8ec 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -112,6 +112,55 @@ static inline void mpam_mon_sel_lock_init(struct mpam_= msc *msc) raw_spin_lock_init(&msc->_mon_sel_lock); } =20 +/* + * When we compact the supported features, we don't care what they are. + * Storing them as a bitmap makes life easy. + */ +typedef u16 mpam_features_t; + +/* Bits for mpam_features_t */ +enum mpam_device_features { + mpam_feat_ccap_part =3D 0, + mpam_feat_cpor_part, + mpam_feat_mbw_part, + mpam_feat_mbw_min, + mpam_feat_mbw_max, + mpam_feat_mbw_prop, + mpam_feat_msmon, + mpam_feat_msmon_csu, + mpam_feat_msmon_csu_capture, + mpam_feat_msmon_csu_hw_nrdy, + mpam_feat_msmon_mbwu, + mpam_feat_msmon_mbwu_capture, + mpam_feat_msmon_mbwu_rwbw, + mpam_feat_msmon_mbwu_hw_nrdy, + mpam_feat_msmon_capt, + MPAM_FEATURE_LAST, +}; +static_assert(BITS_PER_TYPE(mpam_features_t) >=3D MPAM_FEATURE_LAST); + +struct mpam_props { + mpam_features_t features; + + u16 cpbm_wd; + u16 mbw_pbm_bits; + u16 bwa_wd; + u16 num_csu_mon; + u16 num_mbwu_mon; +}; + +static inline bool mpam_has_feature(enum mpam_device_features feat, + struct mpam_props *props) +{ + return (1 << feat) & props->features; +} + +static inline void mpam_set_feature(enum mpam_device_features feat, + struct mpam_props *props) +{ + props->features |=3D (1 << feat); +} + struct mpam_class { /* mpam_components in this class */ struct list_head components; @@ -151,6 +200,8 @@ struct mpam_vmsc { /* mpam_msc_ris in this vmsc */ struct list_head ris; =20 + struct mpam_props props; + /* All RIS in this vMSC are members of this MSC */ struct mpam_msc *msc; =20 @@ -162,6 +213,8 @@ struct mpam_vmsc { =20 struct mpam_msc_ris { u8 ris_idx; + u64 idr; + struct mpam_props props; =20 cpumask_t affinity; =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E889A3191DA; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 450471C0A; Wed, 10 Sep 2025 13:44:32 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D1DD13F63F; Wed, 10 Sep 2025 13:44:35 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 14/29] arm_mpam: Merge supported features during mpam_enable() into mpam_class Date: Wed, 10 Sep 2025 20:42:54 +0000 Message-Id: <20250910204309.20751-15-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To make a decision about whether to expose an mpam class as a resctrl resource we need to know its overall supported features and properties. Once we've probed all the resources, we can walk the tree and produce overall values by merging the bitmaps. This eliminates features that are only supported by some MSC that make up a component or class. If bitmap properties are mismatched within a component we cannot support the mismatched feature. Care has to be taken as vMSC may hold mismatched RIS. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- drivers/resctrl/mpam_devices.c | 215 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 8 ++ 2 files changed, 223 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index ba8e8839cdc4..cd8e95fa5fd6 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -961,8 +961,223 @@ static struct platform_driver mpam_msc_driver =3D { .remove =3D mpam_msc_drv_remove, }; =20 +/* Any of these features mean the BWA_WD field is valid. */ +static bool mpam_has_bwa_wd_feature(struct mpam_props *props) +{ + if (mpam_has_feature(mpam_feat_mbw_min, props)) + return true; + if (mpam_has_feature(mpam_feat_mbw_max, props)) + return true; + if (mpam_has_feature(mpam_feat_mbw_prop, props)) + return true; + return false; +} + +#define MISMATCHED_HELPER(parent, child, helper, field, alias) \ + helper(parent) && \ + ((helper(child) && (parent)->field !=3D (child)->field) || \ + (!helper(child) && !(alias))) + +#define MISMATCHED_FEAT(parent, child, feat, field, alias) \ + mpam_has_feature((feat), (parent)) && \ + ((mpam_has_feature((feat), (child)) && (parent)->field !=3D (child)->fiel= d) || \ + (!mpam_has_feature((feat), (child)) && !(alias))) + +#define CAN_MERGE_FEAT(parent, child, feat, alias) \ + (alias) && !mpam_has_feature((feat), (parent)) && \ + mpam_has_feature((feat), (child)) + +/* + * Combine two props fields. + * If this is for controls that alias the same resource, it is safe to just + * copy the values over. If two aliasing controls implement the same scheme + * a safe value must be picked. + * For non-aliasing controls, these control different resources, and the + * resulting safe value must be compatible with both. When merging values = in + * the tree, all the aliasing resources must be handled first. + * On mismatch, parent is modified. + */ +static void __props_mismatch(struct mpam_props *parent, + struct mpam_props *child, bool alias) +{ + if (CAN_MERGE_FEAT(parent, child, mpam_feat_cpor_part, alias)) { + parent->cpbm_wd =3D child->cpbm_wd; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_cpor_part, + cpbm_wd, alias)) { + pr_debug("%s cleared cpor_part\n", __func__); + mpam_clear_feature(mpam_feat_cpor_part, &parent->features); + parent->cpbm_wd =3D 0; + } + + if (CAN_MERGE_FEAT(parent, child, mpam_feat_mbw_part, alias)) { + parent->mbw_pbm_bits =3D child->mbw_pbm_bits; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_mbw_part, + mbw_pbm_bits, alias)) { + pr_debug("%s cleared mbw_part\n", __func__); + mpam_clear_feature(mpam_feat_mbw_part, &parent->features); + parent->mbw_pbm_bits =3D 0; + } + + /* bwa_wd is a count of bits, fewer bits means less precision */ + if (alias && !mpam_has_bwa_wd_feature(parent) && mpam_has_bwa_wd_feature(= child)) { + parent->bwa_wd =3D child->bwa_wd; + } else if (MISMATCHED_HELPER(parent, child, mpam_has_bwa_wd_feature, + bwa_wd, alias)) { + pr_debug("%s took the min bwa_wd\n", __func__); + parent->bwa_wd =3D min(parent->bwa_wd, child->bwa_wd); + } + + /* For num properties, take the minimum */ + if (CAN_MERGE_FEAT(parent, child, mpam_feat_msmon_csu, alias)) { + parent->num_csu_mon =3D child->num_csu_mon; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_msmon_csu, + num_csu_mon, alias)) { + pr_debug("%s took the min num_csu_mon\n", __func__); + parent->num_csu_mon =3D min(parent->num_csu_mon, child->num_csu_mon); + } + + if (CAN_MERGE_FEAT(parent, child, mpam_feat_msmon_mbwu, alias)) { + parent->num_mbwu_mon =3D child->num_mbwu_mon; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_msmon_mbwu, + num_mbwu_mon, alias)) { + pr_debug("%s took the min num_mbwu_mon\n", __func__); + parent->num_mbwu_mon =3D min(parent->num_mbwu_mon, child->num_mbwu_mon); + } + + if (alias) { + /* Merge features for aliased resources */ + parent->features |=3D child->features; + } else { + /* Clear missing features for non aliasing */ + parent->features &=3D child->features; + } +} + +/* + * If a vmsc doesn't match class feature/configuration, do the right thing= (tm). + * For 'num' properties we can just take the minimum. + * For properties where the mismatched unused bits would make a difference= , we + * nobble the class feature, as we can't configure all the resources. + * e.g. The L3 cache is composed of two resources with 13 and 17 portion + * bitmaps respectively. + */ +static void +__class_props_mismatch(struct mpam_class *class, struct mpam_vmsc *vmsc) +{ + struct mpam_props *cprops =3D &class->props; + struct mpam_props *vprops =3D &vmsc->props; + + lockdep_assert_held(&mpam_list_lock); /* we modify class */ + + pr_debug("%s: Merging features for class:0x%lx &=3D vmsc:0x%lx\n", + dev_name(&vmsc->msc->pdev->dev), + (long)cprops->features, (long)vprops->features); + + /* Take the safe value for any common features */ + __props_mismatch(cprops, vprops, false); +} + +static void +__vmsc_props_mismatch(struct mpam_vmsc *vmsc, struct mpam_msc_ris *ris) +{ + struct mpam_props *rprops =3D &ris->props; + struct mpam_props *vprops =3D &vmsc->props; + + lockdep_assert_held(&mpam_list_lock); /* we modify vmsc */ + + pr_debug("%s: Merging features for vmsc:0x%lx |=3D ris:0x%lx\n", + dev_name(&vmsc->msc->pdev->dev), + (long)vprops->features, (long)rprops->features); + + /* + * Merge mismatched features - Copy any features that aren't common, + * but take the safe value for any common features. + */ + __props_mismatch(vprops, rprops, true); +} + +/* + * Copy the first component's first vMSC's properties and features to the + * class. __class_props_mismatch() will remove conflicts. + * It is not possible to have a class with no components, or a component w= ith + * no resources. The vMSC properties have already been built. + */ +static void mpam_enable_init_class_features(struct mpam_class *class) +{ + struct mpam_vmsc *vmsc; + struct mpam_component *comp; + + comp =3D list_first_entry_or_null(&class->components, + struct mpam_component, class_list); + if (WARN_ON(!comp)) + return; + + vmsc =3D list_first_entry_or_null(&comp->vmsc, + struct mpam_vmsc, comp_list); + if (WARN_ON(!vmsc)) + return; + + class->props =3D vmsc->props; +} + +static void mpam_enable_merge_vmsc_features(struct mpam_component *comp) +{ + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + struct mpam_class *class =3D comp->class; + + list_for_each_entry(vmsc, &comp->vmsc, comp_list) { + list_for_each_entry(ris, &vmsc->ris, vmsc_list) { + __vmsc_props_mismatch(vmsc, ris); + class->nrdy_usec =3D max(class->nrdy_usec, + vmsc->msc->nrdy_usec); + } + } +} + +static void mpam_enable_merge_class_features(struct mpam_component *comp) +{ + struct mpam_vmsc *vmsc; + struct mpam_class *class =3D comp->class; + + list_for_each_entry(vmsc, &comp->vmsc, comp_list) + __class_props_mismatch(class, vmsc); +} + +/* + * Merge all the common resource features into class. + * vmsc features are bitwise-or'd together, this must be done first. + * Next the class features are the bitwise-and of all the vmsc features. + * Other features are the min/max as appropriate. + * + * To avoid walking the whole tree twice, the class->nrdy_usec property is + * updated when working with the vmsc as it is a max(), and doesn't need + * initialising first. + */ +static void mpam_enable_merge_features(struct list_head *all_classes_list) +{ + struct mpam_class *class; + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(class, all_classes_list, classes_list) { + list_for_each_entry(comp, &class->components, class_list) + mpam_enable_merge_vmsc_features(comp); + + mpam_enable_init_class_features(class); + + list_for_each_entry(comp, &class->components, class_list) + mpam_enable_merge_class_features(comp); + } +} + static void mpam_enable_once(void) { + mutex_lock(&mpam_list_lock); + mpam_enable_merge_features(&mpam_classes); + mutex_unlock(&mpam_list_lock); + /* * Once the cpuhp callbacks have been changed, mpam_partid_max can no * longer change. diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 5ae5d4eee8ec..eace5ba871f3 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -161,12 +161,20 @@ static inline void mpam_set_feature(enum mpam_device_= features feat, props->features |=3D (1 << feat); } =20 +static inline void mpam_clear_feature(enum mpam_device_features feat, + mpam_features_t *supported) +{ + *supported &=3D ~(1 << feat); +} + struct mpam_class { /* mpam_components in this class */ struct list_head components; =20 cpumask_t affinity; =20 + struct mpam_props props; + u32 nrdy_usec; u8 level; enum mpam_class_types type; =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 67DDE32142B; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B8601EDB; Wed, 10 Sep 2025 13:44:37 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E70113F63F; Wed, 10 Sep 2025 13:44:40 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Rohit Mathew Subject: [PATCH v2 15/29] arm_mpam: Reset MSC controls from cpu hp callbacks Date: Wed, 10 Sep 2025 20:42:55 +0000 Message-Id: <20250910204309.20751-16-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When a CPU comes online, it may bring a newly accessible MSC with it. Only the default partid has its value reset by hardware, and even then the MSC might not have been reset since its config was previously dirtyied. e.g. Kexec. Any in-use partid must have its configuration restored, or reset. In-use partids may be held in caches and evicted later. MSC are also reset when CPUs are taken offline to cover cases where firmware doesn't reset the MSC over reboot using UEFI, or kexec where there is no firmware involvement. If the configuration for a RIS has not been touched since it was brought online, it does not need resetting again. To reset, write the maximum values for all discovered controls. CC: Rohit Mathew Signed-off-by: James Morse --- Changes since RFC: * Last bitmap write will always be non-zero. * Dropped READ_ONCE() - teh value can no longer change. * Write 0 to proporitional stride, remove the bwa_fract variable. * Removed nested srcu lock, the assert should cover it. --- drivers/resctrl/mpam_devices.c | 117 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 8 +++ 2 files changed, 125 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index cd8e95fa5fd6..0353313cf284 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -777,8 +778,110 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) return 0; } =20 +static void mpam_reset_msc_bitmap(struct mpam_msc *msc, u16 reg, u16 wd) +{ + u32 num_words, msb; + u32 bm =3D ~0; + int i; + + lockdep_assert_held(&msc->part_sel_lock); + + if (wd =3D=3D 0) + return; + + /* + * Write all ~0 to all but the last 32bit-word, which may + * have fewer bits... + */ + num_words =3D DIV_ROUND_UP(wd, 32); + for (i =3D 0; i < num_words - 1; i++, reg +=3D sizeof(bm)) + __mpam_write_reg(msc, reg, bm); + + /* + * ....and then the last (maybe) partial 32bit word. When wd is a + * multiple of 32, msb should be 31 to write a full 32bit word. + */ + msb =3D (wd - 1) % 32; + bm =3D GENMASK(msb, 0); + __mpam_write_reg(msc, reg, bm); +} + +static void mpam_reset_ris_partid(struct mpam_msc_ris *ris, u16 partid) +{ + struct mpam_msc *msc =3D ris->vmsc->msc; + struct mpam_props *rprops =3D &ris->props; + + mpam_assert_srcu_read_lock_held(); + + mutex_lock(&msc->part_sel_lock); + __mpam_part_sel(ris->ris_idx, partid, msc); + + if (mpam_has_feature(mpam_feat_cpor_part, rprops)) + mpam_reset_msc_bitmap(msc, MPAMCFG_CPBM, rprops->cpbm_wd); + + if (mpam_has_feature(mpam_feat_mbw_part, rprops)) + mpam_reset_msc_bitmap(msc, MPAMCFG_MBW_PBM, rprops->mbw_pbm_bits); + + if (mpam_has_feature(mpam_feat_mbw_min, rprops)) + mpam_write_partsel_reg(msc, MBW_MIN, 0); + + if (mpam_has_feature(mpam_feat_mbw_max, rprops)) + mpam_write_partsel_reg(msc, MBW_MAX, MPAMCFG_MBW_MAX_MAX); + + if (mpam_has_feature(mpam_feat_mbw_prop, rprops)) + mpam_write_partsel_reg(msc, MBW_PROP, 0); + mutex_unlock(&msc->part_sel_lock); +} + +static void mpam_reset_ris(struct mpam_msc_ris *ris) +{ + u16 partid, partid_max; + + mpam_assert_srcu_read_lock_held(); + + if (ris->in_reset_state) + return; + + spin_lock(&partid_max_lock); + partid_max =3D mpam_partid_max; + spin_unlock(&partid_max_lock); + for (partid =3D 0; partid < partid_max; partid++) + mpam_reset_ris_partid(ris, partid); +} + +static void mpam_reset_msc(struct mpam_msc *msc, bool online) +{ + struct mpam_msc_ris *ris; + + mpam_assert_srcu_read_lock_held(); + + list_for_each_entry_srcu(ris, &msc->ris, msc_list, srcu_read_lock_held(&m= pam_srcu)) { + mpam_reset_ris(ris); + + /* + * Set in_reset_state when coming online. The reset state + * for non-zero partid may be lost while the CPUs are offline. + */ + ris->in_reset_state =3D online; + } +} + static int mpam_cpu_online(unsigned int cpu) { + int idx; + struct mpam_msc *msc; + + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + if (!cpumask_test_cpu(cpu, &msc->accessibility)) + continue; + + if (atomic_fetch_inc(&msc->online_refs) =3D=3D 0) + mpam_reset_msc(msc, true); + } + srcu_read_unlock(&mpam_srcu, idx); + return 0; } =20 @@ -818,6 +921,20 @@ static int mpam_discovery_cpu_online(unsigned int cpu) =20 static int mpam_cpu_offline(unsigned int cpu) { + int idx; + struct mpam_msc *msc; + + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + if (!cpumask_test_cpu(cpu, &msc->accessibility)) + continue; + + if (atomic_dec_and_test(&msc->online_refs)) + mpam_reset_msc(msc, false); + } + srcu_read_unlock(&mpam_srcu, idx); + return 0; } =20 diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index eace5ba871f3..6e047fbd3512 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -5,6 +5,7 @@ #define MPAM_INTERNAL_H =20 #include +#include #include #include #include @@ -45,6 +46,7 @@ struct mpam_msc { struct pcc_mbox_chan *pcc_chan; u32 nrdy_usec; cpumask_t accessibility; + atomic_t online_refs; =20 /* * probe_lock is only taken during discovery. After discovery these @@ -223,6 +225,7 @@ struct mpam_msc_ris { u8 ris_idx; u64 idr; struct mpam_props props; + bool in_reset_state; =20 cpumask_t affinity; =20 @@ -242,6 +245,11 @@ struct mpam_msc_ris { extern struct srcu_struct mpam_srcu; extern struct list_head mpam_classes; =20 +static inline void mpam_assert_srcu_read_lock_held(void) +{ + WARN_ON_ONCE(!srcu_read_lock_held((&mpam_srcu))); +} + /* System wide partid/pmg values */ extern u16 mpam_partid_max; extern u8 mpam_pmg_max; --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7B44032F75A; Wed, 10 Sep 2025 20:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537093; cv=none; b=hBBHDMsqV32Uo5rQ0l+Erhf/BNsdVTs6REHJPOlMtJgKt2ln7vKeBUVj4hCP4ujCptW2KHfAZuzBNY0m39CcPxqmCrjnoCe3yhmSyBl4WG/CsfiiPRY8AEFFg/r9kWlrJaUZxgRgSZpmJFlRaWSWiRIvcaLjngAa16pZcjYnvF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537093; c=relaxed/simple; bh=ecboDpRgZG84ERgK0CvlpjbQW/NKOjcHN8P8jEJMmXM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XQmHJSXfrg+L1VUydtY/Jrjd6hDmx7RAI6OdcStkDVEl4CuJsjPMUDEU8GWFQN+wk6/s3/CFE/CGDbMS8Alw0+GJqruFI011lz20gDBmRdTPm6RRWjA3k/fByWfpQkzTRYzhfHbEh2y2Jrr56L4ZxRzbIhg99OB6V1jdSmMRfKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 80FB31C0A; Wed, 10 Sep 2025 13:44:42 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A3063F63F; Wed, 10 Sep 2025 13:44:45 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 16/29] arm_mpam: Add a helper to touch an MSC from any CPU Date: Wed, 10 Sep 2025 20:42:56 +0000 Message-Id: <20250910204309.20751-17-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Resetting RIS entries from the cpuhp callback is easy as the callback occurs on the correct CPU. This won't be true for any other caller that wants to reset or configure an MSC. Add a helper that schedules the provided function if necessary. Callers should take the cpuhp lock to prevent the cpuhp callbacks from changing the MSC state. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- drivers/resctrl/mpam_devices.c | 37 +++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 0353313cf284..e7faf453b5d7 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -833,20 +833,51 @@ static void mpam_reset_ris_partid(struct mpam_msc_ris= *ris, u16 partid) mutex_unlock(&msc->part_sel_lock); } =20 -static void mpam_reset_ris(struct mpam_msc_ris *ris) +/* + * Called via smp_call_on_cpu() to prevent migration, while still being + * pre-emptible. + */ +static int mpam_reset_ris(void *arg) { u16 partid, partid_max; + struct mpam_msc_ris *ris =3D arg; =20 mpam_assert_srcu_read_lock_held(); =20 if (ris->in_reset_state) - return; + return 0; =20 spin_lock(&partid_max_lock); partid_max =3D mpam_partid_max; spin_unlock(&partid_max_lock); for (partid =3D 0; partid < partid_max; partid++) mpam_reset_ris_partid(ris, partid); + + return 0; +} + +/* + * Get the preferred CPU for this MSC. If it is accessible from this CPU, + * this CPU is preferred. This can be preempted/migrated, it will only res= ult + * in more work. + */ +static int mpam_get_msc_preferred_cpu(struct mpam_msc *msc) +{ + int cpu =3D raw_smp_processor_id(); + + if (cpumask_test_cpu(cpu, &msc->accessibility)) + return cpu; + + return cpumask_first_and(&msc->accessibility, cpu_online_mask); +} + +static int mpam_touch_msc(struct mpam_msc *msc, int (*fn)(void *a), void *= arg) +{ + lockdep_assert_irqs_enabled(); + lockdep_assert_cpus_held(); + mpam_assert_srcu_read_lock_held(); + + return smp_call_on_cpu(mpam_get_msc_preferred_cpu(msc), fn, arg, true); } =20 static void mpam_reset_msc(struct mpam_msc *msc, bool online) @@ -856,7 +887,7 @@ static void mpam_reset_msc(struct mpam_msc *msc, bool o= nline) mpam_assert_srcu_read_lock_held(); =20 list_for_each_entry_srcu(ris, &msc->ris, msc_list, srcu_read_lock_held(&m= pam_srcu)) { - mpam_reset_ris(ris); + mpam_touch_msc(msc, &mpam_reset_ris, ris); =20 /* * Set in_reset_state when coming online. The reset state --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 60ADE340D83; Wed, 10 Sep 2025 20:44:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537098; cv=none; b=WWJzIsWjbQ+Z2t3BipiIQHhK/p7Xxj361zrdwZysZYdDh94pJJPuykbmZoNugE7mneSzGJ1BSptlDciGD77i094cROf050ZeyvA49EGkaBxMH3NdFWZIKH02h2YO/vGry+ADVmt6NXaJJ/Ksc0EswVfOSvCDbmjpjleJji+rjWM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537098; c=relaxed/simple; bh=3KZYD7Z7TcbCEIPnBJHHIhpfRjculKakBilZ/Wgo8ng=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OcEBFu0vPsC6ogjB3Nh/K7B+gBHm5QnShuapWe3eAcZtKpF+gKsPeYOgk0fMpR1uFE1JnWWa2E/R7+y6U4383yybeuMGAFM7qd0k8o7Jog7JeylmaFLGRrKaXITz6M5ND/DMP04VBwa0OMTf2pT7vNg2FHPBWCgqfuPyTR5IivA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 760EC22EA; Wed, 10 Sep 2025 13:44:47 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 30FBD3F63F; Wed, 10 Sep 2025 13:44:51 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 17/29] arm_mpam: Extend reset logic to allow devices to be reset any time Date: Wed, 10 Sep 2025 20:42:57 +0000 Message-Id: <20250910204309.20751-18-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" cpuhp callbacks aren't the only time the MSC configuration may need to be reset. Resctrl has an API call to reset a class. If an MPAM error interrupt arrives it indicates the driver has misprogrammed an MSC. The safest thing to do is reset all the MSCs and disable MPAM. Add a helper to reset RIS via their class. Call this from mpam_disable(), which can be scheduled from the error interrupt handler. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- Changes since v1: * more complete use of _srcu helpers. * Use guard macro for srcu. * Dropped a might_sleep() - something else will bark. --- drivers/resctrl/mpam_devices.c | 56 ++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index e7faf453b5d7..a9d3c4b09976 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -842,8 +842,6 @@ static int mpam_reset_ris(void *arg) u16 partid, partid_max; struct mpam_msc_ris *ris =3D arg; =20 - mpam_assert_srcu_read_lock_held(); - if (ris->in_reset_state) return 0; =20 @@ -1340,8 +1338,56 @@ static void mpam_enable_once(void) mpam_partid_max + 1, mpam_pmg_max + 1); } =20 +static void mpam_reset_component_locked(struct mpam_component *comp) +{ + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(vmsc, &comp->vmsc, comp_list, + srcu_read_lock_held(&mpam_srcu)) { + msc =3D vmsc->msc; + + list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list, + srcu_read_lock_held(&mpam_srcu)) { + if (!ris->in_reset_state) + mpam_touch_msc(msc, mpam_reset_ris, ris); + ris->in_reset_state =3D true; + } + } +} + +static void mpam_reset_class_locked(struct mpam_class *class) +{ + struct mpam_component *comp; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(comp, &class->components, class_list, + srcu_read_lock_held(&mpam_srcu)) + mpam_reset_component_locked(comp); +} + +static void mpam_reset_class(struct mpam_class *class) +{ + cpus_read_lock(); + mpam_reset_class_locked(class); + cpus_read_unlock(); +} + +/* + * Called in response to an error IRQ. + * All of MPAMs errors indicate a software bug, restore any modified + * controls to their reset values. + */ void mpam_disable(struct work_struct *ignored) { + int idx; + struct mpam_class *class; struct mpam_msc *msc, *tmp; =20 mutex_lock(&mpam_cpuhp_state_lock); @@ -1351,6 +1397,12 @@ void mpam_disable(struct work_struct *ignored) } mutex_unlock(&mpam_cpuhp_state_lock); =20 + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(class, &mpam_classes, classes_list, + srcu_read_lock_held(&mpam_srcu)) + mpam_reset_class(class); + srcu_read_unlock(&mpam_srcu, idx); + mutex_lock(&mpam_list_lock); list_for_each_entry_safe(msc, tmp, &mpam_all_msc, all_msc_list) mpam_msc_destroy(msc); --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6B518313535; Wed, 10 Sep 2025 20:45:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537104; cv=none; b=jAxfEhbLhS71Y2MckfhA4xYZc0x4NkdxIZizHEutbz+3EL6jPLqeNvAh8joEqD4tFTrbdVDrMmInK5a9f0RmyndztII6QfHpxgxZD1NUKUgxvMYtmRCEeRpsu5x6BSZeWl77+/Z5mlD7XE6JkvvwJjIchhsppGDrnTpZ3O3svMQ= ARC-Message-Signature: i=1; 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Wed, 10 Sep 2025 13:44:56 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 18/29] arm_mpam: Register and enable IRQs Date: Wed, 10 Sep 2025 20:42:58 +0000 Message-Id: <20250910204309.20751-19-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register and enable error IRQs. All the MPAM error interrupts indicate a software bug, e.g. out of range partid. If the error interrupt is ever signalled, attempt to disable MPAM. Only the irq handler accesses the ESR register, so no locking is needed. The work to disable MPAM after an error needs to happen at process context as it takes mutex. It also unregisters the interrupts, meaning it can't be done from the threaded part of a threaded interrupt. Instead, mpam_disable() gets scheduled. Enabling the IRQs in the MSC may involve cross calling to a CPU that can access the MSC. Once the IRQ is requested, the mpam_disable() path can be called asynchronously, which will walk structures sized by max_partid. Ensure this size is fixed before the interrupt is requested. CC: Rohit Mathew Tested-by: Rohit Mathew Signed-off-by: James Morse --- Changes since v1: * Made mpam_unregister_irqs() safe to race with itself. * Removed threaded interrupts. * Schedule mpam_disable() from cpuhp callback in the case of an error. * Added mpam_disable_reason. * Use alloc_percpu() Changes since RFC: * Use guard marco when walking srcu list. * Use INTEN macro for enabling interrupts. * Move partid_max_published up earlier in mpam_enable_once(). --- drivers/resctrl/mpam_devices.c | 277 +++++++++++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 10 ++ 2 files changed, 284 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index a9d3c4b09976..e7e4afc1ea95 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -14,6 +14,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -166,6 +169,24 @@ static u64 mpam_msc_read_idr(struct mpam_msc *msc) return (idr_high << 32) | idr_low; } =20 +static void mpam_msc_zero_esr(struct mpam_msc *msc) +{ + __mpam_write_reg(msc, MPAMF_ESR, 0); + if (msc->has_extd_esr) + __mpam_write_reg(msc, MPAMF_ESR + 4, 0); +} + +static u64 mpam_msc_read_esr(struct mpam_msc *msc) +{ + u64 esr_high =3D 0, esr_low; + + esr_low =3D __mpam_read_reg(msc, MPAMF_ESR); + if (msc->has_extd_esr) + esr_high =3D __mpam_read_reg(msc, MPAMF_ESR + 4); + + return (esr_high << 32) | esr_low; +} + static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc) { lockdep_assert_held(&msc->part_sel_lock); @@ -754,6 +775,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) pmg_max =3D FIELD_GET(MPAMF_IDR_PMG_MAX, idr); msc->partid_max =3D min(msc->partid_max, partid_max); msc->pmg_max =3D min(msc->pmg_max, pmg_max); + msc->has_extd_esr =3D FIELD_GET(MPAMF_IDR_HAS_EXTD_ESR, idr); =20 mutex_lock(&mpam_list_lock); ris =3D mpam_get_or_create_ris(msc, ris_idx); @@ -768,6 +790,9 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) mutex_unlock(&msc->part_sel_lock); } =20 + /* Clear any stale errors */ + mpam_msc_zero_esr(msc); + spin_lock(&partid_max_lock); mpam_partid_max =3D min(mpam_partid_max, msc->partid_max); mpam_pmg_max =3D min(mpam_pmg_max, msc->pmg_max); @@ -895,6 +920,13 @@ static void mpam_reset_msc(struct mpam_msc *msc, bool = online) } } =20 +static void _enable_percpu_irq(void *_irq) +{ + int *irq =3D _irq; + + enable_percpu_irq(*irq, IRQ_TYPE_NONE); +} + static int mpam_cpu_online(unsigned int cpu) { int idx; @@ -906,6 +938,9 @@ static int mpam_cpu_online(unsigned int cpu) if (!cpumask_test_cpu(cpu, &msc->accessibility)) continue; =20 + if (msc->reenable_error_ppi) + _enable_percpu_irq(&msc->reenable_error_ppi); + if (atomic_fetch_inc(&msc->online_refs) =3D=3D 0) mpam_reset_msc(msc, true); } @@ -959,6 +994,9 @@ static int mpam_cpu_offline(unsigned int cpu) if (!cpumask_test_cpu(cpu, &msc->accessibility)) continue; =20 + if (msc->reenable_error_ppi) + disable_percpu_irq(msc->reenable_error_ppi); + if (atomic_dec_and_test(&msc->online_refs)) mpam_reset_msc(msc, false); } @@ -985,6 +1023,51 @@ static void mpam_register_cpuhp_callbacks(int (*onlin= e)(unsigned int online), mutex_unlock(&mpam_cpuhp_state_lock); } =20 +static int __setup_ppi(struct mpam_msc *msc) +{ + int cpu; + struct device *dev =3D &msc->pdev->dev; + + msc->error_dev_id =3D alloc_percpu(struct mpam_msc *); + if (!msc->error_dev_id) + return -ENOMEM; + + for_each_cpu(cpu, &msc->accessibility) { + struct mpam_msc *empty =3D *per_cpu_ptr(msc->error_dev_id, cpu); + + if (empty) { + dev_err_once(dev, "MSC shares PPI with %s!\n", + dev_name(&empty->pdev->dev)); + return -EBUSY; + } + *per_cpu_ptr(msc->error_dev_id, cpu) =3D msc; + } + + return 0; +} + +static int mpam_msc_setup_error_irq(struct mpam_msc *msc) +{ + int irq; + + irq =3D platform_get_irq_byname_optional(msc->pdev, "error"); + if (irq <=3D 0) + return 0; + + /* Allocate and initialise the percpu device pointer for PPI */ + if (irq_is_percpu(irq)) + return __setup_ppi(msc); + + /* sanity check: shared interrupts can be routed anywhere? */ + if (!cpumask_equal(&msc->accessibility, cpu_possible_mask)) { + pr_err_once("msc:%u is a private resource with a shared error interrupt", + msc->id); + return -EINVAL; + } + + return 0; +} + /* * An MSC can control traffic from a set of CPUs, but may only be accessib= le * from a (hopefully wider) set of CPUs. The common reason for this is pow= er @@ -1060,6 +1143,10 @@ static int mpam_msc_drv_probe(struct platform_device= *pdev) break; } =20 + err =3D mpam_msc_setup_error_irq(msc); + if (err) + break; + if (device_property_read_u32(&pdev->dev, "pcc-channel", &msc->pcc_subspace_id)) msc->iface =3D MPAM_IFACE_MMIO; @@ -1318,11 +1405,172 @@ static void mpam_enable_merge_features(struct list= _head *all_classes_list) } } =20 +static char *mpam_errcode_names[16] =3D { + [0] =3D "No error", + [1] =3D "PARTID_SEL_Range", + [2] =3D "Req_PARTID_Range", + [3] =3D "MSMONCFG_ID_RANGE", + [4] =3D "Req_PMG_Range", + [5] =3D "Monitor_Range", + [6] =3D "intPARTID_Range", + [7] =3D "Unexpected_INTERNAL", + [8] =3D "Undefined_RIS_PART_SEL", + [9] =3D "RIS_No_Control", + [10] =3D "Undefined_RIS_MON_SEL", + [11] =3D "RIS_No_Monitor", + [12 ... 15] =3D "Reserved" +}; + +static int mpam_enable_msc_ecr(void *_msc) +{ + struct mpam_msc *msc =3D _msc; + + __mpam_write_reg(msc, MPAMF_ECR, MPAMF_ECR_INTEN); + + return 0; +} + +/* This can run in mpam_disable(), and the interrupt handler on the same C= PU */ +static int mpam_disable_msc_ecr(void *_msc) +{ + struct mpam_msc *msc =3D _msc; + + __mpam_write_reg(msc, MPAMF_ECR, 0); + + return 0; +} + +static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) +{ + u64 reg; + u16 partid; + u8 errcode, pmg, ris; + + if (WARN_ON_ONCE(!msc) || + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), + &msc->accessibility))) + return IRQ_NONE; + + reg =3D mpam_msc_read_esr(msc); + + errcode =3D FIELD_GET(MPAMF_ESR_ERRCODE, reg); + if (!errcode) + return IRQ_NONE; + + /* Clear level triggered irq */ + mpam_msc_zero_esr(msc); + + partid =3D FIELD_GET(MPAMF_ESR_PARTID_MON, reg); + pmg =3D FIELD_GET(MPAMF_ESR_PMG, reg); + ris =3D FIELD_GET(MPAMF_ESR_RIS, reg); + + pr_err_ratelimited("error irq from msc:%u '%s', partid:%u, pmg: %u, ris: = %u\n", + msc->id, mpam_errcode_names[errcode], partid, pmg, + ris); + + /* Disable this interrupt. */ + mpam_disable_msc_ecr(msc); + + /* + * Schedule the teardown work. Don't use a threaded IRQ as we can't + * unregister the interrupt from the threaded part of the handler. + */ + mpam_disable_reason =3D "hardware error interrupt"; + schedule_work(&mpam_broken_work); + + return IRQ_HANDLED; +} + +static irqreturn_t mpam_ppi_handler(int irq, void *dev_id) +{ + struct mpam_msc *msc =3D *(struct mpam_msc **)dev_id; + + return __mpam_irq_handler(irq, msc); +} + +static irqreturn_t mpam_spi_handler(int irq, void *dev_id) +{ + struct mpam_msc *msc =3D dev_id; + + return __mpam_irq_handler(irq, msc); +} + +static int mpam_register_irqs(void) +{ + int err, irq; + struct mpam_msc *msc; + + lockdep_assert_cpus_held(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + irq =3D platform_get_irq_byname_optional(msc->pdev, "error"); + if (irq <=3D 0) + continue; + + /* The MPAM spec says the interrupt can be SPI, PPI or LPI */ + /* We anticipate sharing the interrupt with other MSCs */ + if (irq_is_percpu(irq)) { + err =3D request_percpu_irq(irq, &mpam_ppi_handler, + "mpam:msc:error", + msc->error_dev_id); + if (err) + return err; + + msc->reenable_error_ppi =3D irq; + smp_call_function_many(&msc->accessibility, + &_enable_percpu_irq, &irq, + true); + } else { + err =3D devm_request_irq(&msc->pdev->dev,irq, + &mpam_spi_handler, IRQF_SHARED, + "mpam:msc:error", msc); + if (err) + return err; + } + + set_bit(MPAM_ERROR_IRQ_REQUESTED, &msc->error_irq_flags); + mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); + set_bit(MPAM_ERROR_IRQ_HW_ENABLED, &msc->error_irq_flags); + } + + return 0; +} + +static void mpam_unregister_irqs(void) +{ + int irq, idx; + struct mpam_msc *msc; + + cpus_read_lock(); + /* take the lock as free_irq() can sleep */ + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, + srcu_read_lock_held(&mpam_srcu)) { + irq =3D platform_get_irq_byname_optional(msc->pdev, "error"); + if (irq <=3D 0) + continue; + + if (test_and_clear_bit(MPAM_ERROR_IRQ_HW_ENABLED, &msc->error_irq_flags)) + mpam_touch_msc(msc, mpam_disable_msc_ecr, msc); + + if (test_and_clear_bit(MPAM_ERROR_IRQ_REQUESTED, &msc->error_irq_flags))= { + if (irq_is_percpu(irq)) { + msc->reenable_error_ppi =3D 0; + free_percpu_irq(irq, msc->error_dev_id); + } else { + devm_free_irq(&msc->pdev->dev, irq, msc); + } + } + } + srcu_read_unlock(&mpam_srcu, idx); + cpus_read_unlock(); +} + static void mpam_enable_once(void) { - mutex_lock(&mpam_list_lock); - mpam_enable_merge_features(&mpam_classes); - mutex_unlock(&mpam_list_lock); + int err; =20 /* * Once the cpuhp callbacks have been changed, mpam_partid_max can no @@ -1332,6 +1580,27 @@ static void mpam_enable_once(void) partid_max_published =3D true; spin_unlock(&partid_max_lock); =20 + /* + * If all the MSC have been probed, enabling the IRQs happens next. + * That involves cross-calling to a CPU that can reach the MSC, and + * the locks must be taken in this order: + */ + cpus_read_lock(); + mutex_lock(&mpam_list_lock); + mpam_enable_merge_features(&mpam_classes); + + err =3D mpam_register_irqs(); + if (err) + pr_warn("Failed to register irqs: %d\n", err); + + mutex_unlock(&mpam_list_lock); + cpus_read_unlock(); + + if (err) { + schedule_work(&mpam_broken_work); + return; + } + mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline); =20 printk(KERN_INFO "MPAM enabled with %u PARTIDs and %u PMGs\n", @@ -1397,6 +1666,8 @@ void mpam_disable(struct work_struct *ignored) } mutex_unlock(&mpam_cpuhp_state_lock); =20 + mpam_unregister_irqs(); + idx =3D srcu_read_lock(&mpam_srcu); list_for_each_entry_srcu(class, &mpam_classes, classes_list, srcu_read_lock_held(&mpam_srcu)) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 6e047fbd3512..f04a9ef189cf 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -32,6 +32,10 @@ struct mpam_garbage { struct platform_device *pdev; }; =20 +/* Bit positions for error_irq_flags */ +#define MPAM_ERROR_IRQ_REQUESTED 0 +#define MPAM_ERROR_IRQ_HW_ENABLED 1 + struct mpam_msc { /* member of mpam_all_msc */ struct list_head all_msc_list; @@ -46,6 +50,11 @@ struct mpam_msc { struct pcc_mbox_chan *pcc_chan; u32 nrdy_usec; cpumask_t accessibility; + bool has_extd_esr; + + int reenable_error_ppi; + struct mpam_msc * __percpu *error_dev_id; + atomic_t online_refs; =20 /* @@ -54,6 +63,7 @@ struct mpam_msc { */ struct mutex probe_lock; bool probed; + unsigned long error_irq_flags; u16 partid_max; u8 pmg_max; unsigned long ris_idxs; --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 428B9340DB8; Wed, 10 Sep 2025 20:45:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537107; cv=none; b=JWTVOSSU1bNf63NBfbGzc2XRAlBNhaCfgvLjzcFp8RiKGWz9wkzbPCO30TQg/iWV3vPuWjfmyRxfIbIgV6edh3W3n+uaUAc8TcAPlxsJZdRBx717D6mwfxzGGJethqNV++dq3lxiYRdhtCv6iUqGp4det6getUQFG3ncXoijT1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537107; c=relaxed/simple; bh=Jf0Qy8hxlxqlgcAaS+9CrrG+bpgVUMXaHXpO4R1PKDo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BAbHp93RtEti0bqR087kQBRIhV+bwxsNWx29FjIz22uoJ3/cYc4fZd/GjE53HyAo8YrWSW9RlVyWn4ODjYOoWiIZ/KvvDTdevXvG2ZjMctpJpooZYgVtlNveCJotHYvk04Vuk0jtEV69RhSI3duEtA6HCOYP0l4q1sPMWtoBxFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 592BF1C0A; Wed, 10 Sep 2025 13:44:57 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 166F13F63F; Wed, 10 Sep 2025 13:45:00 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 19/29] arm_mpam: Use a static key to indicate when mpam is enabled Date: Wed, 10 Sep 2025 20:42:59 +0000 Message-Id: <20250910204309.20751-20-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Once all the MSC have been probed, the system wide usable number of PARTID is known and the configuration arrays can be allocated. After this point, checking all the MSC have been probed is pointless, and the cpuhp callbacks should restore the configuration, instead of just resetting the MSC. Add a static key to enable this behaviour. This will also allow MPAM to be disabled in repsonse to an error, and the architecture code to enable/disable the context switch of the MPAM system registers. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Fenghua Yu Reviewed-by: Jonathan Cameron --- drivers/resctrl/mpam_devices.c | 12 ++++++++++++ drivers/resctrl/mpam_internal.h | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index e7e4afc1ea95..ec1db5f8b05c 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -29,6 +29,8 @@ =20 #include "mpam_internal.h" =20 +DEFINE_STATIC_KEY_FALSE(mpam_enabled); /* TODO: move to arch code */ + /* * mpam_list_lock protects the SRCU lists when writing. Once the * mpam_enabled key is enabled these lists are read-only, @@ -956,6 +958,9 @@ static int mpam_discovery_cpu_online(unsigned int cpu) struct mpam_msc *msc; bool new_device_probed =3D false; =20 + if (mpam_is_enabled()) + return 0; + guard(srcu)(&mpam_srcu); list_for_each_entry_srcu(msc, &mpam_all_msc, all_msc_list, srcu_read_lock_held(&mpam_srcu)) { @@ -1471,6 +1476,10 @@ static irqreturn_t __mpam_irq_handler(int irq, struc= t mpam_msc *msc) /* Disable this interrupt. */ mpam_disable_msc_ecr(msc); =20 + /* Are we racing with the thread disabling MPAM? */ + if (!mpam_is_enabled()) + return IRQ_HANDLED; + /* * Schedule the teardown work. Don't use a threaded IRQ as we can't * unregister the interrupt from the threaded part of the handler. @@ -1601,6 +1610,7 @@ static void mpam_enable_once(void) return; } =20 + static_branch_enable(&mpam_enabled); mpam_register_cpuhp_callbacks(mpam_cpu_online, mpam_cpu_offline); =20 printk(KERN_INFO "MPAM enabled with %u PARTIDs and %u PMGs\n", @@ -1666,6 +1676,8 @@ void mpam_disable(struct work_struct *ignored) } mutex_unlock(&mpam_cpuhp_state_lock); =20 + static_branch_disable(&mpam_enabled); + mpam_unregister_irqs(); =20 idx =3D srcu_read_lock(&mpam_srcu); diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index f04a9ef189cf..b69fa9199cb4 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -17,6 +18,13 @@ =20 #define MPAM_MSC_MAX_NUM_RIS 16 =20 +DECLARE_STATIC_KEY_FALSE(mpam_enabled); + +static inline bool mpam_is_enabled(void) +{ + return static_branch_likely(&mpam_enabled); +} + /* * Structures protected by SRCU may not be freed for a surprising amount of * time (especially if perf is running). To ensure the MPAM error interrup= t can --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36D3E34166F; Wed, 10 Sep 2025 20:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537113; cv=none; b=i1TT/2Xbedhusn2QlwJEEaFKYcpkjmMqkdMemUyVti+FDPoCeSrLwvf09oY0LScEB0xbzPela5yMvV2/nJnyBg4uE3zx5RDCqfHJM7k382MMN5aut4lQCUTSjlO/eKIhKTE9AjASkY08OGFix7eP13Hybs8pCQuqJMChdSQnnHc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537113; c=relaxed/simple; bh=o+xFkpUfgOG9TcCM2SUXqYxVokWP+lHkm3PeLjE2MzY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BYpJ7/wmdkejaqZwPNg/cABwuMM3hrau7OsNPn0hZBN2IVUnkcDhw5478fAg8iej8u+c7UjB6ojArnjWNeGsRANPkfqCvEAjyXiqOBDQqRm8pCT2/MjZ26GyqjM2DIQZZZPbVRbJEoSjxhKU1ZLfgpFDuAXgsANql16UZ/5ClJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71DC4244C; Wed, 10 Sep 2025 13:45:02 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 099733F63F; Wed, 10 Sep 2025 13:45:05 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Dave Martin Subject: [PATCH v2 20/29] arm_mpam: Allow configuration to be applied and restored during cpu online Date: Wed, 10 Sep 2025 20:43:00 +0000 Message-Id: <20250910204309.20751-21-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When CPUs come online the MSC's original configuration should be restored. Add struct mpam_config to hold the configuration. This has a bitmap of features that were modified. Once the maximum partid is known, allocate a configuration array for each component, and reprogram each RIS configuration from this. CC: Dave Martin Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- Changes since v1: * Switched entry_rcu to srcu versions. Changes since RFC: * Added a comment about the ordering around max_partid. * Allocate configurations after interrupts are registered to reduce churn. * Added mpam_assert_partid_sizes_fixed(); * Make reset use an all-ones instead of zero config. --- drivers/resctrl/mpam_devices.c | 269 +++++++++++++++++++++++++++++--- drivers/resctrl/mpam_internal.h | 29 +++- 2 files changed, 271 insertions(+), 27 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index ec1db5f8b05c..7fd149109c75 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -114,6 +114,16 @@ static LLIST_HEAD(mpam_garbage); /* When mpam is disabled, the printed reason to aid debugging */ static char *mpam_disable_reason; =20 +/* + * Once mpam is enabled, new requestors cannot further reduce the available + * partid. Assert that the size is fixed, and new requestors will be turned + * away. + */ +static void mpam_assert_partid_sizes_fixed(void) +{ + WARN_ON_ONCE(!partid_max_published); +} + static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg) { WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); @@ -363,12 +373,16 @@ static void mpam_class_destroy(struct mpam_class *cla= ss) add_to_garbage(class); } =20 +static void __destroy_component_cfg(struct mpam_component *comp); + static void mpam_comp_destroy(struct mpam_component *comp) { struct mpam_class *class =3D comp->class; =20 lockdep_assert_held(&mpam_list_lock); =20 + __destroy_component_cfg(comp); + list_del_rcu(&comp->class_list); add_to_garbage(comp); =20 @@ -833,50 +847,105 @@ static void mpam_reset_msc_bitmap(struct mpam_msc *m= sc, u16 reg, u16 wd) __mpam_write_reg(msc, reg, bm); } =20 -static void mpam_reset_ris_partid(struct mpam_msc_ris *ris, u16 partid) +/* Called via IPI. Call while holding an SRCU reference */ +static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid, + struct mpam_config *cfg) { struct mpam_msc *msc =3D ris->vmsc->msc; struct mpam_props *rprops =3D &ris->props; =20 - mpam_assert_srcu_read_lock_held(); - mutex_lock(&msc->part_sel_lock); __mpam_part_sel(ris->ris_idx, partid, msc); =20 - if (mpam_has_feature(mpam_feat_cpor_part, rprops)) - mpam_reset_msc_bitmap(msc, MPAMCFG_CPBM, rprops->cpbm_wd); + if (mpam_has_feature(mpam_feat_cpor_part, rprops) && + mpam_has_feature(mpam_feat_cpor_part, cfg)) { + if (cfg->reset_cpbm) + mpam_reset_msc_bitmap(msc, MPAMCFG_CPBM, + rprops->cpbm_wd); + else + mpam_write_partsel_reg(msc, CPBM, cfg->cpbm); + } =20 - if (mpam_has_feature(mpam_feat_mbw_part, rprops)) - mpam_reset_msc_bitmap(msc, MPAMCFG_MBW_PBM, rprops->mbw_pbm_bits); + if (mpam_has_feature(mpam_feat_mbw_part, rprops) && + mpam_has_feature(mpam_feat_mbw_part, cfg)) { + if (cfg->reset_mbw_pbm) + mpam_reset_msc_bitmap(msc, MPAMCFG_MBW_PBM, + rprops->mbw_pbm_bits); + else + mpam_write_partsel_reg(msc, MBW_PBM, cfg->mbw_pbm); + } =20 - if (mpam_has_feature(mpam_feat_mbw_min, rprops)) + if (mpam_has_feature(mpam_feat_mbw_min, rprops) && + mpam_has_feature(mpam_feat_mbw_min, cfg)) mpam_write_partsel_reg(msc, MBW_MIN, 0); =20 - if (mpam_has_feature(mpam_feat_mbw_max, rprops)) - mpam_write_partsel_reg(msc, MBW_MAX, MPAMCFG_MBW_MAX_MAX); + if (mpam_has_feature(mpam_feat_mbw_max, rprops) && + mpam_has_feature(mpam_feat_mbw_max, cfg)) + mpam_write_partsel_reg(msc, MBW_MAX, cfg->mbw_max); =20 - if (mpam_has_feature(mpam_feat_mbw_prop, rprops)) + if (mpam_has_feature(mpam_feat_mbw_prop, rprops) && + mpam_has_feature(mpam_feat_mbw_prop, cfg)) mpam_write_partsel_reg(msc, MBW_PROP, 0); mutex_unlock(&msc->part_sel_lock); } =20 +struct reprogram_ris { + struct mpam_msc_ris *ris; + struct mpam_config *cfg; +}; + +/* Call with MSC lock held */ +static int mpam_reprogram_ris(void *_arg) +{ + u16 partid, partid_max; + struct reprogram_ris *arg =3D _arg; + struct mpam_msc_ris *ris =3D arg->ris; + struct mpam_config *cfg =3D arg->cfg; + + if (ris->in_reset_state) + return 0; + + spin_lock(&partid_max_lock); + partid_max =3D mpam_partid_max; + spin_unlock(&partid_max_lock); + for (partid =3D 0; partid <=3D partid_max; partid++) + mpam_reprogram_ris_partid(ris, partid, cfg); + + return 0; +} + +static void mpam_init_reset_cfg(struct mpam_config *reset_cfg) +{ + memset(reset_cfg, 0, sizeof(*reset_cfg)); + + reset_cfg->features =3D ~0; + reset_cfg->cpbm =3D ~0; + reset_cfg->mbw_pbm =3D ~0; + reset_cfg->mbw_max =3D MPAMCFG_MBW_MAX_MAX; + + reset_cfg->reset_cpbm =3D true; + reset_cfg->reset_mbw_pbm =3D true; +} + /* * Called via smp_call_on_cpu() to prevent migration, while still being * pre-emptible. */ static int mpam_reset_ris(void *arg) { - u16 partid, partid_max; + struct mpam_config reset_cfg; struct mpam_msc_ris *ris =3D arg; + struct reprogram_ris reprogram_arg; =20 if (ris->in_reset_state) return 0; =20 - spin_lock(&partid_max_lock); - partid_max =3D mpam_partid_max; - spin_unlock(&partid_max_lock); - for (partid =3D 0; partid < partid_max; partid++) - mpam_reset_ris_partid(ris, partid); + mpam_init_reset_cfg(&reset_cfg); + + reprogram_arg.ris =3D ris; + reprogram_arg.cfg =3D &reset_cfg; + + mpam_reprogram_ris(&reprogram_arg); =20 return 0; } @@ -922,6 +991,40 @@ static void mpam_reset_msc(struct mpam_msc *msc, bool = online) } } =20 +static void mpam_reprogram_msc(struct mpam_msc *msc) +{ + u16 partid; + bool reset; + struct mpam_config *cfg; + struct mpam_msc_ris *ris; + + /* + * No lock for mpam_partid_max as partid_max_published has been + * set by mpam_enabled(), so the values can no longer change. + */ + mpam_assert_partid_sizes_fixed(); + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(ris, &msc->ris, msc_list, + srcu_read_lock_held(&mpam_srcu)) { + if (!mpam_is_enabled() && !ris->in_reset_state) { + mpam_touch_msc(msc, &mpam_reset_ris, ris); + ris->in_reset_state =3D true; + continue; + } + + reset =3D true; + for (partid =3D 0; partid <=3D mpam_partid_max; partid++) { + cfg =3D &ris->vmsc->comp->cfg[partid]; + if (cfg->features) + reset =3D false; + + mpam_reprogram_ris_partid(ris, partid, cfg); + } + ris->in_reset_state =3D reset; + } +} + static void _enable_percpu_irq(void *_irq) { int *irq =3D _irq; @@ -944,7 +1047,7 @@ static int mpam_cpu_online(unsigned int cpu) _enable_percpu_irq(&msc->reenable_error_ppi); =20 if (atomic_fetch_inc(&msc->online_refs) =3D=3D 0) - mpam_reset_msc(msc, true); + mpam_reprogram_msc(msc); } srcu_read_unlock(&mpam_srcu, idx); =20 @@ -1577,6 +1680,45 @@ static void mpam_unregister_irqs(void) cpus_read_unlock(); } =20 +static void __destroy_component_cfg(struct mpam_component *comp) +{ + add_to_garbage(comp->cfg); +} + +static int __allocate_component_cfg(struct mpam_component *comp) +{ + mpam_assert_partid_sizes_fixed(); + + if (comp->cfg) + return 0; + + comp->cfg =3D kcalloc(mpam_partid_max + 1, sizeof(*comp->cfg), GFP_KERNEL= ); + if (!comp->cfg) + return -ENOMEM; + init_garbage(comp->cfg); + + return 0; +} + +static int mpam_allocate_config(void) +{ + int err =3D 0; + struct mpam_class *class; + struct mpam_component *comp; + + lockdep_assert_held(&mpam_list_lock); + + list_for_each_entry(class, &mpam_classes, classes_list) { + list_for_each_entry(comp, &class->components, class_list) { + err =3D __allocate_component_cfg(comp); + if (err) + return err; + } + } + + return 0; +} + static void mpam_enable_once(void) { int err; @@ -1596,12 +1738,21 @@ static void mpam_enable_once(void) */ cpus_read_lock(); mutex_lock(&mpam_list_lock); - mpam_enable_merge_features(&mpam_classes); + do { + mpam_enable_merge_features(&mpam_classes); =20 - err =3D mpam_register_irqs(); - if (err) - pr_warn("Failed to register irqs: %d\n", err); + err =3D mpam_register_irqs(); + if (err) { + pr_warn("Failed to register irqs: %d\n", err); + break; + } =20 + err =3D mpam_allocate_config(); + if (err) { + pr_err("Failed to allocate configuration arrays.\n"); + break; + } + } while (0); mutex_unlock(&mpam_list_lock); cpus_read_unlock(); =20 @@ -1624,6 +1775,9 @@ static void mpam_reset_component_locked(struct mpam_c= omponent *comp) struct mpam_msc_ris *ris; =20 lockdep_assert_cpus_held(); + mpam_assert_partid_sizes_fixed(); + + memset(comp->cfg, 0, (mpam_partid_max * sizeof(*comp->cfg))); =20 guard(srcu)(&mpam_srcu); list_for_each_entry_srcu(vmsc, &comp->vmsc, comp_list, @@ -1723,6 +1877,77 @@ void mpam_enable(struct work_struct *work) mpam_enable_once(); } =20 +struct mpam_write_config_arg { + struct mpam_msc_ris *ris; + struct mpam_component *comp; + u16 partid; +}; + +static int __write_config(void *arg) +{ + struct mpam_write_config_arg *c =3D arg; + + mpam_reprogram_ris_partid(c->ris, c->partid, &c->comp->cfg[c->partid]); + + return 0; +} + +#define maybe_update_config(cfg, feature, newcfg, member, changes) do { \ + if (mpam_has_feature(feature, newcfg) && \ + (newcfg)->member !=3D (cfg)->member) { \ + (cfg)->member =3D (newcfg)->member; \ + cfg->features |=3D (1 << feature); \ + \ + (changes) |=3D (1 << feature); \ + } \ +} while (0) + +static mpam_features_t mpam_update_config(struct mpam_config *cfg, + const struct mpam_config *newcfg) +{ + mpam_features_t changes =3D 0; + + maybe_update_config(cfg, mpam_feat_cpor_part, newcfg, cpbm, changes); + maybe_update_config(cfg, mpam_feat_mbw_part, newcfg, mbw_pbm, changes); + maybe_update_config(cfg, mpam_feat_mbw_max, newcfg, mbw_max, changes); + + return changes; +} + +int mpam_apply_config(struct mpam_component *comp, u16 partid, + struct mpam_config *cfg) +{ + struct mpam_write_config_arg arg; + struct mpam_msc_ris *ris; + struct mpam_vmsc *vmsc; + struct mpam_msc *msc; + + lockdep_assert_cpus_held(); + + /* Don't pass in the current config! */ + WARN_ON_ONCE(&comp->cfg[partid] =3D=3D cfg); + + if (!mpam_update_config(&comp->cfg[partid], cfg)) + return 0; + + arg.comp =3D comp; + arg.partid =3D partid; + + guard(srcu)(&mpam_srcu); + list_for_each_entry_srcu(vmsc, &comp->vmsc, comp_list, + srcu_read_lock_held(&mpam_srcu)) { + msc =3D vmsc->msc; + + list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list, + srcu_read_lock_held(&mpam_srcu)) { + arg.ris =3D ris; + mpam_touch_msc(msc, __write_config, &arg); + } + } + + return 0; +} + static int __init mpam_msc_driver_init(void) { if (!system_supports_mpam()) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index b69fa9199cb4..17570d9aae9b 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -169,11 +169,7 @@ struct mpam_props { u16 num_mbwu_mon; }; =20 -static inline bool mpam_has_feature(enum mpam_device_features feat, - struct mpam_props *props) -{ - return (1 << feat) & props->features; -} +#define mpam_has_feature(_feat, x) ((1 << (_feat)) & (x)->features) =20 static inline void mpam_set_feature(enum mpam_device_features feat, struct mpam_props *props) @@ -204,6 +200,20 @@ struct mpam_class { struct mpam_garbage garbage; }; =20 +struct mpam_config { + /* Which configuration values are valid. */ + mpam_features_t features; + + u32 cpbm; + u32 mbw_pbm; + u16 mbw_max; + + bool reset_cpbm; + bool reset_mbw_pbm; + + struct mpam_garbage garbage; +}; + struct mpam_component { u32 comp_id; =20 @@ -212,6 +222,12 @@ struct mpam_component { =20 cpumask_t affinity; =20 + /* + * Array of configuration values, indexed by partid. + * Read from cpuhp callbacks, hold the cpuhp lock when writing. + */ + struct mpam_config *cfg; + /* member of mpam_class:components */ struct list_head class_list; =20 @@ -276,6 +292,9 @@ extern u8 mpam_pmg_max; void mpam_enable(struct work_struct *work); void mpam_disable(struct work_struct *work); =20 +int mpam_apply_config(struct mpam_component *comp, u16 partid, + struct mpam_config *cfg); + int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D0BBF340DA7; Wed, 10 Sep 2025 20:45:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537119; cv=none; b=fbmmIw5XQc3Lu9gfD+PA+/kTfSkFztN39LV0WMwV8X9BIid4B1cZgunLm4441IldxLIeEOEYEq3g9AD6FLy9y7XLzhaL0l3tLfrXpvrHcPY6YNN21Tjexv+HKbppPbbFANhI+81+YrA8qBfrK12oG93bbHgjAlwlh/PUM9ebMpk= ARC-Message-Signature: i=1; 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Wed, 10 Sep 2025 13:45:10 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Rohit Mathew , Zeng Heng , Dave Martin Subject: [PATCH v2 21/29] arm_mpam: Probe and reset the rest of the features Date: Wed, 10 Sep 2025 20:43:01 +0000 Message-Id: <20250910204309.20751-22-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPAM supports more features than are going to be exposed to resctrl. For partid other than 0, the reset values of these controls isn't known. Discover the rest of the features so they can be reset to avoid any side effects when resctrl is in use. PARTID narrowing allows MSC/RIS to support less configuration space than is usable. If this feature is found on a class of device we are likely to use, then reduce the partid_max to make it usable. This allows us to map a PARTID to itself. CC: Rohit Mathew CC: Zeng Heng CC: Dave Martin Signed-off-by: James Morse Reviewed-by: Jonathan Cameron --- Changes since v1: * Added reset for cassoc. * Added detection of CSU XCL. --- drivers/resctrl/mpam_devices.c | 181 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 17 ++- 2 files changed, 196 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 7fd149109c75..f536ebbcf94e 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -214,6 +214,15 @@ static void __mpam_part_sel(u8 ris_idx, u16 partid, st= ruct mpam_msc *msc) __mpam_part_sel_raw(partsel, msc); } =20 +static void __mpam_intpart_sel(u8 ris_idx, u16 intpartid, struct mpam_msc = *msc) +{ + u32 partsel =3D FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) | + FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, intpartid) | + MPAMCFG_PART_SEL_INTERNAL; + + __mpam_part_sel_raw(partsel, msc); +} + int mpam_register_requestor(u16 partid_max, u8 pmg_max) { int err =3D 0; @@ -667,10 +676,35 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ri= s) struct mpam_msc *msc =3D ris->vmsc->msc; struct device *dev =3D &msc->pdev->dev; struct mpam_props *props =3D &ris->props; + struct mpam_class *class =3D ris->vmsc->comp->class; =20 lockdep_assert_held(&msc->probe_lock); lockdep_assert_held(&msc->part_sel_lock); =20 + /* Cache Capacity Partitioning */ + if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) { + u32 ccap_features =3D mpam_read_partsel_reg(msc, CCAP_IDR); + + props->cmax_wd =3D FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features); + if (props->cmax_wd && + FIELD_GET(MPAMF_CCAP_IDR_HAS_CMAX_SOFTLIM, ccap_features)) + mpam_set_feature(mpam_feat_cmax_softlim, props); + + if (props->cmax_wd && + !FIELD_GET(MPAMF_CCAP_IDR_NO_CMAX, ccap_features)) + mpam_set_feature(mpam_feat_cmax_cmax, props); + + if (props->cmax_wd && + FIELD_GET(MPAMF_CCAP_IDR_HAS_CMIN, ccap_features)) + mpam_set_feature(mpam_feat_cmax_cmin, props); + + props->cassoc_wd =3D FIELD_GET(MPAMF_CCAP_IDR_CASSOC_WD, ccap_features); + + if (props->cassoc_wd && + FIELD_GET(MPAMF_CCAP_IDR_HAS_CASSOC, ccap_features)) + mpam_set_feature(mpam_feat_cmax_cassoc, props); + } + /* Cache Portion partitioning */ if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) { u32 cpor_features =3D mpam_read_partsel_reg(msc, CPOR_IDR); @@ -693,6 +727,31 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) props->bwa_wd =3D FIELD_GET(MPAMF_MBW_IDR_BWA_WD, mbw_features); if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MAX, mbw_features)) mpam_set_feature(mpam_feat_mbw_max, props); + + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_MIN, mbw_features)) + mpam_set_feature(mpam_feat_mbw_min, props); + + if (props->bwa_wd && FIELD_GET(MPAMF_MBW_IDR_HAS_PROP, mbw_features)) + mpam_set_feature(mpam_feat_mbw_prop, props); + } + + /* Priority partitioning */ + if (FIELD_GET(MPAMF_IDR_HAS_PRI_PART, ris->idr)) { + u32 pri_features =3D mpam_read_partsel_reg(msc, PRI_IDR); + + props->intpri_wd =3D FIELD_GET(MPAMF_PRI_IDR_INTPRI_WD, pri_features); + if (props->intpri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_INTPRI, pri_features= )) { + mpam_set_feature(mpam_feat_intpri_part, props); + if (FIELD_GET(MPAMF_PRI_IDR_INTPRI_0_IS_LOW, pri_features)) + mpam_set_feature(mpam_feat_intpri_part_0_low, props); + } + + props->dspri_wd =3D FIELD_GET(MPAMF_PRI_IDR_DSPRI_WD, pri_features); + if (props->dspri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_DSPRI, pri_features))= { + mpam_set_feature(mpam_feat_dspri_part, props); + if (FIELD_GET(MPAMF_PRI_IDR_DSPRI_0_IS_LOW, pri_features)) + mpam_set_feature(mpam_feat_dspri_part_0_low, props); + } } =20 /* Performance Monitoring */ @@ -717,6 +776,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) =20 mpam_set_feature(mpam_feat_msmon_csu, props); =20 + if (FIELD_GET(MPAMF_CSUMON_IDR_HAS_XCL, csumonidr)) + mpam_set_feature(mpam_feat_msmon_csu_xcl, props); + /* Is NRDY hardware managed? */ hw_managed =3D mpam_ris_hw_probe_hw_nrdy(ris, CSU); if (hw_managed) @@ -752,6 +814,21 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) */ } } + + /* + * RIS with PARTID narrowing don't have enough storage for one + * configuration per PARTID. If these are in a class we could use, + * reduce the supported partid_max to match the number of intpartid. + * If the class is unknown, just ignore it. + */ + if (FIELD_GET(MPAMF_IDR_HAS_PARTID_NRW, ris->idr) && + class->type !=3D MPAM_CLASS_UNKNOWN) { + u32 nrwidr =3D mpam_read_partsel_reg(msc, PARTID_NRW_IDR); + u16 partid_max =3D FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr); + + mpam_set_feature(mpam_feat_partid_nrw, props); + msc->partid_max =3D min(msc->partid_max, partid_max); + } } =20 static int mpam_msc_hw_probe(struct mpam_msc *msc) @@ -851,12 +928,28 @@ static void mpam_reset_msc_bitmap(struct mpam_msc *ms= c, u16 reg, u16 wd) static void mpam_reprogram_ris_partid(struct mpam_msc_ris *ris, u16 partid, struct mpam_config *cfg) { + u32 pri_val =3D 0; + u16 cmax =3D MPAMCFG_CMAX_CMAX; struct mpam_msc *msc =3D ris->vmsc->msc; struct mpam_props *rprops =3D &ris->props; + u16 dspri =3D GENMASK(rprops->dspri_wd, 0); + u16 intpri =3D GENMASK(rprops->intpri_wd, 0); =20 mutex_lock(&msc->part_sel_lock); __mpam_part_sel(ris->ris_idx, partid, msc); =20 + if (mpam_has_feature(mpam_feat_partid_nrw, rprops)) { + /* Update the intpartid mapping */ + mpam_write_partsel_reg(msc, INTPARTID, + MPAMCFG_INTPARTID_INTERNAL | partid); + + /* + * Then switch to the 'internal' partid to update the + * configuration. + */ + __mpam_intpart_sel(ris->ris_idx, partid, msc); + } + if (mpam_has_feature(mpam_feat_cpor_part, rprops) && mpam_has_feature(mpam_feat_cpor_part, cfg)) { if (cfg->reset_cpbm) @@ -886,6 +979,32 @@ static void mpam_reprogram_ris_partid(struct mpam_msc_= ris *ris, u16 partid, if (mpam_has_feature(mpam_feat_mbw_prop, rprops) && mpam_has_feature(mpam_feat_mbw_prop, cfg)) mpam_write_partsel_reg(msc, MBW_PROP, 0); + + if (mpam_has_feature(mpam_feat_cmax_cmax, rprops)) + mpam_write_partsel_reg(msc, CMAX, cmax); + + if (mpam_has_feature(mpam_feat_cmax_cmin, rprops)) + mpam_write_partsel_reg(msc, CMIN, 0); + + if (mpam_has_feature(mpam_feat_cmax_cassoc, rprops)) + mpam_write_partsel_reg(msc, CASSOC, MPAMCFG_CASSOC_CASSOC); + + if (mpam_has_feature(mpam_feat_intpri_part, rprops) || + mpam_has_feature(mpam_feat_dspri_part, rprops)) { + /* aces high? */ + if (!mpam_has_feature(mpam_feat_intpri_part_0_low, rprops)) + intpri =3D 0; + if (!mpam_has_feature(mpam_feat_dspri_part_0_low, rprops)) + dspri =3D 0; + + if (mpam_has_feature(mpam_feat_intpri_part, rprops)) + pri_val |=3D FIELD_PREP(MPAMCFG_PRI_INTPRI, intpri); + if (mpam_has_feature(mpam_feat_dspri_part, rprops)) + pri_val |=3D FIELD_PREP(MPAMCFG_PRI_DSPRI, dspri); + + mpam_write_partsel_reg(msc, PRI, pri_val); + } + mutex_unlock(&msc->part_sel_lock); } =20 @@ -1314,6 +1433,16 @@ static bool mpam_has_bwa_wd_feature(struct mpam_prop= s *props) return false; } =20 +/* Any of these features mean the CMAX_WD field is valid. */ +static bool mpam_has_cmax_wd_feature(struct mpam_props *props) +{ + if (mpam_has_feature(mpam_feat_cmax_cmax, props)) + return true; + if (mpam_has_feature(mpam_feat_cmax_cmin, props)) + return true; + return false; +} + #define MISMATCHED_HELPER(parent, child, helper, field, alias) \ helper(parent) && \ ((helper(child) && (parent)->field !=3D (child)->field) || \ @@ -1368,6 +1497,23 @@ static void __props_mismatch(struct mpam_props *pare= nt, parent->bwa_wd =3D min(parent->bwa_wd, child->bwa_wd); } =20 + if (alias && !mpam_has_cmax_wd_feature(parent) && mpam_has_cmax_wd_featur= e(child)) { + parent->cmax_wd =3D child->cmax_wd; + } else if (MISMATCHED_HELPER(parent, child, mpam_has_cmax_wd_feature, + cmax_wd, alias)) { + pr_debug("%s took the min cmax_wd\n", __func__); + parent->cmax_wd =3D min(parent->cmax_wd, child->cmax_wd); + } + + if (CAN_MERGE_FEAT(parent, child, mpam_feat_cmax_cassoc, alias)) { + parent->cassoc_wd =3D child->cassoc_wd; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_cmax_cassoc, + cassoc_wd, alias)) { + pr_debug("%s cleared cassoc_wd\n", __func__); + mpam_clear_feature(mpam_feat_cmax_cassoc, &parent->features); + parent->cassoc_wd =3D 0; + } + /* For num properties, take the minimum */ if (CAN_MERGE_FEAT(parent, child, mpam_feat_msmon_csu, alias)) { parent->num_csu_mon =3D child->num_csu_mon; @@ -1385,6 +1531,41 @@ static void __props_mismatch(struct mpam_props *pare= nt, parent->num_mbwu_mon =3D min(parent->num_mbwu_mon, child->num_mbwu_mon); } =20 + if (CAN_MERGE_FEAT(parent, child, mpam_feat_intpri_part, alias)) { + parent->intpri_wd =3D child->intpri_wd; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_intpri_part, + intpri_wd, alias)) { + pr_debug("%s took the min intpri_wd\n", __func__); + parent->intpri_wd =3D min(parent->intpri_wd, child->intpri_wd); + } + + if (CAN_MERGE_FEAT(parent, child, mpam_feat_dspri_part, alias)) { + parent->dspri_wd =3D child->dspri_wd; + } else if (MISMATCHED_FEAT(parent, child, mpam_feat_dspri_part, + dspri_wd, alias)) { + pr_debug("%s took the min dspri_wd\n", __func__); + parent->dspri_wd =3D min(parent->dspri_wd, child->dspri_wd); + } + + /* TODO: alias support for these two */ + /* {int,ds}pri may not have differing 0-low behaviour */ + if (mpam_has_feature(mpam_feat_intpri_part, parent) && + (!mpam_has_feature(mpam_feat_intpri_part, child) || + mpam_has_feature(mpam_feat_intpri_part_0_low, parent) !=3D + mpam_has_feature(mpam_feat_intpri_part_0_low, child))) { + pr_debug("%s cleared intpri_part\n", __func__); + mpam_clear_feature(mpam_feat_intpri_part, &parent->features); + mpam_clear_feature(mpam_feat_intpri_part_0_low, &parent->features); + } + if (mpam_has_feature(mpam_feat_dspri_part, parent) && + (!mpam_has_feature(mpam_feat_dspri_part, child) || + mpam_has_feature(mpam_feat_dspri_part_0_low, parent) !=3D + mpam_has_feature(mpam_feat_dspri_part_0_low, child))) { + pr_debug("%s cleared dspri_part\n", __func__); + mpam_clear_feature(mpam_feat_dspri_part, &parent->features); + mpam_clear_feature(mpam_feat_dspri_part_0_low, &parent->features); + } + if (alias) { /* Merge features for aliased resources */ parent->features |=3D child->features; diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 17570d9aae9b..326ba9114d70 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -136,25 +136,34 @@ static inline void mpam_mon_sel_lock_init(struct mpam= _msc *msc) * When we compact the supported features, we don't care what they are. * Storing them as a bitmap makes life easy. */ -typedef u16 mpam_features_t; +typedef u32 mpam_features_t; =20 /* Bits for mpam_features_t */ enum mpam_device_features { - mpam_feat_ccap_part =3D 0, + mpam_feat_cmax_softlim, + mpam_feat_cmax_cmax, + mpam_feat_cmax_cmin, + mpam_feat_cmax_cassoc, mpam_feat_cpor_part, mpam_feat_mbw_part, mpam_feat_mbw_min, mpam_feat_mbw_max, mpam_feat_mbw_prop, + mpam_feat_intpri_part, + mpam_feat_intpri_part_0_low, + mpam_feat_dspri_part, + mpam_feat_dspri_part_0_low, mpam_feat_msmon, mpam_feat_msmon_csu, mpam_feat_msmon_csu_capture, + mpam_feat_msmon_csu_xcl, mpam_feat_msmon_csu_hw_nrdy, mpam_feat_msmon_mbwu, mpam_feat_msmon_mbwu_capture, mpam_feat_msmon_mbwu_rwbw, mpam_feat_msmon_mbwu_hw_nrdy, mpam_feat_msmon_capt, + mpam_feat_partid_nrw, MPAM_FEATURE_LAST, }; static_assert(BITS_PER_TYPE(mpam_features_t) >=3D MPAM_FEATURE_LAST); @@ -165,6 +174,10 @@ struct mpam_props { u16 cpbm_wd; u16 mbw_pbm_bits; u16 bwa_wd; + u16 cmax_wd; + u16 cassoc_wd; + u16 intpri_wd; + u16 dspri_wd; u16 num_csu_mon; u16 num_mbwu_mon; }; --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E7D37341AA9; Wed, 10 Sep 2025 20:45:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537123; cv=none; b=uzD3wSpUcGDLP6erd4ISbTFY1211mzgBU1lVHl+0Yo7KYiHQfqn+kLx5iIT3YRKW0XVh1DCI3A8ANRQDG6qY4Oo5iK17kCh9PcIpF+7HgAdS6z66xBffutN9+olPUcd57k44aulCABiL2mfLYj2fzAxjPbZnLdNh50MqGfpe5T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537123; c=relaxed/simple; bh=NYxyUURKHS7//bwml/NqGTPmVOVzvVFJiIDjuvOd/Ng=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ELUmllRnuFxuuiMO3h9B4ATkxyv+RjxmBPTNjPgVHLWrZ8VU5VqoZzck0dmhpKv2UTP3IRiJcaQRkYCT7GjRA1eZmLfYsEQDmXmFkpGGG6llyDk5SdgQQWA9boo5M2DOBcjwJvEhWQ+XoROZGt1yl5Rchps+ur6CjbmPDgn3B5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E2ECB1EDB; Wed, 10 Sep 2025 13:45:12 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7869D3F63F; Wed, 10 Sep 2025 13:45:16 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 22/29] arm_mpam: Add helpers to allocate monitors Date: Wed, 10 Sep 2025 20:43:02 +0000 Message-Id: <20250910204309.20751-23-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MPAM's MSC support a number of monitors, each of which supports bandwidth counters, or cache-storage-utilisation counters. To use a counter, a monitor needs to be configured. Add helpers to allocate and free CSU or MBWU monitors. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Jonathan Cameron --- drivers/resctrl/mpam_devices.c | 2 ++ drivers/resctrl/mpam_internal.h | 35 +++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index f536ebbcf94e..cf190f896de1 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -340,6 +340,8 @@ mpam_class_alloc(u8 level_idx, enum mpam_class_types ty= pe) class->level =3D level_idx; class->type =3D type; INIT_LIST_HEAD_RCU(&class->classes_list); + ida_init(&class->ida_csu_mon); + ida_init(&class->ida_mbwu_mon); =20 list_add_rcu(&class->classes_list, &mpam_classes); =20 diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 326ba9114d70..81c4c2bfea3d 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -210,6 +210,9 @@ struct mpam_class { /* member of mpam_classes */ struct list_head classes_list; =20 + struct ida ida_csu_mon; + struct ida ida_mbwu_mon; + struct mpam_garbage garbage; }; =20 @@ -288,6 +291,38 @@ struct mpam_msc_ris { struct mpam_garbage garbage; }; =20 +static inline int mpam_alloc_csu_mon(struct mpam_class *class) +{ + struct mpam_props *cprops =3D &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_csu, cprops)) + return -EOPNOTSUPP; + + return ida_alloc_range(&class->ida_csu_mon, 0, cprops->num_csu_mon - 1, + GFP_KERNEL); +} + +static inline void mpam_free_csu_mon(struct mpam_class *class, int csu_mon) +{ + ida_free(&class->ida_csu_mon, csu_mon); +} + +static inline int mpam_alloc_mbwu_mon(struct mpam_class *class) +{ + struct mpam_props *cprops =3D &class->props; + + if (!mpam_has_feature(mpam_feat_msmon_mbwu, cprops)) + return -EOPNOTSUPP; + + return ida_alloc_range(&class->ida_mbwu_mon, 0, + cprops->num_mbwu_mon - 1, GFP_KERNEL); +} + +static inline void mpam_free_mbwu_mon(struct mpam_class *class, int mbwu_m= on) +{ + ida_free(&class->ida_mbwu_mon, mbwu_mon); +} + /* List of all classes - protected by srcu*/ extern struct srcu_struct mpam_srcu; extern struct list_head mpam_classes; --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9032F3431FD; Wed, 10 Sep 2025 20:45:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537128; cv=none; b=fHr7N2pQVz/Jc4Pi5tDNHqxkPSDuth49/dQUsVikceB8eOINGjaeLWLPXeSEWbeeCda9GP83JovUQs2WPfz7j43nqakXljh+rdQqBZv2NKuomJpchk6xbU77nQJJkdW+2b+a018NQcbeSgvB4RXbCONOa90+Jyw3xxzwBOQqPeU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537128; c=relaxed/simple; bh=gsT0NWtXQpW/FfAfzYUCCHhshRNXgLIz3ZHWDoWC2zQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ba/YMm8b6Gti1/9ldR4D0/p+uX9Ocatn+XOz0joxvr7U5/IrQOPlHsVarwuw/68Pa3R12lTZdXm55QOVvB2rHkLDWBTz8XKGh3VygBh4QskcB7DW9EkA4yEmT7xkSsfKFaeTw04BslwZSd3DOYg632s/r5jEP8owtU45d6s0SRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E16AD244B; Wed, 10 Sep 2025 13:45:17 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 97F1D3F63F; Wed, 10 Sep 2025 13:45:21 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 23/29] arm_mpam: Add mpam_msmon_read() to read monitor value Date: Wed, 10 Sep 2025 20:43:03 +0000 Message-Id: <20250910204309.20751-24-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reading a monitor involves configuring what you want to monitor, and reading the value. Components made up of multiple MSC may need values from each MSC. MSCs may take time to configure, returning 'not ready'. The maximum 'not ready' time should have been provided by firmware. Add mpam_msmon_read() to hide all this. If (one of) the MSC returns not ready, then wait the full timeout value before trying again. CC: Shanker Donthineni Signed-off-by: James Morse --- Changes since v1: * Added XCL support. * Merged FLT/CTL constants. * a spelling mistake in a comment. * moved structrues around. --- drivers/resctrl/mpam_devices.c | 226 ++++++++++++++++++++++++++++++++ drivers/resctrl/mpam_internal.h | 19 +++ 2 files changed, 245 insertions(+) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index cf190f896de1..1543c33c5d6a 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -898,6 +898,232 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) return 0; } =20 +struct mon_read { + struct mpam_msc_ris *ris; + struct mon_cfg *ctx; + enum mpam_device_features type; + u64 *val; + int err; +}; + +static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, + u32 *flt_val) +{ + struct mon_cfg *ctx =3D m->ctx; + + /* + * For CSU counters its implementation-defined what happens when not + * filtering by partid. + */ + *ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PARTID; + + *flt_val =3D FIELD_PREP(MSMON_CFG_x_FLT_PARTID, ctx->partid); + if (m->ctx->match_pmg) { + *ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PMG; + *flt_val |=3D FIELD_PREP(MSMON_CFG_x_FLT_PMG, ctx->pmg); + } + + switch (m->type) { + case mpam_feat_msmon_csu: + *ctl_val =3D MSMON_CFG_CSU_CTL_TYPE_CSU; + + if (mpam_has_feature(mpam_feat_msmon_csu_xcl, &m->ris->props)) + *flt_val |=3D FIELD_PREP(MSMON_CFG_CSU_FLT_XCL, + ctx->csu_exclude_clean); + + break; + case mpam_feat_msmon_mbwu: + *ctl_val =3D MSMON_CFG_MBWU_CTL_TYPE_MBWU; + + if (mpam_has_feature(mpam_feat_msmon_mbwu_rwbw, &m->ris->props)) + *flt_val |=3D FIELD_PREP(MSMON_CFG_MBWU_FLT_RWBW, ctx->opts); + + break; + default: + return; + } +} + +static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, + u32 *flt_val) +{ + struct mpam_msc *msc =3D m->ris->vmsc->msc; + + switch (m->type) { + case mpam_feat_msmon_csu: + *ctl_val =3D mpam_read_monsel_reg(msc, CFG_CSU_CTL); + *flt_val =3D mpam_read_monsel_reg(msc, CFG_CSU_FLT); + break; + case mpam_feat_msmon_mbwu: + *ctl_val =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); + *flt_val =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); + break; + default: + return; + } +} + +/* Remove values set by the hardware to prevent apparent mismatches. */ +static void clean_msmon_ctl_val(u32 *cur_ctl) +{ + *cur_ctl &=3D ~MSMON_CFG_x_CTL_OFLOW_STATUS; +} + +static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val, + u32 flt_val) +{ + struct mpam_msc *msc =3D m->ris->vmsc->msc; + + /* + * Write the ctl_val with the enable bit cleared, reset the counter, + * then enable counter. + */ + switch (m->type) { + case mpam_feat_msmon_csu: + mpam_write_monsel_reg(msc, CFG_CSU_FLT, flt_val); + mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val); + mpam_write_monsel_reg(msc, CSU, 0); + mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); + break; + case mpam_feat_msmon_mbwu: + mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val); + mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); + mpam_write_monsel_reg(msc, MBWU, 0); + mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); + break; + default: + return; + } +} + +/* Call with MSC lock held */ +static void __ris_msmon_read(void *arg) +{ + u64 now; + bool nrdy =3D false; + struct mon_read *m =3D arg; + struct mon_cfg *ctx =3D m->ctx; + struct mpam_msc_ris *ris =3D m->ris; + struct mpam_props *rprops =3D &ris->props; + struct mpam_msc *msc =3D m->ris->vmsc->msc; + u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; + + if (!mpam_mon_sel_lock(msc)) { + m->err =3D -EIO; + return; + } + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) | + FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); + mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + + /* + * Read the existing configuration to avoid re-writing the same values. + * This saves waiting for 'nrdy' on subsequent reads. + */ + read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt); + clean_msmon_ctl_val(&cur_ctl); + gen_msmon_ctl_flt_vals(m, &ctl_val, &flt_val); + if (cur_flt !=3D flt_val || cur_ctl !=3D (ctl_val | MSMON_CFG_x_CTL_EN)) + write_msmon_ctl_flt_vals(m, ctl_val, flt_val); + + switch (m->type) { + case mpam_feat_msmon_csu: + now =3D mpam_read_monsel_reg(msc, CSU); + if (mpam_has_feature(mpam_feat_msmon_csu_hw_nrdy, rprops)) + nrdy =3D now & MSMON___NRDY; + break; + case mpam_feat_msmon_mbwu: + now =3D mpam_read_monsel_reg(msc, MBWU); + if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops)) + nrdy =3D now & MSMON___NRDY; + break; + default: + m->err =3D -EINVAL; + break; + } + mpam_mon_sel_unlock(msc); + + if (nrdy) { + m->err =3D -EBUSY; + return; + } + + now =3D FIELD_GET(MSMON___VALUE, now); + *m->val +=3D now; +} + +static int _msmon_read(struct mpam_component *comp, struct mon_read *arg) +{ + int err, idx; + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_rcu(vmsc, &comp->vmsc, comp_list) { + msc =3D vmsc->msc; + + list_for_each_entry_rcu(ris, &vmsc->ris, vmsc_list) { + arg->ris =3D ris; + + err =3D smp_call_function_any(&msc->accessibility, + __ris_msmon_read, arg, + true); + if (!err && arg->err) + err =3D arg->err; + if (err) + break; + } + if (err) + break; + } + srcu_read_unlock(&mpam_srcu, idx); + + return err; +} + +int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, + enum mpam_device_features type, u64 *val) +{ + int err; + struct mon_read arg; + u64 wait_jiffies =3D 0; + struct mpam_props *cprops =3D &comp->class->props; + + might_sleep(); + + if (!mpam_is_enabled()) + return -EIO; + + if (!mpam_has_feature(type, cprops)) + return -EOPNOTSUPP; + + memset(&arg, 0, sizeof(arg)); + arg.ctx =3D ctx; + arg.type =3D type; + arg.val =3D val; + *val =3D 0; + + err =3D _msmon_read(comp, &arg); + if (err =3D=3D -EBUSY && comp->class->nrdy_usec) + wait_jiffies =3D usecs_to_jiffies(comp->class->nrdy_usec); + + while (wait_jiffies) + wait_jiffies =3D schedule_timeout_uninterruptible(wait_jiffies); + + if (err =3D=3D -EBUSY) { + memset(&arg, 0, sizeof(arg)); + arg.ctx =3D ctx; + arg.type =3D type; + arg.val =3D val; + *val =3D 0; + + err =3D _msmon_read(comp, &arg); + } + + return err; +} + static void mpam_reset_msc_bitmap(struct mpam_msc *msc, u16 reg, u16 wd) { u32 num_words, msb; diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 81c4c2bfea3d..bb01e7dbde40 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -196,6 +196,22 @@ static inline void mpam_clear_feature(enum mpam_device= _features feat, *supported &=3D ~(1 << feat); } =20 +/* The values for MSMON_CFG_MBWU_FLT.RWBW */ +enum mon_filter_options { + COUNT_BOTH =3D 0, + COUNT_WRITE =3D 1, + COUNT_READ =3D 2, +}; + +struct mon_cfg { + u16 mon; + u8 pmg; + bool match_pmg; + bool csu_exclude_clean; + u32 partid; + enum mon_filter_options opts; +}; + struct mpam_class { /* mpam_components in this class */ struct list_head components; @@ -343,6 +359,9 @@ void mpam_disable(struct work_struct *work); int mpam_apply_config(struct mpam_component *comp, u16 partid, struct mpam_config *cfg); =20 +int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, + enum mpam_device_features, u64 *val); + int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B55AB2FF650; Wed, 10 Sep 2025 20:45:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537133; cv=none; b=lbHf2kCzxdW0Ldjh8QY8E+Df+T2lv04Hl/6HcboEmEnFLOhCQbn66x1Qlr/VvaPv2EGk7B4OprqNgAyQDRDCjT4kmHUcwScntqrTHu7hj3DsrgEYvNtvxwKxBJhxEz6nirjTZK2oAiemgOkKFYBmMENJxPKwA3id4aNd4CEUa2M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537133; c=relaxed/simple; bh=AMXjaVjTgLXeAiE8mxSQR9KTUbQ7Jtu3Ju7snV+WGWE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gwSiLKdHosogt42QYSUMahy74c3RV5ugF/BM/W6YFjhVSr0nXX512U3ExvFLR0oWeLrcjrzAFT1sCe4TLfc/sUEzeZo/FwziO67gv1+XA8shFojXCEVAJ+RgsuF5nYGvRQYGD80Uce3hQXnZa99CPuiGy7/e8KKS/RU6JYnJG7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 041C422EA; Wed, 10 Sep 2025 13:45:23 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AFDBC3F63F; Wed, 10 Sep 2025 13:45:26 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 24/29] arm_mpam: Track bandwidth counter state for overflow and power management Date: Wed, 10 Sep 2025 20:43:04 +0000 Message-Id: <20250910204309.20751-25-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Bandwidth counters need to run continuously to correctly reflect the bandwidth. The value read may be lower than the previous value read in the case of overflow and when the hardware is reset due to CPU hotplug. Add struct mbwu_state to track the bandwidth counter to allow overflow and power management to be handled. Signed-off-by: James Morse --- Changes since v1: * Fixed lock/unlock typo. --- drivers/resctrl/mpam_devices.c | 154 +++++++++++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 23 +++++ 2 files changed, 175 insertions(+), 2 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 1543c33c5d6a..eeb62ed94520 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -918,6 +918,7 @@ static void gen_msmon_ctl_flt_vals(struct mon_read *m, = u32 *ctl_val, *ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PARTID; =20 *flt_val =3D FIELD_PREP(MSMON_CFG_x_FLT_PARTID, ctx->partid); + if (m->ctx->match_pmg) { *ctl_val |=3D MSMON_CFG_x_CTL_MATCH_PMG; *flt_val |=3D FIELD_PREP(MSMON_CFG_x_FLT_PMG, ctx->pmg); @@ -972,6 +973,7 @@ static void clean_msmon_ctl_val(u32 *cur_ctl) static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val, u32 flt_val) { + struct msmon_mbwu_state *mbwu_state; struct mpam_msc *msc =3D m->ris->vmsc->msc; =20 /* @@ -990,20 +992,32 @@ static void write_msmon_ctl_flt_vals(struct mon_read = *m, u32 ctl_val, mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); mpam_write_monsel_reg(msc, MBWU, 0); mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); + + mbwu_state =3D &m->ris->mbwu_state[m->ctx->mon]; + if (mbwu_state) + mbwu_state->prev_val =3D 0; + break; default: return; } } =20 +static u64 mpam_msmon_overflow_val(struct mpam_msc_ris *ris) +{ + /* TODO: scaling, and long counters */ + return GENMASK_ULL(30, 0); +} + /* Call with MSC lock held */ static void __ris_msmon_read(void *arg) { - u64 now; bool nrdy =3D false; struct mon_read *m =3D arg; + u64 now, overflow_val =3D 0; struct mon_cfg *ctx =3D m->ctx; struct mpam_msc_ris *ris =3D m->ris; + struct msmon_mbwu_state *mbwu_state; struct mpam_props *rprops =3D &ris->props; struct mpam_msc *msc =3D m->ris->vmsc->msc; u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt; @@ -1031,11 +1045,30 @@ static void __ris_msmon_read(void *arg) now =3D mpam_read_monsel_reg(msc, CSU); if (mpam_has_feature(mpam_feat_msmon_csu_hw_nrdy, rprops)) nrdy =3D now & MSMON___NRDY; + now =3D FIELD_GET(MSMON___VALUE, now); break; case mpam_feat_msmon_mbwu: now =3D mpam_read_monsel_reg(msc, MBWU); if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops)) nrdy =3D now & MSMON___NRDY; + now =3D FIELD_GET(MSMON___VALUE, now); + + if (nrdy) + break; + + mbwu_state =3D &ris->mbwu_state[ctx->mon]; + if (!mbwu_state) + break; + + /* Add any pre-overflow value to the mbwu_state->val */ + if (mbwu_state->prev_val > now) + overflow_val =3D mpam_msmon_overflow_val(ris) - mbwu_state->prev_val; + + mbwu_state->prev_val =3D now; + mbwu_state->correction +=3D overflow_val; + + /* Include bandwidth consumed before the last hardware reset */ + now +=3D mbwu_state->correction; break; default: m->err =3D -EINVAL; @@ -1048,7 +1081,6 @@ static void __ris_msmon_read(void *arg) return; } =20 - now =3D FIELD_GET(MSMON___VALUE, now); *m->val +=3D now; } =20 @@ -1261,6 +1293,67 @@ static int mpam_reprogram_ris(void *_arg) return 0; } =20 +/* Call with MSC lock held */ +static int mpam_restore_mbwu_state(void *_ris) +{ + int i; + struct mon_read mwbu_arg; + struct mpam_msc_ris *ris =3D _ris; + + for (i =3D 0; i < ris->props.num_mbwu_mon; i++) { + if (ris->mbwu_state[i].enabled) { + mwbu_arg.ris =3D ris; + mwbu_arg.ctx =3D &ris->mbwu_state[i].cfg; + mwbu_arg.type =3D mpam_feat_msmon_mbwu; + + __ris_msmon_read(&mwbu_arg); + } + } + + return 0; +} + +/* Call with MSC lock and held */ +static int mpam_save_mbwu_state(void *arg) +{ + int i; + u64 val; + struct mon_cfg *cfg; + u32 cur_flt, cur_ctl, mon_sel; + struct mpam_msc_ris *ris =3D arg; + struct msmon_mbwu_state *mbwu_state; + struct mpam_msc *msc =3D ris->vmsc->msc; + + for (i =3D 0; i < ris->props.num_mbwu_mon; i++) { + mbwu_state =3D &ris->mbwu_state[i]; + cfg =3D &mbwu_state->cfg; + + if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + return -EIO; + + mon_sel =3D FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) | + FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); + mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); + + cur_flt =3D mpam_read_monsel_reg(msc, CFG_MBWU_FLT); + cur_ctl =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); + mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); + + val =3D mpam_read_monsel_reg(msc, MBWU); + mpam_write_monsel_reg(msc, MBWU, 0); + + cfg->mon =3D i; + cfg->pmg =3D FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt); + cfg->match_pmg =3D FIELD_GET(MSMON_CFG_x_CTL_MATCH_PMG, cur_ctl); + cfg->partid =3D FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt); + mbwu_state->correction +=3D val; + mbwu_state->enabled =3D FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl); + mpam_mon_sel_unlock(msc); + } + + return 0; +} + static void mpam_init_reset_cfg(struct mpam_config *reset_cfg) { memset(reset_cfg, 0, sizeof(*reset_cfg)); @@ -1335,6 +1428,9 @@ static void mpam_reset_msc(struct mpam_msc *msc, bool= online) * for non-zero partid may be lost while the CPUs are offline. */ ris->in_reset_state =3D online; + + if (mpam_is_enabled() && !online) + mpam_touch_msc(msc, &mpam_save_mbwu_state, ris); } } =20 @@ -1369,6 +1465,9 @@ static void mpam_reprogram_msc(struct mpam_msc *msc) mpam_reprogram_ris_partid(ris, partid, cfg); } ris->in_reset_state =3D reset; + + if (mpam_has_feature(mpam_feat_msmon_mbwu, &ris->props)) + mpam_touch_msc(msc, &mpam_restore_mbwu_state, ris); } } =20 @@ -2091,11 +2190,33 @@ static void mpam_unregister_irqs(void) =20 static void __destroy_component_cfg(struct mpam_component *comp) { + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + + lockdep_assert_held(&mpam_list_lock); + add_to_garbage(comp->cfg); + list_for_each_entry(vmsc, &comp->vmsc, comp_list) { + msc =3D vmsc->msc; + + if (mpam_mon_sel_lock(msc)) { + list_for_each_entry(ris, &vmsc->ris, vmsc_list) + add_to_garbage(ris->mbwu_state); + mpam_mon_sel_unlock(msc); + } + } } =20 static int __allocate_component_cfg(struct mpam_component *comp) { + int err =3D 0; + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + struct msmon_mbwu_state *mbwu_state; + + lockdep_assert_held(&mpam_list_lock); mpam_assert_partid_sizes_fixed(); =20 if (comp->cfg) @@ -2106,6 +2227,35 @@ static int __allocate_component_cfg(struct mpam_comp= onent *comp) return -ENOMEM; init_garbage(comp->cfg); =20 + list_for_each_entry(vmsc, &comp->vmsc, comp_list) { + if (!vmsc->props.num_mbwu_mon) + continue; + + msc =3D vmsc->msc; + list_for_each_entry(ris, &vmsc->ris, vmsc_list) { + if (!ris->props.num_mbwu_mon) + continue; + + mbwu_state =3D kcalloc(ris->props.num_mbwu_mon, + sizeof(*ris->mbwu_state), + GFP_KERNEL); + if (!mbwu_state) { + __destroy_component_cfg(comp); + err =3D -ENOMEM; + break; + } + + if (mpam_mon_sel_lock(msc)) { + init_garbage(mbwu_state); + ris->mbwu_state =3D mbwu_state; + mpam_mon_sel_unlock(msc); + } + } + + if (err) + break; + } + return 0; } =20 diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index bb01e7dbde40..725c2aefa8a2 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -212,6 +212,26 @@ struct mon_cfg { enum mon_filter_options opts; }; =20 +/* + * Changes to enabled and cfg are protected by the msc->lock. + * Changes to prev_val and correction are protected by the msc's mon_sel_l= ock. + */ +struct msmon_mbwu_state { + bool enabled; + struct mon_cfg cfg; + + /* The value last read from the hardware. Used to detect overflow. */ + u64 prev_val; + + /* + * The value to add to the new reading to account for power management, + * and shifts to trigger the overflow interrupt. + */ + u64 correction; + + struct mpam_garbage garbage; +}; + struct mpam_class { /* mpam_components in this class */ struct list_head components; @@ -304,6 +324,9 @@ struct mpam_msc_ris { /* parent: */ struct mpam_vmsc *vmsc; =20 + /* msmon mbwu configuration is preserved over reset */ + struct msmon_mbwu_state *mbwu_state; + struct mpam_garbage garbage; }; =20 --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 21D0D2FF650; Wed, 10 Sep 2025 20:45:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537138; cv=none; b=iqO8XW7PHpB8XcfQc83BNGWsQbpZMImfSkakE618z2ob6Ao29DoNRYiwiF+h4BmFPA7p2hfvK915XAOY6qxsf5xEAQiM/LxWOFIWMhNCUDyMxt0vsR4tnaUR97X4e0bJC/GoIlk46VttrU59w+aAwHxtQK2lPzVb0DBk74TI7fI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537138; c=relaxed/simple; bh=skXi1Vu4Xztmyg4wYEMpxVKamgl0VmMShTVpPPXHP00=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j/yuOOm0IwovUIVtplAHXZB5GNz/g68bQsot7gH7X3K9jfU2j8nPruWCUAD6TAgvJeNa3REQqW9BXIJ+uKKj0Jnq8A9e8ucZr4H7Eki601Wx0jDm7YvKOGiJqd9mmg2HhoAM2FMY5Fo2A6OrBA/gD/pmaSd9szCh2ZP3X6X+5N4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21488153B; Wed, 10 Sep 2025 13:45:28 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A6F4E3F63F; Wed, 10 Sep 2025 13:45:31 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 25/29] arm_mpam: Probe for long/lwd mbwu counters Date: Wed, 10 Sep 2025 20:43:05 +0000 Message-Id: <20250910204309.20751-26-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rohit Mathew mpam v0.1 and versions above v1.0 support optional long counter for memory bandwidth monitoring. The MPAMF_MBWUMON_IDR register have fields indicating support for long counters. As of now, a 44 bit counter represented by HAS_LONG field (bit 30) and a 63 bit counter represented by LWD (bit 29) can be optionally integrated. Probe for these counters and set corresponding feature bits if any of these counters are present. Signed-off-by: Rohit Mathew Signed-off-by: James Morse Reviewed-by: Ben Horgan --- drivers/resctrl/mpam_devices.c | 23 ++++++++++++++++++++++- drivers/resctrl/mpam_internal.h | 9 +++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index eeb62ed94520..bae9fa9441dc 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -795,7 +795,7 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) dev_err_once(dev, "Counters are not usable because not-ready timeout w= as not provided by firmware."); } if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_MBWU, msmon_features)) { - bool hw_managed; + bool has_long, hw_managed; u32 mbwumon_idr =3D mpam_read_partsel_reg(msc, MBWUMON_IDR); =20 props->num_mbwu_mon =3D FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_id= r); @@ -805,6 +805,27 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) if (FIELD_GET(MPAMF_MBWUMON_IDR_HAS_RWBW, mbwumon_idr)) mpam_set_feature(mpam_feat_msmon_mbwu_rwbw, props); =20 + /* + * Treat long counter and its extension, lwd as mutually + * exclusive feature bits. Though these are dependent + * fields at the implementation level, there would never + * be a need for mpam_feat_msmon_mbwu_44counter (long + * counter) and mpam_feat_msmon_mbwu_63counter (lwd) + * bits to be set together. + * + * mpam_feat_msmon_mbwu isn't treated as an exclusive + * bit as this feature bit would be used as the "front + * facing feature bit" for any checks related to mbwu + * monitors. + */ + has_long =3D FIELD_GET(MPAMF_MBWUMON_IDR_HAS_LONG, mbwumon_idr); + if (props->num_mbwu_mon && has_long) { + if (FIELD_GET(MPAMF_MBWUMON_IDR_LWD, mbwumon_idr)) + mpam_set_feature(mpam_feat_msmon_mbwu_63counter, props); + else + mpam_set_feature(mpam_feat_msmon_mbwu_44counter, props); + } + /* Is NRDY hardware managed? */ hw_managed =3D mpam_ris_hw_probe_hw_nrdy(ris, MBWU); if (hw_managed) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 725c2aefa8a2..c190826dfbda 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -158,7 +158,16 @@ enum mpam_device_features { mpam_feat_msmon_csu_capture, mpam_feat_msmon_csu_xcl, mpam_feat_msmon_csu_hw_nrdy, + + /* + * Having mpam_feat_msmon_mbwu set doesn't mean the regular 31 bit MBWU + * counter would be used. The exact counter used is decided based on the + * status of mpam_feat_msmon_mbwu_44counter/mpam_feat_msmon_mbwu_63counter + * as well. + */ mpam_feat_msmon_mbwu, + mpam_feat_msmon_mbwu_44counter, + mpam_feat_msmon_mbwu_63counter, mpam_feat_msmon_mbwu_capture, mpam_feat_msmon_mbwu_rwbw, mpam_feat_msmon_mbwu_hw_nrdy, --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 38D1F2EE289; Wed, 10 Sep 2025 20:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537143; cv=none; b=UP322RetuTchi5KC3n76VJp3i6NsUEOhvw6HbPUfPvco7MBm75SDveUzpT2e1cOckt1bZN7shMUsynXrD+Bv1FnziNGCnZD3ioO7wMOOgtyFg0Fu1fdD59b3KCT/CfPAOj6YgZL91pTDCooAdy3naL5e0tgucCS6qZA0bV/CrWY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537143; c=relaxed/simple; bh=qarIUSn/2z3a3otIBBStepYf26ZfJ2z8yn/RRwvsrBs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HJIQeBDnXD4sv9rJDbTtRWkmSqLgHdltGqIkzDWwmFA0ZXovfgjRWeFp28odx4h215MOsFeSVIOP8IFrA5o/blOOewgXSEdssFkBk5G8pecxdINrsyKdkRwEteoiMXI4Qkf9l34kSlDKIqObL0D89wLWLJW9Hr0vDH9fpwU1h/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B01E1C0A; Wed, 10 Sep 2025 13:45:33 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C7CED3F63F; Wed, 10 Sep 2025 13:45:36 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: [PATCH v2 26/29] arm_mpam: Use long MBWU counters if supported Date: Wed, 10 Sep 2025 20:43:06 +0000 Message-Id: <20250910204309.20751-27-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rohit Mathew If the 44 bit (long) or 63 bit (LWD) counters are detected on probing the RIS, use long/LWD counter instead of the regular 31 bit mbwu counter. Only 32bit accesses to the MSC are required to be supported by the spec, but these registers are 64bits. The lower half may overflow into the higher half between two 32bit reads. To avoid this, use a helper that reads the top half multiple times to check for overflow. Signed-off-by: Rohit Mathew [morse: merged multiple patches from Rohit] Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Fenghua Yu Reviewed-by: Jonathan Cameron --- Changes since v1: * Only clear OFLOW_STATUS_L on MBWU counters. Changes since RFC: * Commit message wrangling. * Refer to 31 bit counters as opposed to 32 bit (registers). --- drivers/resctrl/mpam_devices.c | 91 ++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 9 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index bae9fa9441dc..3080a81f0845 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -927,6 +927,48 @@ struct mon_read { int err; }; =20 +static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris) +{ + return (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, &ris->props) || + mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props)); +} + +static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc) +{ + int retry =3D 3; + u32 mbwu_l_low; + u64 mbwu_l_high1, mbwu_l_high2; + + mpam_mon_sel_lock_held(msc); + + WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); + + mbwu_l_high2 =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4); + do { + mbwu_l_high1 =3D mbwu_l_high2; + mbwu_l_low =3D __mpam_read_reg(msc, MSMON_MBWU_L); + mbwu_l_high2 =3D __mpam_read_reg(msc, MSMON_MBWU_L + 4); + + retry--; + } while (mbwu_l_high1 !=3D mbwu_l_high2 && retry > 0); + + if (mbwu_l_high1 =3D=3D mbwu_l_high2) + return (mbwu_l_high1 << 32) | mbwu_l_low; + return MSMON___NRDY_L; +} + +static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc) +{ + mpam_mon_sel_lock_held(msc); + + WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz); + WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility)); + + __mpam_write_reg(msc, MSMON_MBWU_L, 0); + __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0); +} + static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val, u32 *flt_val) { @@ -989,6 +1031,9 @@ static void read_msmon_ctl_flt_vals(struct mon_read *m= , u32 *ctl_val, static void clean_msmon_ctl_val(u32 *cur_ctl) { *cur_ctl &=3D ~MSMON_CFG_x_CTL_OFLOW_STATUS; + + if (FIELD_GET(MSMON_CFG_x_CTL_TYPE, *cur_ctl) =3D=3D MSMON_CFG_MBWU_CTL_T= YPE_MBWU) + *cur_ctl &=3D ~MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L; } =20 static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val, @@ -1011,7 +1056,11 @@ static void write_msmon_ctl_flt_vals(struct mon_read= *m, u32 ctl_val, case mpam_feat_msmon_mbwu: mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val); mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val); - mpam_write_monsel_reg(msc, MBWU, 0); + if (mpam_ris_has_mbwu_long_counter(m->ris)) + mpam_msc_zero_mbwu_l(m->ris->vmsc->msc); + else + mpam_write_monsel_reg(msc, MBWU, 0); + mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN); =20 mbwu_state =3D &m->ris->mbwu_state[m->ctx->mon]; @@ -1026,8 +1075,13 @@ static void write_msmon_ctl_flt_vals(struct mon_read= *m, u32 ctl_val, =20 static u64 mpam_msmon_overflow_val(struct mpam_msc_ris *ris) { - /* TODO: scaling, and long counters */ - return GENMASK_ULL(30, 0); + /* TODO: implement scaling counters */ + if (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, &ris->props)) + return GENMASK_ULL(62, 0); + else if (mpam_has_feature(mpam_feat_msmon_mbwu_44counter, &ris->props)) + return GENMASK_ULL(43, 0); + else + return GENMASK_ULL(30, 0); } =20 /* Call with MSC lock held */ @@ -1069,10 +1123,24 @@ static void __ris_msmon_read(void *arg) now =3D FIELD_GET(MSMON___VALUE, now); break; case mpam_feat_msmon_mbwu: - now =3D mpam_read_monsel_reg(msc, MBWU); - if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops)) - nrdy =3D now & MSMON___NRDY; - now =3D FIELD_GET(MSMON___VALUE, now); + /* + * If long or lwd counters are supported, use them, else revert + * to the 31 bit counter. + */ + if (mpam_ris_has_mbwu_long_counter(ris)) { + now =3D mpam_msc_read_mbwu_l(msc); + if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops)) + nrdy =3D now & MSMON___NRDY_L; + if (mpam_has_feature(mpam_feat_msmon_mbwu_63counter, rprops)) + now =3D FIELD_GET(MSMON___LWD_VALUE, now); + else + now =3D FIELD_GET(MSMON___L_VALUE, now); + } else { + now =3D mpam_read_monsel_reg(msc, MBWU); + if (mpam_has_feature(mpam_feat_msmon_mbwu_hw_nrdy, rprops)) + nrdy =3D now & MSMON___NRDY; + now =3D FIELD_GET(MSMON___VALUE, now); + } =20 if (nrdy) break; @@ -1360,8 +1428,13 @@ static int mpam_save_mbwu_state(void *arg) cur_ctl =3D mpam_read_monsel_reg(msc, CFG_MBWU_CTL); mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0); =20 - val =3D mpam_read_monsel_reg(msc, MBWU); - mpam_write_monsel_reg(msc, MBWU, 0); + if (mpam_ris_has_mbwu_long_counter(ris)) { + val =3D mpam_msc_read_mbwu_l(msc); + mpam_msc_zero_mbwu_l(msc); + } else { + val =3D mpam_read_monsel_reg(msc, MBWU); + mpam_write_monsel_reg(msc, MBWU, 0); + } =20 cfg->mon =3D i; cfg->pmg =3D FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt); --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E30073009E6; Wed, 10 Sep 2025 20:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537148; cv=none; b=mstJypQDSJfecbMvy9vIEmhazsHKRQnXx1pEw4ev5JnmxHkF6iv3iLBCOtDBUvgm726tRe5NjxgMGSda+10pxVQLAo5Pq5Y1vpIinMJH0/MAs5Trl+IBI3HIa1LwH/2GGjFsF1rvVy48Trej8vqKrxT1MmzSf8RdprYi3slmSY8= ARC-Message-Signature: i=1; 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Wed, 10 Sep 2025 13:45:41 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 27/29] arm_mpam: Add helper to reset saved mbwu state Date: Wed, 10 Sep 2025 20:43:07 +0000 Message-Id: <20250910204309.20751-28-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" resctrl expects to reset the bandwidth counters when the filesystem is mounted. To allow this, add a helper that clears the saved mbwu state. Instead of cross calling to each CPU that can access the component MSC to write to the counter, set a flag that causes it to be zero'd on the the next read. This is easily done by forcing a configuration update. Signed-off-by: James Morse Reviewed-by: Fenghua Yu --- drivers/resctrl/mpam_devices.c | 47 +++++++++++++++++++++++++++++++-- drivers/resctrl/mpam_internal.h | 5 +++- 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 3080a81f0845..8254d6190ca2 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -1088,9 +1088,11 @@ static u64 mpam_msmon_overflow_val(struct mpam_msc_r= is *ris) static void __ris_msmon_read(void *arg) { bool nrdy =3D false; + bool config_mismatch; struct mon_read *m =3D arg; u64 now, overflow_val =3D 0; struct mon_cfg *ctx =3D m->ctx; + bool reset_on_next_read =3D false; struct mpam_msc_ris *ris =3D m->ris; struct msmon_mbwu_state *mbwu_state; struct mpam_props *rprops =3D &ris->props; @@ -1105,6 +1107,14 @@ static void __ris_msmon_read(void *arg) FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx); mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel); =20 + if (m->type =3D=3D mpam_feat_msmon_mbwu) { + mbwu_state =3D &ris->mbwu_state[ctx->mon]; + if (mbwu_state) { + reset_on_next_read =3D mbwu_state->reset_on_next_read; + mbwu_state->reset_on_next_read =3D false; + } + } + /* * Read the existing configuration to avoid re-writing the same values. * This saves waiting for 'nrdy' on subsequent reads. @@ -1112,7 +1122,10 @@ static void __ris_msmon_read(void *arg) read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt); clean_msmon_ctl_val(&cur_ctl); gen_msmon_ctl_flt_vals(m, &ctl_val, &flt_val); - if (cur_flt !=3D flt_val || cur_ctl !=3D (ctl_val | MSMON_CFG_x_CTL_EN)) + config_mismatch =3D cur_flt !=3D flt_val || + cur_ctl !=3D (ctl_val | MSMON_CFG_x_CTL_EN); + + if (config_mismatch || reset_on_next_read) write_msmon_ctl_flt_vals(m, ctl_val, flt_val); =20 switch (m->type) { @@ -1145,7 +1158,6 @@ static void __ris_msmon_read(void *arg) if (nrdy) break; =20 - mbwu_state =3D &ris->mbwu_state[ctx->mon]; if (!mbwu_state) break; =20 @@ -1245,6 +1257,37 @@ int mpam_msmon_read(struct mpam_component *comp, str= uct mon_cfg *ctx, return err; } =20 +void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ct= x) +{ + int idx; + struct mpam_msc *msc; + struct mpam_vmsc *vmsc; + struct mpam_msc_ris *ris; + + if (!mpam_is_enabled()) + return; + + idx =3D srcu_read_lock(&mpam_srcu); + list_for_each_entry_rcu(vmsc, &comp->vmsc, comp_list) { + if (!mpam_has_feature(mpam_feat_msmon_mbwu, &vmsc->props)) + continue; + + msc =3D vmsc->msc; + list_for_each_entry_rcu(ris, &vmsc->ris, vmsc_list) { + if (!mpam_has_feature(mpam_feat_msmon_mbwu, &ris->props)) + continue; + + if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc))) + continue; + + ris->mbwu_state[ctx->mon].correction =3D 0; + ris->mbwu_state[ctx->mon].reset_on_next_read =3D true; + mpam_mon_sel_unlock(msc); + } + } + srcu_read_unlock(&mpam_srcu, idx); +} + static void mpam_reset_msc_bitmap(struct mpam_msc *msc, u16 reg, u16 wd) { u32 num_words, msb; diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index c190826dfbda..7cbcafe8294a 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -223,10 +223,12 @@ struct mon_cfg { =20 /* * Changes to enabled and cfg are protected by the msc->lock. - * Changes to prev_val and correction are protected by the msc's mon_sel_l= ock. + * Changes to reset_on_next_read, prev_val and correction are protected by= the + * msc's mon_sel_lock. */ struct msmon_mbwu_state { bool enabled; + bool reset_on_next_read; struct mon_cfg cfg; =20 /* The value last read from the hardware. Used to detect overflow. */ @@ -393,6 +395,7 @@ int mpam_apply_config(struct mpam_component *comp, u16 = partid, =20 int mpam_msmon_read(struct mpam_component *comp, struct mon_cfg *ctx, enum mpam_device_features, u64 *val); +void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ct= x); =20 int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 cache_level, cpumask_t *affinity); --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 48ED6301475; Wed, 10 Sep 2025 20:45:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537153; cv=none; b=SKb9d7gV2yFDAnXPYNwQgyIm6CT5GFJlTgAIs/pt3JMV1mr4PQ3AUeYx2Aq2gO20eHvB4uIIZZMoElejg0SqD8GQBSP3uqsl40Tg0VuE8H0hLk0x2tvwFXEAfhOeB+J2jwy63GcjTnjIW7vsBkBneDM/cWrG2CPPJ78cpdpIuU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537153; c=relaxed/simple; bh=4da126Sjg4SV/zXQaObTKJcR4hhXi+OtgpTvcTh0mpI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HrdnKX+nSggAGMFt8uM/JItQq+NVv+o+7iGVwpXvXNApDkVq4qpVORFZ9KajAeUCLl4hxFCud/VBawwPtNwRZtf0X7kn5feP7pcvX2KVieCFXanjcCBu+h6/yC2+fMYRG/sspARbJfr54C02AA3qxWvQ4FsgV2767sHEP+tHQb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4BF9C1C0A; Wed, 10 Sep 2025 13:45:43 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D94753F63F; Wed, 10 Sep 2025 13:45:46 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Jonathan Cameron Subject: [PATCH v2 28/29] arm_mpam: Add kunit test for bitmap reset Date: Wed, 10 Sep 2025 20:43:08 +0000 Message-Id: <20250910204309.20751-29-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The bitmap reset code has been a source of bugs. Add a unit test. This currently has to be built in, as the rest of the driver is builtin. Suggested-by: Jonathan Cameron Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Fenghua Yu Reviewed-by: Jonathan Cameron --- drivers/resctrl/Kconfig | 10 +++++ drivers/resctrl/mpam_devices.c | 4 ++ drivers/resctrl/test_mpam_devices.c | 68 +++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 drivers/resctrl/test_mpam_devices.c diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig index c30532a3a3a4..ef59b3057d5d 100644 --- a/drivers/resctrl/Kconfig +++ b/drivers/resctrl/Kconfig @@ -5,10 +5,20 @@ menuconfig ARM64_MPAM_DRIVER MPAM driver for System IP, e,g. caches and memory controllers. =20 if ARM64_MPAM_DRIVER + config ARM64_MPAM_DRIVER_DEBUG bool "Enable debug messages from the MPAM driver" depends on ARM64_MPAM_DRIVER help Say yes here to enable debug messages from the MPAM driver. =20 +config MPAM_KUNIT_TEST + bool "KUnit tests for MPAM driver " if !KUNIT_ALL_TESTS + depends on KUNIT=3Dy + default KUNIT_ALL_TESTS + help + Enable this option to run tests in the MPAM driver. + + If unsure, say N. + endif diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c index 8254d6190ca2..2962cd018207 100644 --- a/drivers/resctrl/mpam_devices.c +++ b/drivers/resctrl/mpam_devices.c @@ -2662,3 +2662,7 @@ static int __init mpam_msc_driver_init(void) } /* Must occur after arm64_mpam_register_cpus() from arch_initcall() */ subsys_initcall(mpam_msc_driver_init); + +#ifdef CONFIG_MPAM_KUNIT_TEST +#include "test_mpam_devices.c" +#endif diff --git a/drivers/resctrl/test_mpam_devices.c b/drivers/resctrl/test_mpa= m_devices.c new file mode 100644 index 000000000000..3e7058f7601c --- /dev/null +++ b/drivers/resctrl/test_mpam_devices.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2024 Arm Ltd. +/* This file is intended to be included into mpam_devices.c */ + +#include + +static void test_mpam_reset_msc_bitmap(struct kunit *test) +{ + char __iomem *buf =3D kunit_kzalloc(test, SZ_16K, GFP_KERNEL); + struct mpam_msc fake_msc =3D {0}; + u32 *test_result; + + if (!buf) + return; + + fake_msc.mapped_hwpage =3D buf; + fake_msc.mapped_hwpage_sz =3D SZ_16K; + cpumask_copy(&fake_msc.accessibility, cpu_possible_mask); + + mutex_init(&fake_msc.part_sel_lock); + mutex_lock(&fake_msc.part_sel_lock); + + test_result =3D (u32 *)(buf + MPAMCFG_CPBM); + + mpam_reset_msc_bitmap(&fake_msc, MPAMCFG_CPBM, 0); + KUNIT_EXPECT_EQ(test, test_result[0], 0); + KUNIT_EXPECT_EQ(test, test_result[1], 0); + test_result[0] =3D 0; + test_result[1] =3D 0; + + mpam_reset_msc_bitmap(&fake_msc, MPAMCFG_CPBM, 1); + KUNIT_EXPECT_EQ(test, test_result[0], 1); + KUNIT_EXPECT_EQ(test, test_result[1], 0); + test_result[0] =3D 0; + test_result[1] =3D 0; + + mpam_reset_msc_bitmap(&fake_msc, MPAMCFG_CPBM, 16); + KUNIT_EXPECT_EQ(test, test_result[0], 0xffff); + KUNIT_EXPECT_EQ(test, test_result[1], 0); + test_result[0] =3D 0; + test_result[1] =3D 0; + + mpam_reset_msc_bitmap(&fake_msc, MPAMCFG_CPBM, 32); + KUNIT_EXPECT_EQ(test, test_result[0], 0xffffffff); + KUNIT_EXPECT_EQ(test, test_result[1], 0); + test_result[0] =3D 0; + test_result[1] =3D 0; + + mpam_reset_msc_bitmap(&fake_msc, MPAMCFG_CPBM, 33); + KUNIT_EXPECT_EQ(test, test_result[0], 0xffffffff); + KUNIT_EXPECT_EQ(test, test_result[1], 1); + test_result[0] =3D 0; + test_result[1] =3D 0; + + mutex_unlock(&fake_msc.part_sel_lock); +} + +static struct kunit_case mpam_devices_test_cases[] =3D { + KUNIT_CASE(test_mpam_reset_msc_bitmap), + {} +}; + +static struct kunit_suite mpam_devices_test_suite =3D { + .name =3D "mpam_devices_test_suite", + .test_cases =3D mpam_devices_test_cases, +}; + +kunit_test_suites(&mpam_devices_test_suite); --=20 2.39.5 From nobody Thu Oct 2 21:40:07 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3B0F5301039; Wed, 10 Sep 2025 20:45:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537159; cv=none; b=Uo2lB+UBdVGvqIAxbLbIt0TW9105wBLdFw6Ql7fVZHNrXtkrQyd2W7qqpqIFV6caq7R7IvKNjF8BtJif/8G3zTLgZTfqAzRgQzYr9M/drzl8n0VEigdHbYwasjXQuxdOPJPTwSb0XGAChwii6xBJj6qBggoGnJ3M1fxMW1N45jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757537159; c=relaxed/simple; bh=kALWgrLvp18k4apv/tsIK6SQrkoHW8swIzKy66580ZU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S9dpo7qX4x2vbuV3p0z6O6iS9njwZEoWERfbtRF3cFvDsyalkXebcPCThFKm4otq/iY+wI5d0Iv7nYtXKctpmzo6V/e/PquNvX1cGD7BqbIAHem+Ng+x+o3iy285cxSorJaVpc6Bs7bMUzhbn2ZRfDc0VYZRx2ou76MBU/Ep6EM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 46EA21EDB; Wed, 10 Sep 2025 13:45:48 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F40C83F63F; Wed, 10 Sep 2025 13:45:51 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: James Morse , D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich Subject: [PATCH v2 29/29] arm_mpam: Add kunit tests for props_mismatch() Date: Wed, 10 Sep 2025 20:43:09 +0000 Message-Id: <20250910204309.20751-30-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250910204309.20751-1-james.morse@arm.com> References: <20250910204309.20751-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When features are mismatched between MSC the way features are combined to the class determines whether resctrl can support this SoC. Add some tests to illustrate the sort of thing that is expected to work, and those that must be removed. Signed-off-by: James Morse Reviewed-by: Ben Horgan Reviewed-by: Fenghua Yu --- Changes since v1: * Waggled some words in comments. * Moved a bunch of variables to be global - shuts up a compiler warning. --- drivers/resctrl/mpam_internal.h | 8 +- drivers/resctrl/test_mpam_devices.c | 321 ++++++++++++++++++++++++++++ 2 files changed, 328 insertions(+), 1 deletion(-) diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_interna= l.h index 7cbcafe8294a..6119e4573187 100644 --- a/drivers/resctrl/mpam_internal.h +++ b/drivers/resctrl/mpam_internal.h @@ -20,6 +20,12 @@ =20 DECLARE_STATIC_KEY_FALSE(mpam_enabled); =20 +#ifdef CONFIG_MPAM_KUNIT_TEST +#define PACKED_FOR_KUNIT __packed +#else +#define PACKED_FOR_KUNIT +#endif + static inline bool mpam_is_enabled(void) { return static_branch_likely(&mpam_enabled); @@ -189,7 +195,7 @@ struct mpam_props { u16 dspri_wd; u16 num_csu_mon; u16 num_mbwu_mon; -}; +} PACKED_FOR_KUNIT; =20 #define mpam_has_feature(_feat, x) ((1 << (_feat)) & (x)->features) =20 diff --git a/drivers/resctrl/test_mpam_devices.c b/drivers/resctrl/test_mpa= m_devices.c index 3e7058f7601c..4eca8590c691 100644 --- a/drivers/resctrl/test_mpam_devices.c +++ b/drivers/resctrl/test_mpam_devices.c @@ -4,6 +4,325 @@ =20 #include =20 +/* + * This test catches fields that aren't being sanitised - but can't tell y= ou + * which one... + */ +static void test__props_mismatch(struct kunit *test) +{ + struct mpam_props parent =3D { 0 }; + struct mpam_props child; + + memset(&child, 0xff, sizeof(child)); + __props_mismatch(&parent, &child, false); + + memset(&child, 0, sizeof(child)); + KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, sizeof(child)), 0); + + memset(&child, 0xff, sizeof(child)); + __props_mismatch(&parent, &child, true); + + KUNIT_EXPECT_EQ(test, memcmp(&parent, &child, sizeof(child)), 0); +} + +static struct list_head fake_classes_list; +static struct mpam_class fake_class =3D { 0 }; +static struct mpam_component fake_comp1 =3D { 0 }; +static struct mpam_component fake_comp2 =3D { 0 }; +static struct mpam_vmsc fake_vmsc1 =3D { 0 }; +static struct mpam_vmsc fake_vmsc2 =3D { 0 }; +static struct mpam_msc fake_msc1 =3D { 0 }; +static struct mpam_msc fake_msc2 =3D { 0 }; +static struct mpam_msc_ris fake_ris1 =3D { 0 }; +static struct mpam_msc_ris fake_ris2 =3D { 0 }; +static struct platform_device fake_pdev =3D { 0 }; + +static void test_mpam_enable_merge_features(struct kunit *test) +{ +#define RESET_FAKE_HIEARCHY() do { \ + INIT_LIST_HEAD(&fake_classes_list); \ + \ + memset(&fake_class, 0, sizeof(fake_class)); \ + fake_class.level =3D 3; \ + fake_class.type =3D MPAM_CLASS_CACHE; \ + INIT_LIST_HEAD_RCU(&fake_class.components); \ + INIT_LIST_HEAD(&fake_class.classes_list); \ + \ + memset(&fake_comp1, 0, sizeof(fake_comp1)); \ + memset(&fake_comp2, 0, sizeof(fake_comp2)); \ + fake_comp1.comp_id =3D 1; \ + fake_comp2.comp_id =3D 2; \ + INIT_LIST_HEAD(&fake_comp1.vmsc); \ + INIT_LIST_HEAD(&fake_comp1.class_list); \ + INIT_LIST_HEAD(&fake_comp2.vmsc); \ + INIT_LIST_HEAD(&fake_comp2.class_list); \ + \ + memset(&fake_vmsc1, 0, sizeof(fake_vmsc1)); \ + memset(&fake_vmsc2, 0, sizeof(fake_vmsc2)); \ + INIT_LIST_HEAD(&fake_vmsc1.ris); \ + INIT_LIST_HEAD(&fake_vmsc1.comp_list); \ + fake_vmsc1.msc =3D &fake_msc1; \ + INIT_LIST_HEAD(&fake_vmsc2.ris); \ + INIT_LIST_HEAD(&fake_vmsc2.comp_list); \ + fake_vmsc2.msc =3D &fake_msc2; \ + \ + memset(&fake_ris1, 0, sizeof(fake_ris1)); \ + memset(&fake_ris2, 0, sizeof(fake_ris2)); \ + fake_ris1.ris_idx =3D 1; \ + INIT_LIST_HEAD(&fake_ris1.msc_list); \ + fake_ris2.ris_idx =3D 2; \ + INIT_LIST_HEAD(&fake_ris2.msc_list); \ + \ + fake_msc1.pdev =3D &fake_pdev; \ + fake_msc2.pdev =3D &fake_pdev; \ + \ + list_add(&fake_class.classes_list, &fake_classes_list); \ +} while (0) + + RESET_FAKE_HIEARCHY(); + + mutex_lock(&mpam_list_lock); + + /* One Class+Comp, two RIS in one vMSC with common features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D NULL; + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc1; + list_add(&fake_ris2.vmsc_list, &fake_vmsc1.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cpor_part, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cpbm_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_class= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 4); + + RESET_FAKE_HIEARCHY(); + + /* One Class+Comp, two RIS in one vMSC with non-overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D NULL; + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc1; + list_add(&fake_ris2.vmsc_list, &fake_vmsc1.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cmax_cmin, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cmax_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + /* Multiple RIS within one MSC controlling the same resource can be misma= tched */ + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_class= .props)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cmax_cmin, &fake_class= .props)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cmax_cmin, &fake_vmsc1= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 4); + KUNIT_EXPECT_EQ(test, fake_vmsc1.props.cmax_wd, 4); + KUNIT_EXPECT_EQ(test, fake_class.props.cmax_wd, 4); + + RESET_FAKE_HIEARCHY(); + + /* One Class+Comp, two MSC with overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp1; + list_add(&fake_vmsc2.comp_list, &fake_comp1.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cpor_part, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cpbm_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_class= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 4); + + RESET_FAKE_HIEARCHY(); + + /* One Class+Comp, two MSC with non-overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp1; + list_add(&fake_vmsc2.comp_list, &fake_comp1.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cmax_cmin, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cmax_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + /* + * Multiple RIS in different MSC can't control the same resource, + * mismatched features can not be supported. + */ + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_clas= s.props)); + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_cmax_cmin, &fake_clas= s.props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 0); + KUNIT_EXPECT_EQ(test, fake_class.props.cmax_wd, 0); + + RESET_FAKE_HIEARCHY(); + + /* One Class+Comp, two MSC with incompatible overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp1; + list_add(&fake_vmsc2.comp_list, &fake_comp1.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cpor_part, &fake_ris2.props); + mpam_set_feature(mpam_feat_mbw_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_mbw_part, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 5; + fake_ris2.props.cpbm_wd =3D 3; + fake_ris1.props.mbw_pbm_bits =3D 5; + fake_ris2.props.mbw_pbm_bits =3D 3; + + mpam_enable_merge_features(&fake_classes_list); + + /* + * Multiple RIS in different MSC can't control the same resource, + * mismatched features can not be supported. + */ + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_clas= s.props)); + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_mbw_part, &fake_class= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 0); + KUNIT_EXPECT_EQ(test, fake_class.props.mbw_pbm_bits, 0); + + RESET_FAKE_HIEARCHY(); + + /* One Class+Comp, two MSC with overlapping features that need tweaking */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D NULL; + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp1; + list_add(&fake_vmsc2.comp_list, &fake_comp1.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_mbw_min, &fake_ris1.props); + mpam_set_feature(mpam_feat_mbw_min, &fake_ris2.props); + mpam_set_feature(mpam_feat_cmax_cmax, &fake_ris1.props); + mpam_set_feature(mpam_feat_cmax_cmax, &fake_ris2.props); + fake_ris1.props.bwa_wd =3D 5; + fake_ris2.props.bwa_wd =3D 3; + fake_ris1.props.cmax_wd =3D 5; + fake_ris2.props.cmax_wd =3D 3; + + mpam_enable_merge_features(&fake_classes_list); + + /* + * RIS with different control properties need to be sanitised so the + * class has the common set of properties. + */ + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_mbw_min, &fake_class.p= rops)); + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cmax_cmax, &fake_class= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.bwa_wd, 3); + KUNIT_EXPECT_EQ(test, fake_class.props.cmax_wd, 3); + + RESET_FAKE_HIEARCHY(); + + /* One Class Two Comp with overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D &fake_class; + list_add(&fake_comp2.class_list, &fake_class.components); + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp2; + list_add(&fake_vmsc2.comp_list, &fake_comp2.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cpor_part, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cpbm_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + KUNIT_EXPECT_TRUE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_class= .props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 4); + + RESET_FAKE_HIEARCHY(); + + /* One Class Two Comp with non-overlapping features */ + fake_comp1.class =3D &fake_class; + list_add(&fake_comp1.class_list, &fake_class.components); + fake_comp2.class =3D &fake_class; + list_add(&fake_comp2.class_list, &fake_class.components); + fake_vmsc1.comp =3D &fake_comp1; + list_add(&fake_vmsc1.comp_list, &fake_comp1.vmsc); + fake_vmsc2.comp =3D &fake_comp2; + list_add(&fake_vmsc2.comp_list, &fake_comp2.vmsc); + fake_ris1.vmsc =3D &fake_vmsc1; + list_add(&fake_ris1.vmsc_list, &fake_vmsc1.ris); + fake_ris2.vmsc =3D &fake_vmsc2; + list_add(&fake_ris2.vmsc_list, &fake_vmsc2.ris); + + mpam_set_feature(mpam_feat_cpor_part, &fake_ris1.props); + mpam_set_feature(mpam_feat_cmax_cmin, &fake_ris2.props); + fake_ris1.props.cpbm_wd =3D 4; + fake_ris2.props.cmax_wd =3D 4; + + mpam_enable_merge_features(&fake_classes_list); + + /* + * Multiple components can't control the same resource, mismatched featur= es can + * not be supported. + */ + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_cpor_part, &fake_clas= s.props)); + KUNIT_EXPECT_FALSE(test, mpam_has_feature(mpam_feat_cmax_cmin, &fake_clas= s.props)); + KUNIT_EXPECT_EQ(test, fake_class.props.cpbm_wd, 0); + KUNIT_EXPECT_EQ(test, fake_class.props.cmax_wd, 0); + + mutex_unlock(&mpam_list_lock); + +#undef RESET_FAKE_HIEARCHY +} + static void test_mpam_reset_msc_bitmap(struct kunit *test) { char __iomem *buf =3D kunit_kzalloc(test, SZ_16K, GFP_KERNEL); @@ -57,6 +376,8 @@ static void test_mpam_reset_msc_bitmap(struct kunit *tes= t) =20 static struct kunit_case mpam_devices_test_cases[] =3D { KUNIT_CASE(test_mpam_reset_msc_bitmap), + KUNIT_CASE(test_mpam_enable_merge_features), + KUNIT_CASE(test__props_mismatch), {} }; =20 --=20 2.39.5