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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific Date: Wed, 10 Sep 2025 21:41:27 +0100 Message-ID: <20250910204132.319975-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Move the hardcoded switch mode mask definition into the SoC-specific miic_of_data structure. This allows each SoC to define its own mask value rather than relying on a single fixed constant. For RZ/N1 the mask remains GENMASK(4, 0). This is in preparation for adding support for RZ/T2H, where the switch mode mask is GENMASK(2, 0). Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Added a comment about replacing with FIELD_PREP(). - Fixed checkpatch warning to fit within 80 columns. - Added Tested-by tag. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 31d9e0982ad6..f6d9c03d10f0 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -23,7 +24,6 @@ #define MIIC_ESID_CODE 0x4 =20 #define MIIC_MODCTRL 0x8 -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) =20 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 @@ -146,6 +146,7 @@ struct miic { * @index_to_string_count: Number of entries in the index_to_string array * @miic_port_start: MIIC port start number * @miic_port_max: Maximum MIIC supported + * @sw_mode_mask: Switch mode mask */ struct miic_of_data { struct modctrl_match *match_table; @@ -157,6 +158,7 @@ struct miic_of_data { u8 index_to_string_count; u8 miic_port_start; u8 miic_port_max; + u8 sw_mode_mask; }; =20 /** @@ -402,6 +404,7 @@ EXPORT_SYMBOL(miic_destroy); =20 static int miic_init_hw(struct miic *miic, u32 cfg_mode) { + u8 sw_mode_mask =3D miic->of_data->sw_mode_mask; int port; =20 /* Unlock write access to accessory registers (cf datasheet). If this @@ -413,8 +416,11 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mod= e) miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); miic_reg_writel(miic, MIIC_PRCMD, 0x0001); =20 + /* TODO: Replace with FIELD_PREP() when compile-time constant + * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. + */ miic_reg_writel(miic, MIIC_MODCTRL, - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); =20 for (port =3D 0; port < miic->of_data->miic_port_max; port++) { miic_converter_enable(miic, port, 0); @@ -582,6 +588,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .index_to_string_count =3D ARRAY_SIZE(index_to_string), .miic_port_start =3D 1, .miic_port_max =3D 5, + .sw_mode_mask =3D GENMASK(4, 0), }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.51.0