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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 9/9] net: pcs: rzn1-miic: Add RZ/T2H MIIC support Date: Wed, 10 Sep 2025 21:41:30 +0100 Message-ID: <20250910204132.319975-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the Renesas RZ/T2H MIIC by defining SoC-specific modctrl match tables, register map, and string representations for converters and ports. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Dropped inlining of miic_lock_regs(). - Added Tested-by tag. v1->v2: - Dropped regx in config description. - Used "renesas,r9a09g077-miic" as compatible for RZ/T2H. --- drivers/net/pcs/Kconfig | 11 +++-- drivers/net/pcs/pcs-rzn1-miic.c | 82 +++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index f6aa437473de..76dbc11d9575 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -26,11 +26,12 @@ config PCS_MTK_LYNXI which is part of MediaTek's SoC and Ethernet switch ICs. =20 config PCS_RZN1_MIIC - tristate "Renesas RZ/N1 MII converter" - depends on OF && (ARCH_RZN1 || COMPILE_TEST) + tristate "Renesas RZ/N1, RZ/N2H, RZ/T2H MII converter" + depends on OF + depends on ARCH_RZN1 || ARCH_R9A09G077 || ARCH_R9A09G087 || COMPILE_TEST help - This module provides a driver for the MII converter that is available - on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in - pass-through mode for MII. + This module provides a driver for the MII converter available on + Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to + RMII/RGMII, or can be set in pass-through mode for MII. =20 endmenu diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index ef10994d8c11..885f17c32643 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -21,6 +21,7 @@ #include #include #include +#include =20 #define MIIC_PRCMD 0x0 #define MIIC_ESID_CODE 0x4 @@ -125,6 +126,57 @@ static const char * const index_to_string[] =3D { "CONV5", }; =20 +static struct modctrl_match rzt2h_modctrl_match_table[] =3D { + {0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, + + {0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, + + {0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, + ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, + + {0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, + ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, + + {0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT, + ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}} +}; + +static const char * const rzt2h_conf_to_string[] =3D { + [ETHSS_GMAC0_PORT] =3D "GMAC0_PORT", + [ETHSS_GMAC1_PORT] =3D "GMAC1_PORT", + [ETHSS_GMAC2_PORT] =3D "GMAC2_PORT", + [ETHSS_ESC_PORT0] =3D "ETHERCAT_PORT0", + [ETHSS_ESC_PORT1] =3D "ETHERCAT_PORT1", + [ETHSS_ESC_PORT2] =3D "ETHERCAT_PORT2", + [ETHSS_ETHSW_PORT0] =3D "SWITCH_PORT0", + [ETHSS_ETHSW_PORT1] =3D "SWITCH_PORT1", + [ETHSS_ETHSW_PORT2] =3D "SWITCH_PORT2", +}; + +static const char * const rzt2h_index_to_string[] =3D { + "SWITCH_PORTIN", + "CONV0", + "CONV1", + "CONV2", + "CONV3", +}; + +static const char * const rzt2h_reset_ids[] =3D { + "rst", + "crst", +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -204,11 +256,24 @@ static void miic_unlock_regs(struct miic *miic) writel(0x0001, miic->base + MIIC_PRCMD); } =20 +static void miic_lock_regs(struct miic *miic) +{ + /* Protect register writes */ + writel(0x0000, miic->base + MIIC_PRCMD); +} + static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 va= lue) { writel(value, miic->base + offset); } =20 +static void miic_reg_writel_locked(struct miic *miic, int offset, u32 valu= e) +{ + miic_unlock_regs(miic); + writel(value, miic->base + offset); + miic_lock_regs(miic); +} + static void miic_reg_writel(struct miic *miic, int offset, u32 value) { miic->of_data->miic_write(miic, offset, value); @@ -666,7 +731,24 @@ static struct miic_of_data rzn1_miic_of_data =3D { .miic_write =3D miic_reg_writel_unlocked, }; =20 +static struct miic_of_data rzt2h_miic_of_data =3D { + .match_table =3D rzt2h_modctrl_match_table, + .match_table_count =3D ARRAY_SIZE(rzt2h_modctrl_match_table), + .conf_conv_count =3D 5, + .conf_to_string =3D rzt2h_conf_to_string, + .conf_to_string_count =3D ARRAY_SIZE(rzt2h_conf_to_string), + .index_to_string =3D rzt2h_index_to_string, + .index_to_string_count =3D ARRAY_SIZE(rzt2h_index_to_string), + .miic_port_start =3D 0, + .miic_port_max =3D 4, + .sw_mode_mask =3D GENMASK(2, 0), + .reset_ids =3D rzt2h_reset_ids, + .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), + .miic_write =3D miic_reg_writel_locked, +}; + static const struct of_device_id miic_of_mtable[] =3D { + { .compatible =3D "renesas,r9a09g077-miic", .data =3D &rzt2h_miic_of_data= }, { .compatible =3D "renesas,rzn1-miic", .data =3D &rzn1_miic_of_data }, { /* sentinel */ } }; --=20 2.51.0