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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 1/9] dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support Date: Wed, 10 Sep 2025 21:41:22 +0100 Message-ID: <20250910204132.319975-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC functionality but have architectural differences that require schema updates. Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and "renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to the RZ/T2H variant. The new SoCs require reset support with two reset lines for converter register reset and converter reset, which are not present on RZ/N1. Update port configurations to accommodate the different architectures. RZ/N1 supports 5 ports numbered 1-5 with complex input mappings covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports numbered 0-3 with simplified input mappings covering indices 0-8. Extend the switch port configuration property to support value 0 for the new SoCs. Add a new dt-bindings header file with media interface connection matrix constants that map GMAC, ESC, and ETHSW ports to numeric identifiers for use with RZ/T2H and RZ/N2H device trees. Update DT schema validation to ensure proper port numbering and input mappings per SoC variant. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) --- v2->v3: - Added Tested-by tag. v1->v2: - Dropped regx in title and description. - As done for other IPs used T2H compatible as a fallback for N2H. - Renamed pcs-rzt2h-miic.h -> renesas,r9a09g077-pcs-miic.h - Added matrix table in the new header file. - Corrected the resets check for RZ/N1. - Updated the commit message. --- .../bindings/net/pcs/renesas,rzn1-miic.yaml | 177 +++++++++++++----- .../net/renesas,r9a09g077-pcs-miic.h | 36 ++++ 2 files changed, 165 insertions(+), 48 deletions(-) create mode 100644 include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.ya= ml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 2d33bbab7163..3adbcf56d2be 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -4,14 +4,15 @@ $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Renesas RZ/N1 MII converter +title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter =20 maintainers: - Cl=C3=A9ment L=C3=A9ger + - Lad Prabhakar =20 description: | - This MII converter is present on the Renesas RZ/N1 SoC family. It is - responsible to do MII passthrough or convert it to RMII/RGMII. + This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC + families. It is responsible to do MII passthrough or convert it to RMII/= RGMII. =20 properties: '#address-cells': @@ -21,10 +22,16 @@ properties: const: 0 =20 compatible: - items: - - enum: - - renesas,r9a06g032-miic - - const: renesas,rzn1-miic + oneOf: + - items: + - enum: + - renesas,r9a06g032-miic + - const: renesas,rzn1-miic + - items: + - const: renesas,r9a09g077-miic # RZ/T2H + - items: + - const: renesas,r9a09g087-miic # RZ/N2H + - const: renesas,r9a09g077-miic =20 reg: maxItems: 1 @@ -43,11 +50,22 @@ properties: - const: rmii_ref - const: hclk =20 + resets: + items: + - description: Converter register reset + - description: Converter reset + + reset-names: + items: + - const: rst + - const: crst + renesas,miic-switch-portin: description: MII Switch PORTIN configuration. This value should use on= e of - the values defined in dt-bindings/net/pcs-rzn1-miic.h. + the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC = and + include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/= T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2] + enum: [0, 1, 2] =20 power-domains: maxItems: 1 @@ -60,11 +78,12 @@ patternProperties: properties: reg: description: MII Converter port number. - enum: [1, 2, 3, 4, 5] + enum: [0, 1, 2, 3, 4, 5] =20 renesas,miic-input: description: Converter input port configuration. This value should= use - one of the values defined in dt-bindings/net/pcs-rzn1-miic.h. + one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for= RZ/N1 SoC + and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/= N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 =20 required: @@ -73,47 +92,109 @@ patternProperties: =20 additionalProperties: false =20 - allOf: - - if: - properties: - reg: - const: 1 - then: - properties: - renesas,miic-input: - const: 0 - - if: +allOf: + - if: + properties: + compatible: + contains: + const: renesas,rzn1-miic + then: + properties: + renesas,miic-switch-portin: + enum: [1, 2] + resets: false + reset-names: false + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 2 - then: - properties: - renesas,miic-input: - enum: [1, 11] - - if: - properties: - reg: - const: 3 - then: - properties: - renesas,miic-input: - enum: [7, 10] - - if: + enum: [1, 2, 3, 4, 5] + allOf: + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + const: 0 + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [1, 11] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + enum: [7, 10] + - if: + properties: + reg: + const: 4 + then: + properties: + renesas,miic-input: + enum: [4, 6, 9, 13] + - if: + properties: + reg: + const: 5 + then: + properties: + renesas,miic-input: + enum: [3, 5, 8, 12] + else: + properties: + renesas,miic-switch-portin: + const: 0 + required: + - resets + - reset-names + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 4 - then: - properties: - renesas,miic-input: - enum: [4, 6, 9, 13] - - if: - properties: - reg: - const: 5 - then: - properties: - renesas,miic-input: - enum: [3, 5, 8, 12] + enum: [0, 1, 2, 3] + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + renesas,miic-input: + enum: [0, 3, 6] + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + enum: [1, 4, 7] + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [2, 5, 8] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + const: 1 =20 required: - '#address-cells' diff --git a/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h b/include= /dt-bindings/net/renesas,r9a09g077-pcs-miic.h new file mode 100644 index 000000000000..43a2b5743a63 --- /dev/null +++ b/include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation. + */ + +#ifndef _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H +#define _DT_BINDINGS_RENASAS_R9A09G077_PCS_MIIC_H + +/* + * Media Interface Connection Matrix + * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + * + * Selects the function of the Media interface of the MAC to be used + * + * SW_MODE[2:0] | Port 0 | Port 1 | Port 2 | Port 3 + * -------------|-------------|-------------|-------------|------------- + * 000b | ETHSW Port0 | ETHSW Port1 | ETHSW Port2 | GMAC1 + * 001b | ESC Port0 | ESC Port1 | GMAC2 | GMAC1 + * 010b | ESC Port0 | ESC Port1 | ETHSW Port2 | GMAC1 + * 011b | ESC Port0 | ESC Port1 | ESC Port2 | GMAC1 + * 100b | ETHSW Port0 | ESC Port1 | ESC Port2 | GMAC1 + * 101b | ETHSW Port0 | ESC Port1 | ETHSW Port2 | GMAC1 + * 110b | ETHSW Port0 | ETHSW Port1 | GMAC2 | GMAC1 + * 111b | GMAC0 | GMAC1 | GMAC2 | - + */ +#define ETHSS_GMAC0_PORT 0 +#define ETHSS_GMAC1_PORT 1 +#define ETHSS_GMAC2_PORT 2 +#define ETHSS_ESC_PORT0 3 +#define ETHSS_ESC_PORT1 4 +#define ETHSS_ESC_PORT2 5 +#define ETHSS_ETHSW_PORT0 6 +#define ETHSS_ETHSW_PORT1 7 +#define ETHSS_ETHSW_PORT2 8 + +#endif --=20 2.51.0 From nobody Thu Oct 2 21:41:04 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 955302F616D; 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Wed, 10 Sep 2025 13:41:38 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:38 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Andrew Lunn Subject: [PATCH net-next v3 2/9] net: pcs: rzn1-miic: Drop trailing comma from of_device_id table Date: Wed, 10 Sep 2025 21:41:23 +0100 Message-ID: <20250910204132.319975-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Remove the trailing comma after the sentinel entry in the of_device_id match table. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang --- v2->v3: - Added Reviewed-by and Tested-by tags. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index ce73d9474d5b..c1bd7cd58478 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -529,7 +529,7 @@ static void miic_remove(struct platform_device *pdev) =20 static const struct of_device_id miic_of_mtable[] =3D { { .compatible =3D "renesas,rzn1-miic" }, - { /* sentinel */ }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, miic_of_mtable); =20 --=20 2.51.0 From nobody Thu Oct 2 21:41:04 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACC552F6196; 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Wed, 10 Sep 2025 13:41:39 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:39 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Andrew Lunn Subject: [PATCH net-next v3 3/9] net: pcs: rzn1-miic: Add missing include files Date: Wed, 10 Sep 2025 21:41:24 +0100 Message-ID: <20250910204132.319975-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Lad Prabhakar The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK() macros but does not explicitly include the headers where they are defined. Add the missing and includes. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang --- v2->v3: - Added Reviewed-by and Tested-by tags. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index c1bd7cd58478..adf4b5e4741c 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -5,6 +5,8 @@ * Cl=C3=A9ment L=C3=A9ger */ =20 +#include +#include #include #include #include --=20 2.51.0 From nobody Thu Oct 2 21:41:04 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 052042FB08E; Wed, 10 Sep 2025 20:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Wed, 10 Sep 2025 13:41:41 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 4/9] net: pcs: rzn1-miic: Move configuration data to SoC-specific struct Date: Wed, 10 Sep 2025 21:41:25 +0100 Message-ID: <20250910204132.319975-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Move configuration data such as the modctrl matching table, converter count, and string lookup tables into the SoC-specific miic_of_data structure. Update the helper functions to use the per-SoC configuration instead of relying on fixed-size arrays or global tables, and allocate DT configuration memory dynamically. This refactoring keeps the existing RZ/N1 support intact while preparing the driver to handle the different configuration requirements of the RZ/T2H SoC. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Added Tested-by tag. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 109 ++++++++++++++++++++++---------- 1 file changed, 77 insertions(+), 32 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index adf4b5e4741c..afa0c2ffbd30 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -16,6 +16,7 @@ #include #include #include +#include #include =20 #define MIIC_PRCMD 0x0 @@ -50,7 +51,7 @@ =20 #define MIIC_MAX_NR_PORTS 5 =20 -#define MIIC_MODCTRL_CONF_CONV_NUM 6 +#define MIIC_MODCTRL_CONF_CONV_MAX 6 #define MIIC_MODCTRL_CONF_NONE -1 =20 /** @@ -58,11 +59,13 @@ * See section 8.2.1 of manual. * @mode_cfg: Configuration value for convctrl * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORT= IN, - * then index 1 - 5 are CONV1 - CONV5. + * then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case + * of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then + * index 0 - 3 are CONV0 - CONV3. */ struct modctrl_match { u32 mode_cfg; - u8 conv[MIIC_MODCTRL_CONF_CONV_NUM]; + u8 conv[MIIC_MODCTRL_CONF_CONV_MAX]; }; =20 static struct modctrl_match modctrl_match_table[] =3D { @@ -111,7 +114,7 @@ static const char * const conf_to_string[] =3D { [MIIC_HSR_PORTB] =3D "HSR_PORTB", }; =20 -static const char *index_to_string[MIIC_MODCTRL_CONF_CONV_NUM] =3D { +static const char * const index_to_string[] =3D { "SWITCH_PORTIN", "CONV1", "CONV2", @@ -125,11 +128,33 @@ static const char *index_to_string[MIIC_MODCTRL_CONF_= CONV_NUM] =3D { * @base: base address of the MII converter * @dev: Device associated to the MII converter * @lock: Lock used for read-modify-write access + * @of_data: Pointer to OF data */ struct miic { void __iomem *base; struct device *dev; spinlock_t lock; + const struct miic_of_data *of_data; +}; + +/** + * struct miic_of_data - OF data for MII converter + * @match_table: Matching table for convctrl configuration + * @match_table_count: Number of entries in the matching table + * @conf_conv_count: Number of entries in the conf_conv array + * @conf_to_string: String representations of the configuration values + * @conf_to_string_count: Number of entries in the conf_to_string array + * @index_to_string: String representations of the index values + * @index_to_string_count: Number of entries in the index_to_string array + */ +struct miic_of_data { + struct modctrl_match *match_table; + u8 match_table_count; + u8 conf_conv_count; + const char * const *conf_to_string; + u8 conf_to_string_count; + const char * const *index_to_string; + u8 index_to_string_count; }; =20 /** @@ -398,12 +423,11 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mo= de) return 0; } =20 -static bool miic_modctrl_match(s8 table_val[MIIC_MODCTRL_CONF_CONV_NUM], - s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]) +static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count) { int i; =20 - for (i =3D 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { + for (i =3D 0; i < count; i++) { if (dt_val[i] =3D=3D MIIC_MODCTRL_CONF_NONE) continue; =20 @@ -414,53 +438,59 @@ static bool miic_modctrl_match(s8 table_val[MIIC_MODC= TRL_CONF_CONV_NUM], return true; } =20 -static void miic_dump_conf(struct device *dev, - s8 conf[MIIC_MODCTRL_CONF_CONV_NUM]) +static void miic_dump_conf(struct miic *miic, s8 *conf) { + const struct miic_of_data *of_data =3D miic->of_data; const char *conf_name; int i; =20 - for (i =3D 0; i < MIIC_MODCTRL_CONF_CONV_NUM; i++) { + for (i =3D 0; i < of_data->conf_conv_count; i++) { if (conf[i] !=3D MIIC_MODCTRL_CONF_NONE) - conf_name =3D conf_to_string[conf[i]]; + conf_name =3D of_data->conf_to_string[conf[i]]; else conf_name =3D "NONE"; =20 - dev_err(dev, "%s: %s\n", index_to_string[i], conf_name); + dev_err(miic->dev, "%s: %s\n", + of_data->index_to_string[i], conf_name); } } =20 -static int miic_match_dt_conf(struct device *dev, - s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM], - u32 *mode_cfg) +static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg) { + const struct miic_of_data *of_data =3D miic->of_data; struct modctrl_match *table_entry; int i; =20 - for (i =3D 0; i < ARRAY_SIZE(modctrl_match_table); i++) { - table_entry =3D &modctrl_match_table[i]; + for (i =3D 0; i < of_data->match_table_count; i++) { + table_entry =3D &of_data->match_table[i]; =20 - if (miic_modctrl_match(table_entry->conv, dt_val)) { + if (miic_modctrl_match(table_entry->conv, dt_val, + miic->of_data->conf_conv_count)) { *mode_cfg =3D table_entry->mode_cfg; return 0; } } =20 - dev_err(dev, "Failed to apply requested configuration\n"); - miic_dump_conf(dev, dt_val); + dev_err(miic->dev, "Failed to apply requested configuration\n"); + miic_dump_conf(miic, dt_val); =20 return -EINVAL; } =20 -static int miic_parse_dt(struct device *dev, u32 *mode_cfg) +static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) { - s8 dt_val[MIIC_MODCTRL_CONF_CONV_NUM]; - struct device_node *np =3D dev->of_node; + struct device_node *np =3D miic->dev->of_node; struct device_node *conv; + int port, ret; + s8 *dt_val; u32 conf; - int port; =20 - memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(dt_val)); + dt_val =3D kmalloc_array(miic->of_data->conf_conv_count, + sizeof(*dt_val), GFP_KERNEL); + if (!dt_val) + return -ENOMEM; + + memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val)); =20 if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) =3D=3D = 0) dt_val[0] =3D conf; @@ -473,7 +503,10 @@ static int miic_parse_dt(struct device *dev, u32 *mode= _cfg) dt_val[port] =3D conf; } =20 - return miic_match_dt_conf(dev, dt_val, mode_cfg); + ret =3D miic_match_dt_conf(miic, dt_val, mode_cfg); + kfree(dt_val); + + return ret; } =20 static int miic_probe(struct platform_device *pdev) @@ -483,16 +516,18 @@ static int miic_probe(struct platform_device *pdev) u32 mode_cfg; int ret; =20 - ret =3D miic_parse_dt(dev, &mode_cfg); - if (ret < 0) - return ret; - miic =3D devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL); if (!miic) return -ENOMEM; =20 - spin_lock_init(&miic->lock); + miic->of_data =3D of_device_get_match_data(dev); miic->dev =3D dev; + + ret =3D miic_parse_dt(miic, &mode_cfg); + if (ret < 0) + return ret; + + spin_lock_init(&miic->lock); miic->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(miic->base)) return PTR_ERR(miic->base); @@ -529,8 +564,18 @@ static void miic_remove(struct platform_device *pdev) pm_runtime_put(&pdev->dev); } =20 +static struct miic_of_data rzn1_miic_of_data =3D { + .match_table =3D modctrl_match_table, + .match_table_count =3D ARRAY_SIZE(modctrl_match_table), + .conf_conv_count =3D MIIC_MODCTRL_CONF_CONV_MAX, + .conf_to_string =3D conf_to_string, + .conf_to_string_count =3D ARRAY_SIZE(conf_to_string), + .index_to_string =3D index_to_string, + .index_to_string_count =3D ARRAY_SIZE(index_to_string), +}; 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Wed, 10 Sep 2025 13:41:42 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:41 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Andrew Lunn Subject: [PATCH net-next v3 5/9] net: pcs: rzn1-miic: move port range handling into SoC data Date: Wed, 10 Sep 2025 21:41:26 +0100 Message-ID: <20250910204132.319975-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Define per-SoC miic_port_start and miic_port_max fields in struct miic_of_data and use them to validate the device-tree "reg" port number and to compute the driver's internal zero-based port index as (port - miic_port_start). Replace uses of the hard-coded MIIC_MAX_NR_PORTS with the SoC-provided miic_port_max when iterating over ports. On RZ/N1 the MIIC ports are numbered 1..5, whereas RZ/T2H numbers its MIIC ports 0..3. By making the port base and range part of the OF data the driver no longer assumes a fixed numbering scheme and can support SoCs that enumerate ports from either zero or one and that expose different numbers of ports. This change is preparatory work for adding RZ/T2H support. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang --- v2->v3: - Added Reviewed-by and Tested-by tags. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index afa0c2ffbd30..31d9e0982ad6 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -49,8 +49,6 @@ #define MIIC_SWCTRL 0x304 #define MIIC_SWDUPC 0x308 =20 -#define MIIC_MAX_NR_PORTS 5 - #define MIIC_MODCTRL_CONF_CONV_MAX 6 #define MIIC_MODCTRL_CONF_NONE -1 =20 @@ -146,6 +144,8 @@ struct miic { * @conf_to_string_count: Number of entries in the conf_to_string array * @index_to_string: String representations of the index values * @index_to_string_count: Number of entries in the index_to_string array + * @miic_port_start: MIIC port start number + * @miic_port_max: Maximum MIIC supported */ struct miic_of_data { struct modctrl_match *match_table; @@ -155,6 +155,8 @@ struct miic_of_data { u8 conf_to_string_count; const char * const *index_to_string; u8 index_to_string_count; + u8 miic_port_start; + u8 miic_port_max; }; =20 /** @@ -330,6 +332,7 @@ static const struct phylink_pcs_ops miic_phylink_ops = =3D { =20 struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) { + const struct miic_of_data *of_data; struct platform_device *pdev; struct miic_port *miic_port; struct device_node *pcs_np; @@ -342,9 +345,6 @@ struct phylink_pcs *miic_create(struct device *dev, str= uct device_node *np) if (of_property_read_u32(np, "reg", &port)) return ERR_PTR(-EINVAL); =20 - if (port > MIIC_MAX_NR_PORTS || port < 1) - return ERR_PTR(-EINVAL); - /* The PCS pdev is attached to the parent node */ pcs_np =3D of_get_parent(np); if (!pcs_np) @@ -363,18 +363,24 @@ struct phylink_pcs *miic_create(struct device *dev, s= truct device_node *np) return ERR_PTR(-EPROBE_DEFER); } =20 + miic =3D platform_get_drvdata(pdev); + of_data =3D miic->of_data; + if (port > of_data->miic_port_max || port < of_data->miic_port_start) { + put_device(&pdev->dev); + return ERR_PTR(-EINVAL); + } + miic_port =3D kzalloc(sizeof(*miic_port), GFP_KERNEL); if (!miic_port) { put_device(&pdev->dev); return ERR_PTR(-ENOMEM); } =20 - miic =3D platform_get_drvdata(pdev); device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER); put_device(&pdev->dev); =20 miic_port->miic =3D miic; - miic_port->port =3D port - 1; + miic_port->port =3D port - of_data->miic_port_start; miic_port->pcs.ops =3D &miic_phylink_ops; =20 phy_interface_set_rgmii(miic_port->pcs.supported_interfaces); @@ -410,7 +416,7 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode) miic_reg_writel(miic, MIIC_MODCTRL, FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); =20 - for (port =3D 0; port < MIIC_MAX_NR_PORTS; port++) { + for (port =3D 0; port < miic->of_data->miic_port_max; port++) { miic_converter_enable(miic, port, 0); /* Disable speed/duplex control from these registers, datasheet * says switch registers should be used to setup switch port @@ -499,6 +505,8 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_c= fg) if (of_property_read_u32(conv, "reg", &port)) continue; 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Wed, 10 Sep 2025 13:41:43 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific Date: Wed, 10 Sep 2025 21:41:27 +0100 Message-ID: <20250910204132.319975-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Move the hardcoded switch mode mask definition into the SoC-specific miic_of_data structure. This allows each SoC to define its own mask value rather than relying on a single fixed constant. For RZ/N1 the mask remains GENMASK(4, 0). This is in preparation for adding support for RZ/T2H, where the switch mode mask is GENMASK(2, 0). Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Added a comment about replacing with FIELD_PREP(). - Fixed checkpatch warning to fit within 80 columns. - Added Tested-by tag. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 31d9e0982ad6..f6d9c03d10f0 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -7,6 +7,7 @@ =20 #include #include +#include #include #include #include @@ -23,7 +24,6 @@ #define MIIC_ESID_CODE 0x4 =20 #define MIIC_MODCTRL 0x8 -#define MIIC_MODCTRL_SW_MODE GENMASK(4, 0) =20 #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 @@ -146,6 +146,7 @@ struct miic { * @index_to_string_count: Number of entries in the index_to_string array * @miic_port_start: MIIC port start number * @miic_port_max: Maximum MIIC supported + * @sw_mode_mask: Switch mode mask */ struct miic_of_data { struct modctrl_match *match_table; @@ -157,6 +158,7 @@ struct miic_of_data { u8 index_to_string_count; u8 miic_port_start; u8 miic_port_max; + u8 sw_mode_mask; }; =20 /** @@ -402,6 +404,7 @@ EXPORT_SYMBOL(miic_destroy); =20 static int miic_init_hw(struct miic *miic, u32 cfg_mode) { + u8 sw_mode_mask =3D miic->of_data->sw_mode_mask; int port; =20 /* Unlock write access to accessory registers (cf datasheet). If this @@ -413,8 +416,11 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mod= e) miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); miic_reg_writel(miic, MIIC_PRCMD, 0x0001); =20 + /* TODO: Replace with FIELD_PREP() when compile-time constant + * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. + */ miic_reg_writel(miic, MIIC_MODCTRL, - FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode)); + ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask)); =20 for (port =3D 0; port < miic->of_data->miic_port_max; port++) { miic_converter_enable(miic, port, 0); @@ -582,6 +588,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .index_to_string_count =3D ARRAY_SIZE(index_to_string), .miic_port_start =3D 1, .miic_port_max =3D 5, + .sw_mode_mask =3D GENMASK(4, 0), }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.51.0 From nobody Thu Oct 2 21:41:04 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE10F302752; Wed, 10 Sep 2025 20:41:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; 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Wed, 10 Sep 2025 13:41:44 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:ee64:b92b:f8fd:6cd8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45e0157d68esm320085e9.6.2025.09.10.13.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 13:41:44 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar , Andrew Lunn Subject: [PATCH net-next v3 7/9] net: pcs: rzn1-miic: Add support to handle resets Date: Wed, 10 Sep 2025 21:41:28 +0100 Message-ID: <20250910204132.319975-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add reset-line handling to the RZN1 MIIC driver and move reset configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (=3D 2), add storage for reset_control_bulk_data in struct miic and add reset_ids and reset_count fields to miic_of_data. When reset_ids are present in the OF data, the driver obtains the reset lines with devm_reset_control_bulk_get_exclusive(), deasserts them during probe and registers a devres action to assert them on remove or on error. This change is preparatory work to support the RZ/T2H SoC, which exposes two reset lines for the ETHSS IP. The driver remains backward compatible for platforms that do not provide reset lines. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang --- v2->v3: - Moved reset handling from probe to a separate function miic_reset_control_init() to avoid checkpatch warnings. - Restored Reviewed-by and Tested-by tags. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index f6d9c03d10f0..75009b30084a 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include #include #include =20 @@ -52,6 +54,8 @@ #define MIIC_MODCTRL_CONF_CONV_MAX 6 #define MIIC_MODCTRL_CONF_NONE -1 =20 +#define MIIC_MAX_NUM_RSTS 2 + /** * struct modctrl_match - Matching table entry for convctrl configuration * See section 8.2.1 of manual. @@ -126,12 +130,14 @@ static const char * const index_to_string[] =3D { * @base: base address of the MII converter * @dev: Device associated to the MII converter * @lock: Lock used for read-modify-write access + * @rsts: Reset controls for the MII converter * @of_data: Pointer to OF data */ struct miic { void __iomem *base; struct device *dev; spinlock_t lock; + struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; const struct miic_of_data *of_data; }; =20 @@ -147,6 +153,8 @@ struct miic { * @miic_port_start: MIIC port start number * @miic_port_max: Maximum MIIC supported * @sw_mode_mask: Switch mode mask + * @reset_ids: Reset names array + * @reset_count: Number of entries in the reset_ids array */ struct miic_of_data { struct modctrl_match *match_table; @@ -159,6 +167,8 @@ struct miic_of_data { u8 miic_port_start; u8 miic_port_max; u8 sw_mode_mask; + const char * const *reset_ids; + u8 reset_count; }; =20 /** @@ -523,6 +533,48 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_= cfg) return ret; } =20 +static void miic_reset_control_bulk_assert(void *data) +{ + struct miic *miic =3D data; + int ret; + + ret =3D reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts); + if (ret) + dev_err(miic->dev, "failed to assert reset lines\n"); +} + +static int miic_reset_control_init(struct miic *miic) +{ + const struct miic_of_data *of_data =3D miic->of_data; + struct device *dev =3D miic->dev; + int ret; + u8 i; + + if (!of_data->reset_count) + return 0; + + for (i =3D 0; i < of_data->reset_count; i++) + miic->rsts[i].id =3D of_data->reset_ids[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(dev, of_data->reset_count, + miic->rsts); + if (ret) + return dev_err_probe(dev, ret, + "failed to get bulk reset lines\n"); + + ret =3D reset_control_bulk_deassert(of_data->reset_count, miic->rsts); + if (ret) + return dev_err_probe(dev, ret, + "failed to deassert reset lines\n"); + + ret =3D devm_add_action_or_reset(dev, miic_reset_control_bulk_assert, + miic); + if (ret) + return dev_err_probe(dev, ret, "failed to add reset action\n"); + + return 0; +} + static int miic_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -546,6 +598,10 @@ static int miic_probe(struct platform_device *pdev) if (IS_ERR(miic->base)) return PTR_ERR(miic->base); =20 + ret =3D miic_reset_control_init(miic); + if (ret) + return ret; + ret =3D devm_pm_runtime_enable(dev); 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Wed, 10 Sep 2025 13:41:45 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 8/9] net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock Date: Wed, 10 Sep 2025 21:41:29 +0100 Message-ID: <20250910204132.319975-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so the driver can either perform the traditional global unlock sequence (as used on RZ/N1) or use a different policy for other SoCs (for example RZ/T2H, which does not require leaving registers unlocked). miic_reg_writel() now calls the per-SoC miic_write callback to perform register writes. Provide miic_reg_writel_unlocked() as the default writer and set it for the RZ/N1 OF data so existing platforms keep the same behaviour. Add a miic_unlock_regs() helper that implements the accessory register unlock sequence so the unlock/lock sequence can be reused where needed (for example when a SoC requires explicit unlock/lock around individual accesses). This change is preparatory work for supporting RZ/T2H. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Dropped inlining of miic_unlock_regs(). - Fixed checkpatch warning to fit within 80 columns. - Added Tested-by tag. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 75009b30084a..ef10994d8c11 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -155,6 +155,9 @@ struct miic { * @sw_mode_mask: Switch mode mask * @reset_ids: Reset names array * @reset_count: Number of entries in the reset_ids array + * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed + * before access. + * @miic_write: Function pointer to write a value to a MIIC register */ struct miic_of_data { struct modctrl_match *match_table; @@ -169,6 +172,8 @@ struct miic_of_data { u8 sw_mode_mask; const char * const *reset_ids; u8 reset_count; + bool init_unlock_lock_regs; + void (*miic_write)(struct miic *miic, int offset, u32 value); }; =20 /** @@ -190,11 +195,25 @@ static struct miic_port *phylink_pcs_to_miic_port(str= uct phylink_pcs *pcs) return container_of(pcs, struct miic_port, pcs); } =20 -static void miic_reg_writel(struct miic *miic, int offset, u32 value) +static void miic_unlock_regs(struct miic *miic) +{ + /* Unprotect register writes */ + writel(0x00A5, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); + writel(0xFFFE, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); +} + +static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 va= lue) { writel(value, miic->base + offset); } =20 +static void miic_reg_writel(struct miic *miic, int offset, u32 value) +{ + miic->of_data->miic_write(miic, offset, value); +} + static u32 miic_reg_readl(struct miic *miic, int offset) { return readl(miic->base + offset); @@ -421,10 +440,8 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mod= e) * is going to be used in conjunction with the Cortex-M3, this sequence * will have to be moved in register write */ - miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); - miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); + if (miic->of_data->init_unlock_lock_regs) + miic_unlock_regs(miic); =20 /* TODO: Replace with FIELD_PREP() when compile-time constant * restriction is lifted. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Philipp Zabel , Wolfram Sang , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 9/9] net: pcs: rzn1-miic: Add RZ/T2H MIIC support Date: Wed, 10 Sep 2025 21:41:30 +0100 Message-ID: <20250910204132.319975-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250910204132.319975-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the Renesas RZ/T2H MIIC by defining SoC-specific modctrl match tables, register map, and string representations for converters and ports. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Dropped inlining of miic_lock_regs(). - Added Tested-by tag. v1->v2: - Dropped regx in config description. - Used "renesas,r9a09g077-miic" as compatible for RZ/T2H. --- drivers/net/pcs/Kconfig | 11 +++-- drivers/net/pcs/pcs-rzn1-miic.c | 82 +++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index f6aa437473de..76dbc11d9575 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -26,11 +26,12 @@ config PCS_MTK_LYNXI which is part of MediaTek's SoC and Ethernet switch ICs. =20 config PCS_RZN1_MIIC - tristate "Renesas RZ/N1 MII converter" - depends on OF && (ARCH_RZN1 || COMPILE_TEST) + tristate "Renesas RZ/N1, RZ/N2H, RZ/T2H MII converter" + depends on OF + depends on ARCH_RZN1 || ARCH_R9A09G077 || ARCH_R9A09G087 || COMPILE_TEST help - This module provides a driver for the MII converter that is available - on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in - pass-through mode for MII. + This module provides a driver for the MII converter available on + Renesas RZ/N1, RZ/N2H, and RZ/T2H SoCs. This PCS converts MII to + RMII/RGMII, or can be set in pass-through mode for MII. =20 endmenu diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index ef10994d8c11..885f17c32643 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -21,6 +21,7 @@ #include #include #include +#include =20 #define MIIC_PRCMD 0x0 #define MIIC_ESID_CODE 0x4 @@ -125,6 +126,57 @@ static const char * const index_to_string[] =3D { "CONV5", }; =20 +static struct modctrl_match rzt2h_modctrl_match_table[] =3D { + {0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, + + {0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1, + ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, + + {0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, + ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}}, + + {0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1, + ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}}, + + {0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1, + ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}}, + + {0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT, + ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}} +}; + +static const char * const rzt2h_conf_to_string[] =3D { + [ETHSS_GMAC0_PORT] =3D "GMAC0_PORT", + [ETHSS_GMAC1_PORT] =3D "GMAC1_PORT", + [ETHSS_GMAC2_PORT] =3D "GMAC2_PORT", + [ETHSS_ESC_PORT0] =3D "ETHERCAT_PORT0", + [ETHSS_ESC_PORT1] =3D "ETHERCAT_PORT1", + [ETHSS_ESC_PORT2] =3D "ETHERCAT_PORT2", + [ETHSS_ETHSW_PORT0] =3D "SWITCH_PORT0", + [ETHSS_ETHSW_PORT1] =3D "SWITCH_PORT1", + [ETHSS_ETHSW_PORT2] =3D "SWITCH_PORT2", +}; + +static const char * const rzt2h_index_to_string[] =3D { + "SWITCH_PORTIN", + "CONV0", + "CONV1", + "CONV2", + "CONV3", +}; + +static const char * const rzt2h_reset_ids[] =3D { + "rst", + "crst", +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -204,11 +256,24 @@ static void miic_unlock_regs(struct miic *miic) writel(0x0001, miic->base + MIIC_PRCMD); } =20 +static void miic_lock_regs(struct miic *miic) +{ + /* Protect register writes */ + writel(0x0000, miic->base + MIIC_PRCMD); +} + static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 va= lue) { writel(value, miic->base + offset); } =20 +static void miic_reg_writel_locked(struct miic *miic, int offset, u32 valu= e) +{ + miic_unlock_regs(miic); + writel(value, miic->base + offset); + miic_lock_regs(miic); +} + static void miic_reg_writel(struct miic *miic, int offset, u32 value) { miic->of_data->miic_write(miic, offset, value); @@ -666,7 +731,24 @@ static struct miic_of_data rzn1_miic_of_data =3D { .miic_write =3D miic_reg_writel_unlocked, }; =20 +static struct miic_of_data rzt2h_miic_of_data =3D { + .match_table =3D rzt2h_modctrl_match_table, + .match_table_count =3D ARRAY_SIZE(rzt2h_modctrl_match_table), + .conf_conv_count =3D 5, + .conf_to_string =3D rzt2h_conf_to_string, + .conf_to_string_count =3D ARRAY_SIZE(rzt2h_conf_to_string), + .index_to_string =3D rzt2h_index_to_string, + .index_to_string_count =3D ARRAY_SIZE(rzt2h_index_to_string), + .miic_port_start =3D 0, + .miic_port_max =3D 4, + .sw_mode_mask =3D GENMASK(2, 0), + .reset_ids =3D rzt2h_reset_ids, + .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), + .miic_write =3D miic_reg_writel_locked, +}; + static const struct of_device_id miic_of_mtable[] =3D { + { .compatible =3D "renesas,r9a09g077-miic", .data =3D &rzt2h_miic_of_data= }, { .compatible =3D "renesas,rzn1-miic", .data =3D &rzn1_miic_of_data }, { /* sentinel */ } }; --=20 2.51.0