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Wed, 10 Sep 2025 16:17:40 +0200 From: Wadim Egorov To: , , , , , CC: , , , Subject: [PATCH v2] arm64: dts: ti: k3-am642-phyboard-electra: Add PEB-C-010 Overlay Date: Wed, 10 Sep 2025 16:17:16 +0200 Message-ID: <20250910141716.2133707-1-w.egorov@phytec.de> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: Diagnostix.phytec.de (172.25.0.14) To Florix.phytec.de (172.25.0.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM3PEPF0000A793:EE_|DB9P195MB1306:EE_ X-MS-Office365-Filtering-Correlation-Id: 974a3d2d-2b56-4426-04de-08ddf074cd73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4uyUtmn70HY46d/pEmDZ5bl/9kimeDxnInxSQc/0e6IJLNNnGeOWUewD3pDO?= =?us-ascii?Q?uTyDK8q1mU04Rb5AsxrvAK/cGgfAAakbSj4NwOwP5rT3dOkyZx6+VqjH3wDF?= =?us-ascii?Q?JCwiBBYJryXK7Z6g53CU3t/2QxvOLI/Wp9dwFFI6elfQaAb7IsVxDXeFNd0T?= =?us-ascii?Q?rfqv6a2eFPBI3qcdCi0QdxsaRSvetBqOYffw0zeCii290yMYq+vaIWshpGRR?= =?us-ascii?Q?fyKPdJMok0AP7viBxwXsky0Avpx3BSh9C8FlZGdY7G8Z26Qd2iahpvxybZ0n?= =?us-ascii?Q?yPsFMdNszOFMBvamnK0PeUMGDIgtrIjaU+czjB3UqoeCijTIMxCgqL5fm0OM?= =?us-ascii?Q?j38E8HS4W0phUkS2ifNtDYhW1G77tR4QKEXskfG59Rj/ddZnWlR+JYTwtbxg?= =?us-ascii?Q?JG2ZWu9Ec8lZNN7wTDQUVBrCvX4ZFTegXNoeOjMd0KtHz+87iqJlpB7TJ5d7?= =?us-ascii?Q?+Cdz4RyozHc+eUW6facBzjkJH4rKxM6L7dwE3mcNR0wARUgY4LTmPOu1t0qK?= =?us-ascii?Q?pW3lDcoBzyY7e2uzir//+rcBwmMTZyucEV0d0nXCBJgS3fFqYd/BvoSr43MU?= =?us-ascii?Q?1neOGxEBoW6mZusEv7RRlBspHEaV0atRphpyuCdAqhqQsBWzrfuvZWPWSI5j?= =?us-ascii?Q?0NbxPufAPpybkWDKGoARTS2dgmjKK3wR81JdsqVWz9s0juIHY1G/z+QqzoO3?= =?us-ascii?Q?qC/am7BAKNLlUy0s8iTRoFbOviyo5BV9hL54ErC3BYkKcBLlMktrHonG/zv7?= =?us-ascii?Q?BiiPznp8ibdj7fR6/fRB9u4v30czr2sW30d8RdEHMLhUCOLIwNJABhpgwTF3?= =?us-ascii?Q?1vQAa+AAmFaJfmX2WFM3soHROhDqK4OJnG/cOLx2GBTm8x+ol6XjkYBTZnAS?= =?us-ascii?Q?ettiF0eJgTj/AErqaNW5i5w0FW31FtPAIDjEajsVfE/YbVAxmE0HI7JFqir1?= =?us-ascii?Q?AfQVSOBXnghk3Xaj1tOPd0jYjZHFE8A0/A3mgPcs+JavRLzclhBWa3fbc6PY?= =?us-ascii?Q?p0d+4BAm04k+4E5kCLyCa89QF67KVw6rBgfkdlKTu1dfg/VGwlQplSn7eRIO?= =?us-ascii?Q?n0clQb8FdURJ/M6i6I1g1DC5rfoW/5Jp+kOEtfbNZ8CIC9wgzKceDI5k6xNx?= =?us-ascii?Q?ZVWVnLzjBW96pzS1UXvNUeJmWWt6I5kVyRL/r+rWwckQ2ySSALyYxCeP3by8?= =?us-ascii?Q?BtUdwzLMawB/abO2KjZm0GHYjEvQtEVXlg+A7lOQVaxu3p6XXKF7p7P1UPrN?= =?us-ascii?Q?nHFyThG7MHFR73unTbULHjzRgATDhEbl7SnwT4xopVPCmCswVfy1uyxUZWvK?= =?us-ascii?Q?GFJstbbVI0/oZMkAQcECC87YOOY1uQw4cyfOWriHC70TxT9Vb0p7UrbOSfEb?= =?us-ascii?Q?b1h3FXgb22p4ioVLZNdLplZETcGCxAw11H44ct2Qo1QFcbRfRiHErFZP1LUR?= =?us-ascii?Q?rP7nG542nPfo7srecJqpSXdpOhDZ+Nddiuuqthz2cJshkAOu6YnBtA=3D=3D?= X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:Diagnostix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 14:17:40.9811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 974a3d2d-2b56-4426-04de-08ddf074cd73 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A793.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9P195MB1306 Content-Type: text/plain; charset="utf-8" From: Garrett Giordano The PEB-C-010 expansion board adds two extra 1Gbps ethernet ports to the phyBOARD-Electra-AM64x. Signed-off-by: Garrett Giordano Signed-off-by: Wadim Egorov --- v1: https://lore.kernel.org/lkml/20250113184926.2209094-1-ggiordano@phytec.= com/T/ v2: - Pick up from where Garrett left off - Update aliases to not use node references - Update pinctrl nodes name to match dtschema, *-default-pins --- arch/arm64/boot/dts/ti/Makefile | 3 + .../k3-am642-phyboard-electra-peb-c-010.dtso | 158 ++++++++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-= 010.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index aad9177930e6..98e10b2b0475 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-rdk.= dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.= dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-phyboard-electra-peb-c-010.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -206,6 +207,8 @@ k3-am642-phyboard-electra-pcie-usb2-dtbs :=3D \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs :=3D \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi= 1-uart3.dtbo +k3-am642-phyboard-electra-peb-c-010-dtbs :=3D \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-peb-c-010.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs :=3D \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs :=3D \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dts= o b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso new file mode 100644 index 000000000000..7fc73cfacadb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC America LLC + * Author: Garrett Giordano + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet3 =3D "/icssg1-ethernet/ethernet-ports/port@0"; + ethernet4 =3D "/icssg1-ethernet/ethernet-ports/port@1"; + }; + + icssg1-ethernet { + compatible =3D "ti,am642-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_defaul= t>; + + dmas =3D <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>, /* ingress slice 1 */ + <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */ + <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; + + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + interrupt-parent =3D <&icssg1_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + sram =3D <&oc_sram>; + + ti,iep =3D <&icssg1_iep0>, <&icssg1_iep1>; + ti,mii-g-rt =3D <&icssg1_mii_g_rt>; + ti,mii-rt =3D <&icssg1_mii_rt>; + ti,pa-stats =3D <&icssg1_pa_stats>; + ti,prus =3D <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&= tx_pru1_1>; + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg1_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg1_phy1>; + phy-mode =3D "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + ti,syscon-rgmii-delay =3D <&main_conf 0x4110>; + }; + + icssg1_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg1_phy2>; + phy-mode =3D "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + ti,syscon-rgmii-delay =3D <&main_conf 0x4114>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_mdio_pins_default: icssg1-mdio-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD= 0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD= 1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD= 2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD= 3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_R= XC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX= _CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1= _TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_= TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_= TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1= _TD3 */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_= TX_CTL */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_T= XC */ + >; + }; + + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_R= D0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_R= D1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_= RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_R= D3 */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_R= X_CTL */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_R= XC */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII= 2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2= _TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2= _TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII= 2_TD3 */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2= _TX_CTL */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_= TXC */ + >; + }; +}; + +&icssg1_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg1_mdio_pins_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + icssg1_phy1: ethernet-phy@1 { + reg =3D <0x1>; + rx-fifo-depth =3D ; + tx-fifo-depth =3D ; + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; + ti,clk-output-sel =3D ; + ti,min-output-impedance; + }; + + icssg1_phy2: ethernet-phy@2 { + reg =3D <0x2>; + rx-fifo-depth =3D ; + tx-fifo-depth =3D ; + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; + ti,clk-output-sel =3D ; + ti,min-output-impedance; + }; +}; --=20 2.48.1