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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Conor Dooley , Wolfram Sang Subject: [PATCH v6 1/7] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Date: Wed, 10 Sep 2025 17:02:59 +0300 Message-ID: <20250910140305.541961-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S p= hy bindings") Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - none Changes in v3: - collected tags - rebased on top of latest version of renesas,usb2-phy.yaml; Conor, Geert: I kept your tags; please let me know if you consider it otherwise Changes in v2: - none; this patch is new Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/= Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 179cb4bfc424..2bbec8702a1e 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -118,6 +118,7 @@ allOf: contains: enum: - renesas,usb2-phy-r9a09g057 + - renesas,usb2-phy-r9a08g045 - renesas,rzg2l-usb2-phy then: properties: --=20 2.43.0 From nobody Thu Oct 2 21:56:54 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31BA2322522 for ; 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Christophe JAILLET , Wolfram Sang , Claudiu Beznea Subject: [PATCH v6 2/7] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Date: Wed, 10 Sep 2025 17:03:00 +0300 Message-ID: <20250910140305.541961-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christophe JAILLET If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. While at it, drop struct rcar_gen3_chan::rstc as it is not used aymore. Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initiali= ze the bus") Signed-off-by: Christophe JAILLET Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang [claudiu.beznea: removed "struct reset_control *rstc =3D data;" from rcar_gen3_reset_assert(), dropped struct rcar_gen3_chan::rstc] Signed-off-by: Claudiu Beznea --- Changes in v6: - dropped struct rcar_gen3_chan::rstc; updated the patch description to reflect it - collected tags Changes in v5: - none Changes in v4: - none Changes in v3: - collected tags Changes in v2: - none; this patch is new; re-spinned the Christophe's work at https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR= 01MB11332.jpnprd01.prod.outlook.com/ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas= /phy-rcar-gen3-usb2.c index 3f6b480e1092..a38ead7c8055 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -134,7 +134,6 @@ struct rcar_gen3_chan { struct extcon_dev *extcon; struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; - struct reset_control *rstc; struct work_struct work; spinlock_t lock; /* protects access to hardware and driver data structure= . */ enum usb_dr_mode dr_mode; @@ -771,21 +770,31 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct = device_node *np) return candidate; } =20 +static void rcar_gen3_reset_assert(void *data) +{ + reset_control_assert(data); +} + static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) { struct device *dev =3D channel->dev; + struct reset_control *rstc; int ret; u32 val; =20 - channel->rstc =3D devm_reset_control_array_get_shared(dev); - if (IS_ERR(channel->rstc)) - return PTR_ERR(channel->rstc); + rstc =3D devm_reset_control_array_get_shared(dev); + if (IS_ERR(rstc)) + return PTR_ERR(rstc); =20 ret =3D pm_runtime_resume_and_get(dev); if (ret) return ret; =20 - ret =3D reset_control_deassert(channel->rstc); + ret =3D reset_control_deassert(rstc); + if (ret) + goto rpm_put; + + ret =3D devm_add_action_or_reset(dev, rcar_gen3_reset_assert, rstc); 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v6 3/7] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Date: Wed, 10 Sep 2025 17:03:01 +0300 Message-ID: <20250910140305.541961-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas USB PHY hardware block needs to have the PWRRDY bit in the system controller set before applying any other settings. The PWRRDY bit must be controlled during power-on, power-off, and system suspend/resume sequences as follows: - during power-on/resume, it must be set to zero before enabling clocks and modules - during power-off/suspend, it must be set to one after disabling clocks and modules Add the renesas,sysc-pwrrdy device tree property, which allows the reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system controller PWRRDY bit at the appropriate time. Along with it add a new compatible for the RZ/G3S SoC. Reviewed-by: Rob Herring (Arm) Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - fixed description formatting - collected tags Changes in v4: - dropped blank line from compatible section - s/renesas,sysc-signals/renesas,sysc-pwrrdy/g - dropped description from renesas,sysc-pwrrdy - updated description of renesas,sysc-pwrrdy items - updated patch description Changes in v3: - none; this patch is new .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 41 ++++++++++++++++--- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-c= trl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctr= l.yaml index b0b20af15313..c83469a1b379 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -15,12 +15,14 @@ description: =20 properties: compatible: - items: - - enum: - - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - - renesas,r9a07g054-usbphy-ctrl # RZ/V2L - - const: renesas,rzg2l-usbphy-ctrl + oneOf: + - items: + - enum: + - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five + - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - const: renesas,rzg2l-usbphy-ctrl + - const: renesas,r9a08g045-usbphy-ctrl # RZ/G3S =20 reg: maxItems: 1 @@ -48,6 +50,20 @@ properties: $ref: /schemas/regulator/regulator.yaml# unevaluatedProperties: false =20 + renesas,sysc-pwrrdy: + description: + The system controller PWRRDY indicates to the USB PHY if the power s= upply + is ready. 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:28 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v6 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY Date: Wed, 10 Sep 2025 17:03:02 +0300 Message-ID: <20250910140305.541961-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. On power-on the USB PWRRDY signal need to be de-asserted before enabling clock and switching the module to normal state (through MSTOP support). The power-on configuration sequence must be: 1/ PWRRDY=3D0 2/ CLK_ON=3D1 3/ MSTOP=3D0 On power-off the configuration sequence should be: 1/ MSTOP=3D1 2/ CLK_ON=3D0 3/ PWRRDY=3D1 The CLK_ON and MSTOP functionalities are controlled by clock drivers. After long discussions with the internal HW team, it has been confirmed that the HW connection b/w USB PHY block, the USB channels, the system controller, clock, MSTOP, PWRRDY signal is as follows: =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82 =E2= =94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK0_ON =E2=94=82 USB CH0 =E2= =94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90= =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK2_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82host control= ler registers =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82fu= nction controller registers=E2=94=82 =E2=94=82 =E2=94=82 PHY0 =E2=94=82=E2=97=84=E2=94=80=E2= =94=80=E2=94=A4=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 USB PHY =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTO= P{6, 5}_ON =E2=94=82=E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =90 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=90 =E2=94=82=E2=94=82USHPHY control=E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=82 registers =E2=94=82 =E2=94=82 PHY1 =E2=94=82 =E2= =94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82=E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =98 =E2=94=82 =E2=94=82=E2=97=84=E2=94=80=E2=94=80=E2=94=A4 USB = CH1 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=8C=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=90 =E2=94=82=E2=97=84=E2=94=80=E2=94=80 CPG_CLKON_USB.CLK1_ON =E2=94=94=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82=E2=94=82 host controller registers = =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82=E2=94=94= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=96=B2=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82 =E2=94=82 =E2=94=82 =E2=94= =82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MS= TOP.MSTOP7_ON =E2=94=82PWRRDY =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 CPG_CLK_ON_USB.CLK3_ON =E2=94=82 =E2=94=82 =E2=94=82 CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON =E2=94=82 =E2=94=8C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 =E2=94=82SYSC=E2=94=82 =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=98 where: - CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X of different USB blocks, X in {0, 1, 2, 3} - CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the MSTOP of different USB blocks, X in {4, 5, 6, 7} - USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used by the USB CH0, USB CH1 - SYSC is the system controller block controlling the PWRRDY signal - USB CHx are individual USB block with host and function capabilities (USB CH0 have both host and function capabilities, USB CH1 has only host capabilities) The USBPHY control registers are controlled though the reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver. The connection b/w the system controller and the USB PHY CTRL driver is implemented through the renesas,sysc-pwrrdy device tree property proposed in this patch. This property specifies the register offset and the bitmask required to control the PWRRDY signal. Since the USB PHY CTRL driver needs to be probed before any other USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively to it. This guarantees the correct configuration sequence between clocks, MSTOP bits, and the PWRRDY bit. At the same time, changes are kept minimal by avoiding modifications to the USB PHY driver to also handle the PWRRDY itself. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - used syscon_regmap_lookup_by_phandle_args() to simplify the code - collected tags Changes in v5: - none Changes in v4: - updated patch description - updated rzg2l_usbphy_ctrl_pwrrdy_init() to map directly the "renesas,sysc-pwrrdy" as the SYSC signal abstraction was dropped in this version, along with rz_sysc_get_signal_map() - dropped priv member of rzg2l_usbphy_ctrl_pwrrdy_init() as it is not needed in this version - shift left !power_on with pwrrdy->mask as this is how the regmap_update_bits() needs the last member to be - selected MFD_SYSCON Changes in v3: - none; this patch is new drivers/reset/Kconfig | 1 + drivers/reset/reset-rzg2l-usbphy-ctrl.c | 61 +++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 78b7078478d4..329730cbcfb9 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -237,6 +237,7 @@ config RESET_RASPBERRYPI config RESET_RZG2L_USBPHY_CTRL tristate "Renesas RZ/G2L USBPHY control driver" depends on ARCH_RZG2L || COMPILE_TEST + select MFD_SYSCON help Support for USBPHY Control found on RZ/G2L family. It mainly controls reset and power down of the USB/PHY. diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index 8a7f167e405e..c58bf19993c1 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 #define RESET 0x000 #define VBENCTL 0x03c @@ -41,6 +42,18 @@ struct rzg2l_usbphy_ctrl_priv { =20 #define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rc= dev) =20 +/** + * struct rzg2l_usbphy_ctrl_pwrrdy - SYSC PWRRDY signal descriptor + * @regmap: SYSC regmap + * @offset: offset into the SYSC address space for accessing PWRRDY + * @mask: mask into the register at offset for accessing PWRRDY + */ +struct rzg2l_usbphy_ctrl_pwrrdy { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev, unsigned long id) { @@ -91,6 +104,8 @@ static int rzg2l_usbphy_ctrl_status(struct reset_control= ler_dev *rcdev, return !!(readl(priv->base + RESET) & port_mask); } =20 +#define RZG2L_USBPHY_CTRL_PWRRDY 1 + static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, { /* Sentinel */ } @@ -110,6 +125,48 @@ static const struct regmap_config rzg2l_usb_regconf = =3D { .max_register =3D 1, }; =20 +static void rzg2l_usbphy_ctrl_set_pwrrdy(struct rzg2l_usbphy_ctrl_pwrrdy *= pwrrdy, + bool power_on) +{ + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, + !power_on << pwrrdy->mask); +} + +static void rzg2l_usbphy_ctrl_pwrrdy_off(void *data) +{ + rzg2l_usbphy_ctrl_set_pwrrdy(data, false); +} + +static int rzg2l_usbphy_ctrl_pwrrdy_init(struct device *dev) +{ + struct rzg2l_usbphy_ctrl_pwrrdy *pwrrdy; + struct regmap *regmap; + const int *data; + u32 args[2]; + + data =3D device_get_match_data(dev); + if (data !=3D (int *)RZG2L_USBPHY_CTRL_PWRRDY) + return 0; + + regmap =3D syscon_regmap_lookup_by_phandle_args(dev->of_node, + "renesas,sysc-pwrrdy", + ARRAY_SIZE(args), args); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pwrrdy =3D devm_kzalloc(dev, sizeof(*pwrrdy), GFP_KERNEL); + if (!pwrrdy) + return -ENOMEM; + + pwrrdy->regmap =3D regmap; + pwrrdy->offset =3D args[0]; + pwrrdy->mask =3D args[1]; + + rzg2l_usbphy_ctrl_set_pwrrdy(pwrrdy, true); + + return devm_add_action_or_reset(dev, rzg2l_usbphy_ctrl_pwrrdy_off, pwrrdy= ); +} + static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -132,6 +189,10 @@ static int rzg2l_usbphy_ctrl_probe(struct platform_dev= ice *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); =20 + error =3D rzg2l_usbphy_ctrl_pwrrdy_init(dev); + if (error) + return error; + priv->rstc =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(priv->rstc)) return dev_err_probe(dev, PTR_ERR(priv->rstc), --=20 2.43.0 From nobody Thu Oct 2 21:56:54 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C266326D4D for ; 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v6 5/7] reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC Date: Wed, 10 Sep 2025 17:03:03 +0300 Message-ID: <20250910140305.541961-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY signal from the system controller. Add support for the Renesas RZ/G3S SoC. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - none Changes in v3: - none; this patch is new drivers/reset/reset-rzg2l-usbphy-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-= rzg2l-usbphy-ctrl.c index c58bf19993c1..a7fbf5c50940 100644 --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c @@ -108,6 +108,10 @@ static int rzg2l_usbphy_ctrl_status(struct reset_contr= oller_dev *rcdev, =20 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] =3D { { .compatible =3D "renesas,rzg2l-usbphy-ctrl" }, + { + .compatible =3D "renesas,r9a08g045-usbphy-ctrl", + .data =3D (void *)RZG2L_USBPHY_CTRL_PWRRDY + }, { /* Sentinel */ } }; MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table); --=20 2.43.0 From nobody Thu Oct 2 21:56:54 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97B16321444 for ; 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v6 6/7] arm64: dts: renesas: r9a08g045: Add USB support Date: Wed, 10 Sep 2025 17:03:04 +0300 Message-ID: <20250910140305.541961-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - dropped renesas,sysc-signals from usb2_phy0, usb2_phy1 nodes - s/renesas,sysc-signals/renesas,sysc-pwrrdy/g Changes in v3: - changed the nodes order to keep similar nodes toghether Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise=20 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 16e6ac614417..ab29b8365e26 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -717,6 +717,124 @@ eth1: ethernet@11c40000 { status =3D "disabled"; }; =20 + phyrst: usbphy-ctrl@11e00000 { + compatible =3D "renesas,r9a08g045-usbphy-ctrl"; + reg =3D <0 0x11e00000 0 0x10000>; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets =3D <&cpg R9A08G045_USB_PRESETN>; + power-domains =3D <&cpg>; + #reset-cells =3D <1>; + renesas,sysc-pwrrdy =3D <&sysc 0xd70 0x1>; + status =3D "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name =3D "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e10000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ohci1: usb@11e30000 { + compatible =3D "generic-ohci"; + reg =3D <0 0x11e30000 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 1>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci0: usb@11e10100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e10100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys =3D <&usb2_phy0 2>; + phy-names =3D "usb"; + companion =3D <&ohci0>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + ehci1: usb@11e30100 { + compatible =3D "generic-ehci"; + reg =3D <0 0x11e30100 0 0x100>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys =3D <&usb2_phy1 2>; + phy-names =3D "usb"; + companion =3D <&ohci1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e10200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible =3D "renesas,usb2-phy-r9a08g045"; + reg =3D <0 0x11e30200 0 0x700>; + interrupts =3D ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets =3D <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells =3D <1>; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + + hsusb: usb@11e20000 { + compatible =3D "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg =3D <0 0x11e20000 0 0x10000>; + interrupts =3D , + , + , + ; + clocks =3D <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets =3D <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait =3D <7>; + phys =3D <&usb2_phy0 3>; + phy-names =3D "usb"; + power-domains =3D <&cpg>; + status =3D "disabled"; + }; + gic: interrupt-controller@12400000 { compatible =3D "arm,gic-v3"; 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([82.78.167.139]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45df804bce3sm29523875e9.0.2025.09.10.07.03.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:03:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang Subject: [PATCH v6 7/7] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Wed, 10 Sep 2025 17:03:05 +0300 Message-ID: <20250910140305.541961-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> References: <20250910140305.541961-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable USB support (host, device, USB PHYs). Reviewed-by: Geert Uytterhoeven Tested-by: Wolfram Sang Signed-off-by: Claudiu Beznea --- Changes in v6: - collected tags Changes in v5: - none Changes in v4: - none Changes in v3: - collected tags Changes in v2: - this was patch 15/16 in v1: - dropped sysc enablement as it is now done in SoC dtsi file arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 5e044a4d0234..5586dd43c4d5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -92,6 +92,20 @@ &audio_clk2 { clock-frequency =3D <12288000>; }; =20 +&ehci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&hsusb { + dr_mode =3D "otg"; + status =3D "okay"; +}; + &i2c0 { status =3D "okay"; =20 @@ -132,6 +146,15 @@ power-monitor@44 { }; }; =20 +&ohci0 { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + &pinctrl { audio_clock_pins: audio-clock { pins =3D "AUDIO_CLK1", "AUDIO_CLK2"; @@ -207,6 +230,27 @@ ssi3_pins: ssi3 { , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + peri { + pinmux =3D , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux =3D ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux =3D , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status =3D "okay"; }; =20 &scif0 { @@ -242,3 +286,16 @@ &ssi3 { pinctrl-0 =3D <&ssi3_pins>, <&audio_clock_pins>; status =3D "okay"; }; + +&usb2_phy0 { + pinctrl-0 =3D <&usb0_pins>; + pinctrl-names =3D "default"; + vbus-supply =3D <&usb0_vbus_otg>; + status =3D "okay"; +}; + +&usb2_phy1 { + pinctrl-0 =3D <&usb1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.43.0