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Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- drivers/input/touchscreen/imx6ul_tsc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index 6ac8fa84ed9f..c2c6e50efc54 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -55,7 +55,7 @@ #define ADC_TIMEOUT msecs_to_jiffies(100) =20 /* TSC registers */ -#define REG_TSC_BASIC_SETING 0x00 +#define REG_TSC_BASIC_SETTING 0x00 #define REG_TSC_PRE_CHARGE_TIME 0x10 #define REG_TSC_FLOW_CONTROL 0x20 #define REG_TSC_MEASURE_VALUE 0x30 @@ -192,7 +192,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) =20 basic_setting |=3D tsc->measure_delay_time << 8; basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; - writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); + writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); 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[82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07833a4e37sm172523066b.76.2025.09.10.06.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 06:59:21 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Dmitry Torokhov , Fabio Estevam , Haibo Chen , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [RESEND PATCH 2/4] dt-bindings: input: touchscreen: fsl,imx6ul-tsc: add fsl,glitch-threshold Date: Wed, 10 Sep 2025 15:58:36 +0200 Message-ID: <20250910135916.3939502-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> References: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for glitch threshold configuration. A detected signal is valid only if it lasts longer than the set threshold; otherwise, it is regarded as a glitch. Signed-off-by: Dario Binacchi --- .../input/touchscreen/fsl,imx6ul-tsc.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul= -tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-= tsc.yaml index 678756ad0f92..2fee2940213f 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml @@ -62,6 +62,23 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] =20 + fsl,glitch-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [ 0, 1, 2, 3 ] + description: | + Indicates the glitch threshold. The threshold is defined by number + of clock cycles. A detect signal is only valid if it is exist longer + than threshold; otherwise, it is regarded as a glitch. + 0: Normal function: 8191 clock cycles + Low power mode: 9 clock cycles + 1: Normal function: 4095 clock cycles + Low power mode: 7 clock cycles + 2: Normal function: 2047 clock cycles + Low power mode: 5 clock cycles + 3: Normal function: 1023 clock cycles + Low power mode: 3 clock cycles + required: - compatible - reg @@ -94,4 +111,5 @@ examples: measure-delay-time =3D <0xfff>; pre-charge-time =3D <0xffff>; touchscreen-average-samples =3D <32>; + fsl,glitch-threshold =3D <2>; }; --=20 2.43.0 From nobody Thu Oct 2 21:55:27 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E899132255C for ; Wed, 10 Sep 2025 13:59:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757512768; cv=none; b=iEHh84aFvyZUlNymHbvQmM8WexKAtqxFKUm6clwmyCKE+jIjGVC7PH2ztrc2h3rkisBgqqo7SCyYAK4pj8PPZ+8frKS2dfOP59kMxDUwqr9kyNrFI4BTHBa322mvl/kGVmy89rNSmRsq/tE8Mg9ZQAXtZlKenv69yK7pvfeFjao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757512768; c=relaxed/simple; bh=mAnzVAui+Zh2pgPs+xFJHjOfsAlD+iZi1XelY8rp6FQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mECDo0+ZVDaQyVYi/4TgjOSWH9dfJlj5StmK15VfZ0ZtkAxR0IMKq0H2VpDDn970L8PU+KHyVa/5+8D6tfW+3WjwcxPnXFGo0qAw+h3sOOz0ufE05SPrwT5xDGLx4HNzj73/v+zJNSxPFhcLB/z8oYMzY7TQo+/N39Vark48HIU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=qCLJgAmD; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="qCLJgAmD" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-afcb7a16441so1013247166b.2 for ; Wed, 10 Sep 2025 06:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757512763; x=1758117563; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B0R5rRW0Dwv8g9EBflVK6bi6TKX/71M89TmluJsUG60=; b=qCLJgAmDSQTG82uJC/Z/l9e7PThzJ+Bqz6hwkcY03BJ4/6l17K7/AJiUv2L+iRZyNM cTeRm+BBGjOLeizkGcmikkm0WDX4PoUmHHHFx2SR7Z7c57aweqdugaaQUVIiM/TQPl8g e+DvS1GszZtg5bk9WyjVzNh8Rhl/pb2FQD9+4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757512763; x=1758117563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B0R5rRW0Dwv8g9EBflVK6bi6TKX/71M89TmluJsUG60=; b=OTBCh7sk8al/oGBwfv5CIBUL01bpKJYBpRaECqYpbN+bQntbEqz+do10Gx9b2h7LF2 jzibLAkjsVp0XPXflK4GC4ny3ol7H/YBd7Gj6tA2Q30LGMcY6UaLOcqNPOtuK7d8dsso 53BaCE6G0MpAOorYY6XOQo/Rb0sv7RLMy6sjqAiNkDI6zxpjqXC0lKv69j4mJ8GfxTRp 2UmTnDJ9mVjmAMucFMiKAKwx8EwMVkuc78Pfa9pFS21wLs/Ey9RsvLMLL2jjx+MCxldY c/d6yO1d1UhFoEz+CVUdeT8zJ73+q/AQdPXr1f1ONs22sgACpbqRM10vJ+tSe0XAH8dy Zddw== X-Gm-Message-State: AOJu0YyKAN474PbkgfRiFMTmhZp+GEkVJCYou1+I5KGhbQRy2krYZXLs MJe7TvA3PoOx/9nMjDaNkdr6Um4n6tuQQ1r70FVZ4zooBJgfnOzVyiSVk4jJuNodCZRbO4U0OBj 0o1Rq X-Gm-Gg: ASbGnctg+ynEqxOk98W3Qhkhw9PH3QpXsVu7U6YnufZdqie3QWIELIZBTSJRWcV3Hr6 PlErS4D5/oC3kxLk0AiWMdZTLUk2bDtj/Hq/rkzB0HyfWjhekmf+cB1r/maRv3ZQOhqlLyDQhWg hDUgHR858u67+rW9XJo9imWc9pPNMVGSjtHtTgVf6fwI9io3Fyj4SnIbCMH/c8HPfH8/vGCj3Oc EcazQ6kl6Dgb5AgIZkwA597+EiKyNAvt4FjL11wgwE4EIxXTUx8th8mbJ0vRHgXxuZXnK8AsVVP wTwu8C9ZCRRP/UoX5lkL3fWRDwtY5bbWlZ2IP6Hib9AZxfmocvcnbuSmVqCgOvAYTg0GMh3KY9F ZI8HqlHV3mo84mRl2mbC3Ch5yv9fX0A+T0dV7hbAG3FKf97qEL4dY6hTHTyu+5pBdBhijuxH9VL h2k2N+Ib5/S5xnvZphDWsQm4eXTzb1QYa5WPgkr71dvWRQ3HvEAUvSYgFsfFG55Ey5 X-Google-Smtp-Source: AGHT+IHdweJVzi0li6Hab/FnHQdGRXCIG6Nx0PPgMqfpJ3S+dtaqUO7p5/p1o4bXf82vFHRmV8q+6Q== X-Received: by 2002:a17:907:1c25:b0:b04:5c90:8013 with SMTP id a640c23a62f3a-b04b173763amr1525363866b.45.1757512762970; Wed, 10 Sep 2025 06:59:22 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07833a4e37sm172523066b.76.2025.09.10.06.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 06:59:22 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [RESEND PATCH 3/4] Input: imx6ul_tsc - set glitch threshold by DTS property Date: Wed, 10 Sep 2025 15:58:37 +0200 Message-ID: <20250910135916.3939502-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> References: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set the glitch threshold previously hardcoded in the driver. The change is backward compatible. Signed-off-by: Dario Binacchi --- drivers/input/touchscreen/imx6ul_tsc.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index c2c6e50efc54..a6066643bd48 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -74,7 +75,8 @@ #define MEASURE_INT_EN 0x1 #define MEASURE_SIG_EN 0x1 #define VALID_SIG_EN (0x1 << 8) -#define DE_GLITCH_2 (0x2 << 29) +#define DE_GLITCH_MASK GENMASK(30, 29) +#define DE_GLITCH_DEF 0x02 #define START_SENSE (0x1 << 12) #define TSC_DISABLE (0x1 << 16) #define DETECT_MODE 0x2 @@ -92,6 +94,7 @@ struct imx6ul_tsc { u32 pre_charge_time; bool average_enable; u32 average_select; + u32 de_glitch; =20 struct completion completion; }; @@ -188,13 +191,15 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) { u32 basic_setting =3D 0; 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Wed, 10 Sep 2025 06:59:24 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07833a4e37sm172523066b.76.2025.09.10.06.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 06:59:23 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [RESEND PATCH 4/4] Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros Date: Wed, 10 Sep 2025 15:58:38 +0200 Message-ID: <20250910135916.3939502-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> References: <20250910135916.3939502-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- drivers/input/touchscreen/imx6ul_tsc.c | 88 ++++++++++++++------------ 1 file changed, 48 insertions(+), 40 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index a6066643bd48..e74999c5e22f 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -21,25 +21,23 @@ #include =20 /* ADC configuration registers field define */ -#define ADC_AIEN (0x1 << 7) +#define ADC_AIEN BIT(7) +#define ADC_ADCH_MASK GENMASK(4, 0) #define ADC_CONV_DISABLE 0x1F -#define ADC_AVGE (0x1 << 5) -#define ADC_CAL (0x1 << 7) -#define ADC_CALF 0x2 -#define ADC_12BIT_MODE (0x2 << 2) -#define ADC_CONV_MODE_MASK (0x3 << 2) +#define ADC_AVGE BIT(5) +#define ADC_CAL BIT(7) +#define ADC_CALF BIT(1) +#define ADC_CONV_MODE_MASK GENMASK(3, 2) +#define ADC_12BIT_MODE 0x2 #define ADC_IPG_CLK 0x00 -#define ADC_INPUT_CLK_MASK 0x3 -#define ADC_CLK_DIV_8 (0x03 << 5) -#define ADC_CLK_DIV_MASK (0x3 << 5) -#define ADC_SHORT_SAMPLE_MODE (0x0 << 4) -#define ADC_SAMPLE_MODE_MASK (0x1 << 4) -#define ADC_HARDWARE_TRIGGER (0x1 << 13) -#define ADC_AVGS_SHIFT 14 -#define ADC_AVGS_MASK (0x3 << 14) +#define ADC_INPUT_CLK_MASK GENMASK(1, 0) +#define ADC_CLK_DIV_8 0x03 +#define ADC_CLK_DIV_MASK GENMASK(6, 5) +#define ADC_SAMPLE_MODE BIT(4) +#define ADC_HARDWARE_TRIGGER BIT(13) +#define ADC_AVGS_MASK GENMASK(15, 14) #define SELECT_CHANNEL_4 0x04 #define SELECT_CHANNEL_1 0x01 -#define DISABLE_CONVERSION_INT (0x0 << 7) =20 /* ADC registers */ #define REG_ADC_HC0 0x00 @@ -66,20 +64,26 @@ #define REG_TSC_DEBUG_MODE 0x70 #define REG_TSC_DEBUG_MODE2 0x80 =20 +/* TSC_MEASURE_VALUE register field define */ +#define X_VALUE_MASK GENMASK(27, 16) +#define Y_VALUE_MASK GENMASK(11, 0) + /* TSC configuration registers field define */ -#define DETECT_4_WIRE_MODE (0x0 << 4) -#define AUTO_MEASURE 0x1 -#define MEASURE_SIGNAL 0x1 -#define DETECT_SIGNAL (0x1 << 4) -#define VALID_SIGNAL (0x1 << 8) -#define MEASURE_INT_EN 0x1 -#define MEASURE_SIG_EN 0x1 -#define VALID_SIG_EN (0x1 << 8) +#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8) +#define DETECT_5_WIRE_MODE BIT(4) +#define AUTO_MEASURE BIT(0) +#define MEASURE_SIGNAL BIT(0) +#define DETECT_SIGNAL BIT(4) +#define VALID_SIGNAL BIT(8) +#define MEASURE_INT_EN BIT(0) +#define MEASURE_SIG_EN BIT(0) +#define VALID_SIG_EN BIT(8) #define DE_GLITCH_MASK GENMASK(30, 29) #define DE_GLITCH_DEF 0x02 -#define START_SENSE (0x1 << 12) -#define TSC_DISABLE (0x1 << 16) +#define START_SENSE BIT(12) +#define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 +#define STATE_MACHINE_MASK GENMASK(22, 20) =20 struct imx6ul_tsc { struct device *dev; @@ -115,19 +119,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc) =20 adc_cfg =3D readl(tsc->adc_regs + REG_ADC_CFG); adc_cfg &=3D ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK); - adc_cfg |=3D ADC_12BIT_MODE | ADC_IPG_CLK; - adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK); - adc_cfg |=3D ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE; + adc_cfg |=3D FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) | + FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK); + adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE); + adc_cfg |=3D FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8); if (tsc->average_enable) { adc_cfg &=3D ~ADC_AVGS_MASK; - adc_cfg |=3D (tsc->average_select) << ADC_AVGS_SHIFT; + adc_cfg |=3D FIELD_PREP(ADC_AVGS_MASK, tsc->average_select); } adc_cfg &=3D ~ADC_HARDWARE_TRIGGER; writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); =20 /* enable calibration interrupt */ adc_hc |=3D ADC_AIEN; - adc_hc |=3D ADC_CONV_DISABLE; + adc_hc |=3D FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE); writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); =20 /* start ADC calibration */ @@ -167,19 +172,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) { u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4; =20 - adc_hc0 =3D DISABLE_CONVERSION_INT; + adc_hc0 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); =20 - adc_hc1 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_4; + adc_hc1 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4); writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); =20 - adc_hc2 =3D DISABLE_CONVERSION_INT; + adc_hc2 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); =20 - adc_hc3 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_1; + adc_hc3 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1); writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); =20 - adc_hc4 =3D DISABLE_CONVERSION_INT; + adc_hc4 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); } =20 @@ -194,8 +201,9 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) u32 debug_mode2; u32 start; =20 - basic_setting |=3D tsc->measure_delay_time << 8; - basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; + basic_setting |=3D FIELD_PREP(MEASURE_DELAY_TIME_MASK, + tsc->measure_delay_time); + basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, tsc->de_glitch); @@ -255,7 +263,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc) =20 usleep_range(200, 400); debug_mode2 =3D readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2); - state_machine =3D (debug_mode2 >> 20) & 0x7; + state_machine =3D FIELD_GET(STATE_MACHINE_MASK, debug_mode2); } while (state_machine !=3D DETECT_MODE); =20 usleep_range(200, 400); @@ -283,8 +291,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id) =20 if (status & MEASURE_SIGNAL) { value =3D readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE); - x =3D (value >> 16) & 0x0fff; - y =3D value & 0x0fff; + x =3D FIELD_GET(X_VALUE_MASK, value); + y =3D FIELD_GET(Y_VALUE_MASK, value); =20 /* * In detect mode, we can get the xnur gpio value, --=20 2.43.0