From nobody Thu Oct 2 21:56:26 2025 Received: from out30-98.freemail.mail.aliyun.com (out30-98.freemail.mail.aliyun.com [115.124.30.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D62973081A0; Wed, 10 Sep 2025 09:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.98 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496843; cv=none; b=bsA4xOxe2Xj403og2kJNrsc0nJKt3otGDKnh6BGJ214QzUUVNA3UavqTKA262N8EgcJuLevbiDRPuNVrr2R3yf4HIr0bT03aHlbaMhXDWWE109++5UCyFvWzJSlur1m6qmCA/vxudp7WHzkoWHTt/JwOoSnu+XmFxOgiyPfKUT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496843; c=relaxed/simple; bh=W0kJHMJPyXLBD9AsLRJEuzaG4BOBAaE1iErjmIi/gbU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PtsGMS8hGk9DrmtTq2tHg4VC3YIZMLymVb/GgaKBd4Lv56RTGqWGbtGWe8DzvJzttWfIB7pOJzK9lu6HvW443M4opHO9HBnuXHuFysefW4jmI20B+dXzg7iXXzV2bMn8uQkCh7sKHgOGcgLCAehxh2alhXZRreMkDU9uSl3h7a4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=pUlEO+NC; arc=none smtp.client-ip=115.124.30.98 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="pUlEO+NC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757496836; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=CkbLKay4KW6gGBpr5vlMMMrvH8ODs320iGf0xAuSytA=; b=pUlEO+NC9Qf5fV4RpDucAS4o6cIMdxsU34kTlWsq/ZUnV2nfhjDIxIXJ6Z8oIBDzREZG++uokHqrm3oIqaY3pa3MU9Fg4qVQPi5fUWooMdbyvVXYCCkra/TFae+befS25K4hOk5EUSGxOHZyjAGcTr9qaIghhfw83yFz70dv9+I= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0WnhhBo9_1757496834 cluster:ay36) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 17:33:56 +0800 From: Ruidong Tian To: xueshuai@linux.alibaba.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: james.morse@arm.com, tony.luck@intel.com, cleger@rivosinc.com, hchauhan@ventanamicro.com, tianruidong@linux.alibaba.com Subject: [RFC PATCH 1/5] riscv: Define ioremap_cache for RISC-V Date: Wed, 10 Sep 2025 17:33:43 +0800 Message-Id: <20250910093347.75822-2-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20250910093347.75822-1-tianruidong@linux.alibaba.com> References: <20250910093347.75822-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Himanshu Chauhan bert and einj drivers use ioremap_cache for mapping entries but ioremap_cache is not defined for RISC-V. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/io.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index a0e51840b9db..56eca6b3031f 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -30,6 +30,9 @@ #define PCI_IOBASE ((void __iomem *)PCI_IO_START) #endif /* CONFIG_MMU */ =20 +#define ioremap_cache(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), __pgprot(_PAGE_KERNEL))) + /* * Emulation routines for the port-mapped IO space used by some PCI driver= s. * These are defined as being "fully synchronous", but also "not guarantee= d to --=20 2.43.7 From nobody Thu Oct 2 21:56:26 2025 Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 747CB3128A4; Wed, 10 Sep 2025 09:34:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.113 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496846; cv=none; b=pphwZZ7IOCjOL5Lmc5LXKlPD/0u2KzRJC1m/xU0+IKErfqi0vjq05Z2vIvBpiE449B2pgppOWmFfThKKtHe5IYXTLZTY3wuvdBSn2YQi6ZSvwikot2vr0rudRfsncHB+cRaObg61TqVrSz6fBCj7bwhvPn98522QzM/+y7kH8f0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496846; c=relaxed/simple; bh=jp6L8c0EHB1gymGU5flE9AdnVKMkvLGb58m6qWm61n4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S8cw/6gZJ+o76i0TbEbr9e69FsIiCoGwbevLQYN3yaepm/9jmMLrhIxxADCYWvEKTqDQ6CVWzvOkgGFfemKv90/1cZX8U78WCxlUd2QI0cQLW2Pkp0X1a+XxQxisSmVkDhXSBMxufDR9nSk+g4Icqilyi7qassndW/rHkc+2nz0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=PgcvKRnv; arc=none smtp.client-ip=115.124.30.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="PgcvKRnv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757496841; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=H6tZbk8xd14arH4x+y5nLcp4ATXMokGEomrYYieeMvA=; b=PgcvKRnv7G0jJod/J1p6ua68GW2fdQHDao40/aPR1UNAPS5YTnmF49hU6krqCh0CcbhQkGZ7m7eCSgmXHIPE1dHi6iT9skEfXEEa61J4XUq2kte7UD28IiqXwWhw4j3gXCt3ce/HXl+PagimR4TK8/ph/jNNMkXG+Oa3q3Ev9Zo= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0WnhhBon_1757496838 cluster:ay36) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 17:34:00 +0800 From: Ruidong Tian To: xueshuai@linux.alibaba.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: james.morse@arm.com, tony.luck@intel.com, cleger@rivosinc.com, hchauhan@ventanamicro.com, tianruidong@linux.alibaba.com Subject: [RFC PATCH 2/5] riscv: Define arch_apei_get_mem_attribute for RISC-V Date: Wed, 10 Sep 2025 17:33:44 +0800 Message-Id: <20250910093347.75822-3-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20250910093347.75822-1-tianruidong@linux.alibaba.com> References: <20250910093347.75822-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Himanshu Chauhan ghes_map function uses arch_apei_get_mem_attribute to get the protection bits for a given physical address. These protection bits are then used to map the physical address. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/acpi.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..0c599452ef48 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -27,6 +27,26 @@ extern int acpi_disabled; extern int acpi_noirq; extern int acpi_pci_disabled; =20 +#ifdef CONFIG_ACPI_APEI +/* + * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling + * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode + * with a kernel command line parameter "acpi=3Dnocmcoff". But we don't + * have this IA-32 specific feature on ARM64, this definition is only + * for compatibility. + */ +#define acpi_disable_cmcff 1 +static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr) +{ + /* + * Until we have a way to look for EFI memory attributes. + */ + return PAGE_KERNEL; +} +#else /* CONFIG_ACPI_APEI */ +#define acpi_disable_cmcff 0 +#endif /* !CONFIG_ACPI_APEI */ + static inline void disable_acpi(void) { acpi_disabled =3D 1; --=20 2.43.7 From nobody Thu Oct 2 21:56:26 2025 Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F381E3128A4; Wed, 10 Sep 2025 09:34:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496859; cv=none; b=Zb8wCJTQ4sR0yDtEMGTQKVPC+rG50F8hLgDMveRft33TDPeo+Lz46onJE8x4bKUEtrDWQ9opGKxJbHzaMSwOJw2m7slDXSVkYL4VE3ZPBf/E33JN7MQ9fkCTKs/PTwSLVEDk2JjSldcQH1angnDz9mzlDrrsTP7nlf16TVgN3n4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496859; c=relaxed/simple; bh=G2oIlx5+3F0uTA2qs+8gy1BOtO3oFBeT4X0nl6deiXY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Xjh4fS48pwegJgLRvunFDNrHOIDB62vgHEy2B1/hDiPj1g88A29hBgK3kfVQG0ZUs74e9O9/NUJNt2sw4SkdpxYY+rcsAQhsmwfF8d6o3BPVowuYDGbV/rbKgz7Upn+sWzu4rLDsq0bE0toetiwWqzwZrLAHfKaPXVEggPiP5JM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=r9njdxEu; arc=none smtp.client-ip=115.124.30.97 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="r9njdxEu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757496845; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Pr8EoGstQtjK3lXgH2CmjXH5Mo22c8CU5zRjW49QuUo=; b=r9njdxEuxYheWutRTgpNbkUXDTARsCF0u2IV7NsJDJhXdwCo3VSidLssZw3GI7pMlpnivDWtQAUfjqLbc/iBAqqMqlBZ0qxJf9GKUPC/p8KHP30AXg3R+kM44TOCrRVOFZ9FdkBNjl8IvezwT6Yv0TD2p6EDFuMtXuedm2CPRGI= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0WnhhBqV_1757496843 cluster:ay36) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 17:34:05 +0800 From: Ruidong Tian To: xueshuai@linux.alibaba.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: james.morse@arm.com, tony.luck@intel.com, cleger@rivosinc.com, hchauhan@ventanamicro.com, tianruidong@linux.alibaba.com Subject: [RFC PATCH 3/5] acpi: Introduce SSE and HEE in HEST notification types Date: Wed, 10 Sep 2025 17:33:45 +0800 Message-Id: <20250910093347.75822-4-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20250910093347.75822-1-tianruidong@linux.alibaba.com> References: <20250910093347.75822-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce atwo new HEST notification type for RISC-V Hardware Error Exception and SSE. The GHES entry's notification structure contains the notification to be used for a given error source. Signed-off-by: Ruidong Tian --- include/acpi/actbl1.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 99fd1588ff38..0f04ef10f510 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1534,7 +1534,9 @@ enum acpi_hest_notify_types { ACPI_HEST_NOTIFY_SEI =3D 9, /* ACPI 6.1 */ ACPI_HEST_NOTIFY_GSIV =3D 10, /* ACPI 6.1 */ ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED =3D 11, /* ACPI 6.2 */ - ACPI_HEST_NOTIFY_RESERVED =3D 12 /* 12 and greater are reserved */ + ACPI_HEST_NOTIFY_SSE =3D 12, /* RISCV SSE */ + ACPI_HEST_NOTIFY_HEE =3D 13, /* RISCV Hardware Error Exception */ + ACPI_HEST_NOTIFY_RESERVED =3D 14 /* 14 and greater are reserved */ }; =20 /* Values for config_write_enable bitfield above */ --=20 2.43.7 From nobody Thu Oct 2 21:56:26 2025 Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED062313547; Wed, 10 Sep 2025 09:34:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496860; cv=none; b=LERKrxqJRC52MpuinMpDAGqeS/g1LyWdvsyYwL9xHRjv5gKu8UbeWfguX0f1sDSPjflFLwoMa+qHHpDwRMPirZX6DzQiopRDHY4/b8jrIDkPUERCf3ktSytaPXWG6sOoIw0gbBYPt3CsTg6dyJfYEJ4FtqZUUm/usH67PpmtFmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496860; c=relaxed/simple; bh=vb7ysZHJXr577SA49vAnSzIHlezKX5EJr+tN8E4GHQk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eSqt2aUuv5XUIcrq0kYEc6Gcgf/sz4n+6AzfaxBKhtXyzkFCRF6wUdUaMZXZkd2n/KRObxQdT+RAM4+ZzaEjvKgjovScl3u9+pGl0vQ0qlZhpRQ3LjgvWLZYAaHP4vyeTyISTU7QoZbNFAi9XMNDnk2CqPOGOX/nyxD7yR9rPvM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=ehgkz+qQ; arc=none smtp.client-ip=115.124.30.100 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="ehgkz+qQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757496848; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=5iaWrlk2P/qazoj+ucrjuJcazBZzpbTMnF2UzUvRWzk=; b=ehgkz+qQ5zGXoB2Nb0SoBssgqv9IidQV8HS+xmYyLDrI3LMzXxyzTnvHmaFKIBy7qfrJNrCsn7qRKYrA1z15cC29ePYkYZqRLayQJHizvvNzhefPQ7J4pj3SGAgj4w/iUY5BiqN/DSpPhwoLi/Qj4rZ9Zea6bOQ8G2PJ09u6mOo= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0WnhXsbO_1757496846 cluster:ay36) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 17:34:08 +0800 From: Ruidong Tian To: xueshuai@linux.alibaba.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: james.morse@arm.com, tony.luck@intel.com, cleger@rivosinc.com, hchauhan@ventanamicro.com, tianruidong@linux.alibaba.com Subject: [RFC PATCH 4/5] riscv: Introduce HEST HEE notification handlers for APEI Date: Wed, 10 Sep 2025 17:33:46 +0800 Message-Id: <20250910093347.75822-5-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20250910093347.75822-1-tianruidong@linux.alibaba.com> References: <20250910093347.75822-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add functions to register a ghes entry with HEE, allowing the OS to receive hardware error notifications from firmware through standardized ACPI interfaces. Signed-off-by: Ruidong Tian --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/fixmap.h | 6 ++++ drivers/acpi/apei/Kconfig | 12 +++++++ drivers/acpi/apei/ghes.c | 58 +++++++++++++++++++++++++++++++++ include/acpi/ghes.h | 6 ++++ 5 files changed, 83 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a4b233a0659e..b085e172b355 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -23,6 +23,7 @@ config RISCV select ARCH_ENABLE_MEMORY_HOTREMOVE if MEMORY_HOTPLUG select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE + select HAVE_ACPI_APEI if (ACPI && EFI) select ARCH_HAS_BINFMT_FLAT select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL if MMU diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixma= p.h index 0a55099bb734..07421edc9daa 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -38,6 +38,12 @@ enum fixed_addresses { FIX_TEXT_POKE0, FIX_EARLYCON_MEM_BASE, =20 +#ifdef CONFIG_ACPI_APEI_HEE + /* Used for GHES mapping from assorted contexts */ + FIX_APEI_GHES_IRQ, + FIX_APEI_GHES_HEE, +#endif /* CONFIG_ACPI_APEI_GHES */ + __end_of_permanent_fixed_addresses, /* * Temporary boot-time mappings, used by early_ioremap(), diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 070c07d68dfb..d54a295cfc8d 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -46,6 +46,18 @@ config ACPI_APEI_SEA depends on ARM64 && ACPI_APEI_GHES default y =20 +config ACPI_APEI_HEE + bool "APEI Hardware Error Exception support" + depends on RISCV && ACPI_APEI_GHES + default y + help + Enable support for RISC-V Hardware Error Exception (HEE) notification + in ACPI Platform Error Interface (APEI). This allows firmware + to report hardware errors through RISC-V exception mechanism. + + Say Y if you want to support firmware-first error handling + on RISC-V platforms with ACPI. + config ACPI_APEI_MEMORY_FAILURE bool "APEI memory error recovering support" depends on ACPI_APEI && MEMORY_FAILURE diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index a0d54993edb3..1011e28091dc 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -97,6 +97,11 @@ #define FIX_APEI_GHES_SDEI_CRITICAL __end_of_fixed_addresses #endif =20 +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM64) +#define FIX_APEI_GHES_NMI __end_of_fixed_addresses +#define FIX_APEI_GHES_SEA __end_of_fixed_addresses +#endif + static ATOMIC_NOTIFIER_HEAD(ghes_report_chain); =20 static inline bool is_hest_type_generic_v2(struct ghes *ghes) @@ -1415,6 +1420,45 @@ static inline void ghes_sea_add(struct ghes *ghes) {= } static inline void ghes_sea_remove(struct ghes *ghes) { } #endif /* CONFIG_ACPI_APEI_SEA */ =20 +#ifdef CONFIG_ACPI_APEI_HEE +static LIST_HEAD(ghes_hee); + +/* + * Return 0 only if one of the HEE error sources successfully reported an = error + * record sent from the firmware. + */ +int ghes_notify_hee(void) +{ + static DEFINE_RAW_SPINLOCK(ghes_notify_lock_hee); + int rv; + + raw_spin_lock(&ghes_notify_lock_hee); + rv =3D ghes_in_nmi_spool_from_list(&ghes_hee, FIX_APEI_GHES_HEE); + raw_spin_unlock(&ghes_notify_lock_hee); + + return rv; +} +EXPORT_SYMBOL_GPL(ghes_notify_hee); + +static void ghes_hee_add(struct ghes *ghes) +{ + mutex_lock(&ghes_list_mutex); + list_add_rcu(&ghes->list, &ghes_hee); + mutex_unlock(&ghes_list_mutex); +} + +static void ghes_hee_remove(struct ghes *ghes) +{ + mutex_lock(&ghes_list_mutex); + list_del_rcu(&ghes->list); + mutex_unlock(&ghes_list_mutex); + synchronize_rcu(); +} +#else /* CONFIG_ACPI_APEI_HEE */ +static inline void ghes_hee_add(struct ghes *ghes) { } +static inline void ghes_hee_remove(struct ghes *ghes) { } +#endif /* CONFIG_ACPI_APEI_HEE */ + #ifdef CONFIG_HAVE_ACPI_APEI_NMI /* * NMI may be triggered on any CPU, so ghes_in_nmi is used for @@ -1558,6 +1602,14 @@ static int ghes_probe(struct platform_device *ghes_d= ev) goto err; } break; + case ACPI_HEST_NOTIFY_HEE: + if (!IS_ENABLED(CONFIG_ACPI_APEI_HEE)) { + pr_warn(GHES_PFX "Generic hardware error source: %d notified via HEE is= not supported\n", + generic->header.source_id); + rc =3D -ENOTSUPP; + goto err; + } + break; case ACPI_HEST_NOTIFY_NMI: if (!IS_ENABLED(CONFIG_HAVE_ACPI_APEI_NMI)) { pr_warn(GHES_PFX "Generic hardware error source: %d notified via NMI in= terrupt is not supported!\n", @@ -1631,6 +1683,9 @@ static int ghes_probe(struct platform_device *ghes_de= v) case ACPI_HEST_NOTIFY_SEA: ghes_sea_add(ghes); break; + case ACPI_HEST_NOTIFY_HEE: + ghes_hee_add(ghes); + break; case ACPI_HEST_NOTIFY_NMI: ghes_nmi_add(ghes); break; @@ -1698,6 +1753,9 @@ static void ghes_remove(struct platform_device *ghes_= dev) case ACPI_HEST_NOTIFY_SEA: ghes_sea_remove(ghes); break; + case ACPI_HEST_NOTIFY_HEE: + ghes_hee_remove(ghes); + break; case ACPI_HEST_NOTIFY_NMI: ghes_nmi_remove(ghes); break; diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index ebd21b05fe6e..8046e1b30c21 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -127,6 +127,12 @@ int ghes_notify_sea(void); static inline int ghes_notify_sea(void) { return -ENOENT; } #endif =20 +#ifdef CONFIG_ACPI_APEI_HEE +int ghes_notify_hee(void); +#else +static inline int ghes_notify_hee(void) { return -ENOENT; } +#endif + struct notifier_block; extern void ghes_register_report_chain(struct notifier_block *nb); extern void ghes_unregister_report_chain(struct notifier_block *nb); --=20 2.43.7 From nobody Thu Oct 2 21:56:26 2025 Received: from out30-101.freemail.mail.aliyun.com (out30-101.freemail.mail.aliyun.com [115.124.30.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 924733112BE; Wed, 10 Sep 2025 09:34:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757496859; cv=none; b=ovJ4BORRhrBH7zR6D5VMnBuxY5JlM4M2v+cRvArNp5MmMCTrigkmbI7+Xih8Qg5c2F7EffNoi/cVf82iFC7c+h08Us69VqB3TPAQ23HgGmHMbaudVVyLnHvsTA778+uLLWYZ7jc/lGpk4SX02qwvvN84BphhkMkHjjfprubwpyA= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1757496853; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=CxOpiotR3/TBBHbw/zXSnCu06zXOVHPuSixUgLaNya4=; b=ty2WBiMULegD1S7qvJw/bXQZDV7HJ/q64rOCmdSA6jY6ahB3d51uYvMv2mIMvhHrd+FPnqHAqVdxBnMXjvj8NZawQS9QcC6B0P3Z+FVUtmkpj7pk4u9D1uz4Fm0fWWZRVb7DseDGEz11/l6i3XWTsK44q1Gbne7Z05o8AIbffpg= Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0Wnhbz2M_1757496849 cluster:ay36) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 17:34:12 +0800 From: Ruidong Tian To: xueshuai@linux.alibaba.com, palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: james.morse@arm.com, tony.luck@intel.com, cleger@rivosinc.com, hchauhan@ventanamicro.com, tianruidong@linux.alibaba.com Subject: [RFC PATCH 5/5] riscv: Add Hardware Error Exception trap handler Date: Wed, 10 Sep 2025 17:33:47 +0800 Message-Id: <20250910093347.75822-6-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20250910093347.75822-1-tianruidong@linux.alibaba.com> References: <20250910093347.75822-1-tianruidong@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement the Hardware Error Exception trap handler for RISC-V architecture synchronous hardware error handling. This enables the OS to receive hardware error notifications from firmware through the standardized ACPI HEST (Hardware Error Source Table) interface. The implementation includes: - A new exception vector entry for Hardware Error Exceptio - A trap handler (do_trap_hardware_error) that processes hardware errors in both kernel(panic now) and user modes(SIGBUS) - Integration with APEI GHES (Generic Hardware Error Source) to report hardware errors from firmware This change enables RISC-V systems with ACPI to handle synchronous hardware errors in a firmware-first manner. Signed-off-by: Ruidong Tian --- arch/riscv/include/asm/acpi.h | 2 ++ arch/riscv/kernel/acpi.c | 55 +++++++++++++++++++++++++++++++++++ arch/riscv/kernel/entry.S | 4 +++ arch/riscv/kernel/traps.c | 19 ++++++++++++ 4 files changed, 80 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0c599452ef48..ae861885b97d 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -91,6 +91,7 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, =20 void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_si= ze, u32 *cboz_size, u32 *cbop_size); +int apei_claim_hee(struct pt_regs *regs); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -108,6 +109,7 @@ static inline void acpi_get_cbo_block_size(struct acpi_= table_header *table, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size) { } =20 +static inline int apei_claim_hee(struct pt_regs *regs) { return -ENOENT; } #endif /* CONFIG_ACPI */ =20 #ifdef CONFIG_ACPI_NUMA diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 3f6d5a6789e8..928f9474bfee 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -20,6 +20,11 @@ #include #include #include +#include +#include +#include +#include +#include =20 int acpi_noirq =3D 1; /* skip ACPI IRQ initialization */ int acpi_disabled =3D 1; @@ -334,3 +339,53 @@ int raw_pci_write(unsigned int domain, unsigned int bu= s, } =20 #endif /* CONFIG_PCI */ + +/* + * Claim Hardware Error Exception as a firmware first notification. + * + * Used by RISC-V exception handler for hardware error processing. + * @regs may be NULL when called from process context. + */ +int apei_claim_hee(struct pt_regs *regs) +{ + int err =3D -ENOENT; + bool return_to_irqs_enabled; + unsigned long flags; + + if (!IS_ENABLED(CONFIG_ACPI_APEI_GHES)) + return err; + + /* Save current interrupt state */ + local_irq_save(flags); + return_to_irqs_enabled =3D !irqs_disabled(); + + if (regs) + return_to_irqs_enabled =3D (regs->status & SR_SIE) !=3D 0; + + /* + * HEE can interrupt other operations, handle as NMI-like context + * to ensure proper APEI processing + */ + nmi_enter(); + err =3D ghes_notify_hee(); + nmi_exit(); + + /* + * APEI NMI-like notifications are deferred to irq_work. Unless + * we interrupted irqs-masked code, we can do that now. + */ + if (!err) { + if (return_to_irqs_enabled) { + local_irq_restore(flags); + irq_work_run(); + } else { + pr_warn_ratelimited("APEI work queued but not completed"); + err =3D -EINPROGRESS; + } + } else { + local_irq_restore(flags); + } + + return err; +} +EXPORT_SYMBOL(apei_claim_hee); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 3a0ec6fd5956..1cbefe934d84 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -459,6 +459,10 @@ SYM_DATA_START_LOCAL(excp_vect_table) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ + RISCV_PTR do_trap_unknown + RISCV_PTR do_trap_unknown + RISCV_PTR do_trap_unknown + RISCV_PTR do_trap_hardware_error /* Hardware Error */ SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) =20 #ifndef CONFIG_MMU diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 80230de167de..48f1ea1e03e6 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -22,6 +22,7 @@ #include #include #include +#include =20 #include #include @@ -442,3 +443,21 @@ asmlinkage void handle_bad_stack(struct pt_regs *regs) wait_for_interrupt(); } #endif + +asmlinkage __visible __trap_section void do_trap_hardware_error(struct pt_= regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + if (apei_claim_hee(regs)) + do_trap_error(regs, SIGBUS, BUS_OBJERR, regs->badaddr, "Hardware Error"= ); + + irqentry_exit_to_user_mode(regs); + } else { + irqentry_state_t state =3D irqentry_nmi_enter(regs); + + die(regs, "Hardware Error"); + + irqentry_nmi_exit(regs, state); + } +} --=20 2.43.7