From nobody Thu Oct 2 22:43:17 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2065.outbound.protection.outlook.com [40.107.244.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90F60296BA2; Wed, 10 Sep 2025 04:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757477898; cv=fail; b=sfBWP6yYkHV7eIORASR9IgeUoH71eX46tWNia1BaeM0jKqfz3rVzmeLGVuhjumYw3dZKHBkt7EudoMpzrUT1qjKlL896oH8pIV5FERfCzEQPE21BCUB+O5zvmKtJicpFrjhZ/Kb76D73gZ8c2DuOfeMWzD7Y1NCVhiJyrP8BRRQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757477898; c=relaxed/simple; bh=xXnPiahlzlOQRBAVZJK/tC5dArUyKixZx+oT05pPHic=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GBbSFBpx614Op5ZzLB9d2No8IRUJggAKhci1+zKdExqpE2Hh2asNakwSKMIXmltg68I1TU/CGp8szoVMyr3W2oTCgNjeOuGyGpGK2G0zSD80+WYk1+2x+2W7IrSZBYftQL0VM2wNAdBLON6IZj2/mOSrWm2acAo0zHjdbTobIkQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=iaAIFVRx; arc=fail smtp.client-ip=40.107.244.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="iaAIFVRx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=u+YAlsEAgWdrzYbevkdqw8sLTQXSEwfZ8lhwIcSnI3HIkj+sGNHgXtSzjFkY8/KZMWyc5/GfCdHfmrP7K39Peq4VYS5A5LaTOqnW9hvE5pCx4D04b8DiNPDSrK2Pigi8nL+3shSBMpN7xTh0a6TTg+8BdvtvV85QXN+YAszRQV968GJ/1NogCrTVk5SQTH20haFOfcj1kShySaLznaTqFWDquiFIXHpI2bYqa+U0z5EH42MJSREX04bfgv1iTzVQyAWOffCYeY8mEiMXFtj9r9cclFVTkCuHj8ESzk0QHHi7e4GLyVdyYWSq144K1mvacDOB+0qR3X77BnDZmbb2Fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/PJbBvDV+noSKFlIser/JH9z0P+Q4gTCv13gY7hx1Mg=; b=jdIS+c1n6BHg+BLsT4e6Il6tcCPLPq4q6548nTPTXlXnxKw1TwsJ5LtAckpYOPFVkg5XUejAkjjw0qQcxE4YbPS6wTYkaWgXQMh3Bl3+vnifDwxjTOc1PnUSqjnbnwmIVkVK2McapXi24QnaA7WImHW8/yENBn+J+eqOXQI5CNgSRiUeh/URfoEtyLfXzRSx+JKIIBio7l0BqIC/GMFkG9IVQ6vGGkKpcWmtNWmDbJSL1Wt7Iy2EI00kr25mNbmAouhm1gwVfA/7+6MLI2prn74qFtszKLI4OozayItKYwsu/Ozoz4HiAzYEKe6NafqEksYcagPoz0CIFiPuNFdq2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/PJbBvDV+noSKFlIser/JH9z0P+Q4gTCv13gY7hx1Mg=; b=iaAIFVRxWtwfZXRs9enRM1l9vZ54G9YjAB0hKorwHV4cgZ1IVF6SPdgt8t1duUyQJinmQk8EtTgrGbGTrRhzuqxNbUC7mzWj2MCfXY8U4NOzqkIlYhoJ/pqhHQt+JsJGJ3FW6w9R0hQzLaGnfwLJljgWnmtuNIPojbT8XkbhZS4dnIDn/GGbUll7PGvHiqxhtoyXYdSHaMMcL5aMTuFR14xnQtmv6G2OY7/wHZfFsGWhWVbYpJjfs3ySbITZLY2G8YubhNw4N1lCeOKXwpC8GsbnxmQzDqyvldOwDY1pQ+0kO78eCSr9j1rz2U/0PIF69U0t285Wu6YQ4NoMUuCYpg== Received: from PH7P220CA0002.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:326::34) by PH0PR12MB5605.namprd12.prod.outlook.com (2603:10b6:510:129::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9094.22; Wed, 10 Sep 2025 04:18:09 +0000 Received: from SN1PEPF00036F3D.namprd05.prod.outlook.com (2603:10b6:510:326:cafe::e2) by PH7P220CA0002.outlook.office365.com (2603:10b6:510:326::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9115.15 via Frontend Transport; Wed, 10 Sep 2025 04:18:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9115.13 via Frontend Transport; Wed, 10 Sep 2025 04:18:08 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 9 Sep 2025 21:17:40 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 9 Sep 2025 21:17:39 -0700 Received: from dondevbox.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 9 Sep 2025 21:17:39 -0700 From: Donald Shannon To: , , , CC: , , , , , , , , Krzysztof Kozlowski Subject: [PATCH v9 1/2] dt-bindings: arm: aspeed: Add NVIDIA GB200-UT3.0b board Date: Tue, 9 Sep 2025 21:17:35 -0700 Message-ID: <20250910041736.245451-2-donalds@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910041736.245451-1-donalds@nvidia.com> References: <20250910041736.245451-1-donalds@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: aef6040b-446b-4bff-9533-08ddf0210c80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?r1T4HyoryYM/AZiGq6P5kAL9fDt2BXvgI36+uPMxpcRxOLRQ+MQ/H+TjjDuk?= =?us-ascii?Q?LNTcbPHu6WtQ5eWSGoS1mOpqqPNqig26xrn4AZsXxIJtwkgqU5aGYM8eVHOm?= =?us-ascii?Q?DW1Rv3XQE0x03ry4a2UWmPEHFd77Xst+sC1KopCQCP7GhzzGI04NQ4qmgAAL?= =?us-ascii?Q?ApZN3poXJDyRBW2s4WLPzUMoZeGQH/uUHgXGAr4wnLdT+fZHU4Em506Y2doP?= =?us-ascii?Q?zqGZ4L0xWb5xB0bsDEnRIwhCNfoJ0b4zj2l6H2TSgpIkmN+9j16lmQVEj7db?= =?us-ascii?Q?wcNeWBd+odPL20NaCPWgU+NnIWn+nYdR4Lkr+s/xPtB1W7DWBJ4Zr8ShvUeH?= =?us-ascii?Q?FP/P6JlwBrS08N4xiPkoWHSXmD0GXVquKN5j0xAh28NjPeDe2SEKO42xWMNk?= =?us-ascii?Q?uOxTqS9SDkmV5vQ96kA58PKHeHw0VgiFJmq6qL9wUck/6ctbkDXzptPf6Gqh?= =?us-ascii?Q?fHOrBzH2zRJSwhnZPaUXXYQqsHggEdYOku2ZFnzCk8GwD55J6nFKahocTqlI?= =?us-ascii?Q?4TrcpnkGPrxPzt5zyixoKoVMjH6TClq7uPTTS7oP6T6uxB4v5+sjFuN1Kw9S?= =?us-ascii?Q?HoAvVaJjrCnoVA04+LL69zi1tJ3u74EOkcjkWRllctxjefzJonfdXjQ5KPEx?= =?us-ascii?Q?rE4Kab+zA7yVkodh/eKNf/xXGLzktaUC7fuIolUo1wHYkolwvm8qUrOTIHaW?= =?us-ascii?Q?U14O74Ppr/+e54epMfrykugNnKHwnh2NYCPeYSwZNECXc76LPOt6aYqvlDbZ?= =?us-ascii?Q?NkhrtEBIN7H0e8A+QVEOuCF5SegGYQxyfZ7NU+AJAyRjIU+w8bUgN8y+kb1i?= =?us-ascii?Q?wBBjQ2ChLS8u6YoCBH6EOr2hd58qc3+i9VvOMlVwRFeziKQ/AbpSgejKFQvC?= =?us-ascii?Q?VoydLo5yOHI+8n7Ogl7BxB9bAeS/9u9t+h3dDJmRpJoGsxsdfnERO8tXur7v?= =?us-ascii?Q?S/32RzgndYZa+RAEGWz/HpNDxZd+N1pl99WychAvcMprScpjibEUVqYyH4uY?= =?us-ascii?Q?DvuTQXzB74dWcRAdxRO1njyKTsWcxfd6/x+hcD2VNkGt0IDgOgoHZQzDVPds?= =?us-ascii?Q?4qYuEa6lJ7FmuPQJDPqii0cmoxSQVv+aSGqbXLi9tnN6dbnxhCpGO53uJdPa?= =?us-ascii?Q?SrGrZVwpA3iipIHg/UzWZfS0bdElzxqBV5dlCbqSdYlpKcLJU2/lDFH1M7ff?= =?us-ascii?Q?8gbyjYsF0TNyL3IKLZp6ThUpR0F3CoYgN2upDktKFkJnMZe68Evu+nEjPHiI?= =?us-ascii?Q?IoyDYybiriAaOxw7RHr7X35VY5RqebxNe5JhDNtWWwO3Ix1HjZmY7zbXSfMX?= =?us-ascii?Q?pYH2j3NHhwEF/ipVsvk005EK/UPuaYVAOvOl8J5lPj/0zUlyuZhgwaKSbbbZ?= =?us-ascii?Q?ecXZG/6+nhC7pKpfOZtqEMlqdu4QxJ/dgKSl1Q4pshDA9kvZThhn2FCa/kLp?= =?us-ascii?Q?9NZx2RRnhFQRqh+L+QlVLH4BJik+U0h+bxDogEUPSdlNoejD+/Bg7rL92oPI?= =?us-ascii?Q?+W1/DHsewilNDnQeCzKsLup7GXiMu2H1SXSi?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 04:18:08.7997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aef6040b-446b-4bff-9533-08ddf0210c80 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 Content-Type: text/plain; charset="utf-8" This is an Aspeed AST2600 based unit testing platform for GB200. UT3.0b is different than nvidia-gb200nvl-bmc due to networking topology differences, additional gpio expanders, and voltage regulator gating some devices. Reference to Ast2600 SOC [1]. Reference to Blackwell GB200NVL Platform [2]. Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Donald Shannon Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Doc= umentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..624581db2330 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -99,6 +99,7 @@ properties: - inventec,starscream-bmc - inventec,transformer-bmc - jabil,rbp-bmc + - nvidia,gb200-ut30b - nvidia,gb200nvl-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc --=20 2.43.0 From nobody Thu Oct 2 22:43:17 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2077.outbound.protection.outlook.com [40.107.237.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 813AF28CF6D; Wed, 10 Sep 2025 04:18:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757477905; cv=fail; b=sxuCjgjla3KrM5utskedw7emJQ2sLxbXAot5W7qkOvTPLI4gQrsPHvZ0BC7TUXDTFLccGdjYZo/7KNn1hXnGMSkbLDBXwC9i98ClVJRIr1n4vjBFl2JA1WmdzK6WXUwtZcaZLmwGcu0mJR8EkVjGEMyU2wsH16BUIIJ4/IphTAo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757477905; c=relaxed/simple; bh=BeHZiZ+kgyJLPEcPpMAHF9513BCv8w6v7hR7EZ6w72k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MbvfbOjd1sQX1YDCLQnhADyBrW5rEzuiKuAe8jqgROM0wNtcLS3wgWrYz/5VWqRgbJt4p7sWKUyWmg39VB3Vf1R94c6kYos5lkHPw3gX2jDBmgLnPJrI3mtluGn9zFUjVabo9LjsJp04519n8JBF5No27k2YlcKmlCIWPRNnEcc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=k9ASOcpP; arc=fail smtp.client-ip=40.107.237.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="k9ASOcpP" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=yJzMgCtoib5zcmjDa8f+sDcWITOsD7B58TgRLJVzNvb3y5+xsIM7LXsvMCVIHNMqigDaOCdWRGD0oEtlzdSPy2GXjZQ38Cy097Gp81uSwf/0pHOz8Rh44+OGwFoTGPdXTe0IAGyn4/0VJDrW9cw5z0CpmDNuB64malONR2s9zDPqak4H6cIhtMrT4CHhFtKyr4PFgof8Q03RGMvoaSNtMf/qU5PoNo5wCmSB7SUcbhVy9GT1WvYrUMizorLFdgWLEligQfVDjdNC2bhP0HB40kZSuKbtvLar5GiXK1neH8TvvkShbbnxrL4/cdMbSZFPsz1nnzYCytg0nzcaSmJqTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YPUkDo9p7X7Etdv3h6V2veRrpNteKkiDX/acVlEBdks=; b=No0uV3bGoHEXIMVaQyVRCrc6wdJH89buqig2Fcqz7HJwqUcmqU5HKafhNRXdvNh8xxe2VcBfHYKIDSMqnhTSy7CAy0+VZ4fT/FP/CZ80dX5G9qoGYcWdEwx0mCI/4SsfmQzBe9S6J9OxHwxMNsPIYnvLOrv0F2mdKUVoDig8Bio6ipkishYn1eJ0myvGgVmgS2kUsCX9G3PiQaFJBV4mOG2BzT8bh4mvt5VQTiDfoFNayfDjg4ZeITnucRWpf4btWszWjKC1SfBAXUruD5qIrosBjjBTNK8cjGC/IqP9C5NRXKwgVDKalb181cQ4eCPRS7fJszDHgbbbhEmrR9udnA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YPUkDo9p7X7Etdv3h6V2veRrpNteKkiDX/acVlEBdks=; b=k9ASOcpP/g5JGfL9T0HZLHNTdJuvU0VrRlkvOGCZk7ZkEMNl3NQgBVc8kd1clgmGaDT3rhmK18lxvQ761p5vlPZNOSzZTAUqIuLp22yKNNvdxLn1zNHw3EYg/jIVm/8a5zZqF3JwyA8V7MJ4SjU2YKUuG7Sjm8fUTtYStCpqSzT++Q3tS1v/x4CTqXpMHxDF/YC5JQCQuARnHDfW7n7YFqvU77/an1cGOCwSVyZ4NvjQK5YSVEZBuffWBYaK/CCDQ5KiryJJGRUxaF9r0QV8cP7laenhob3LMykIm2Bthlru9zYWdQYr0W4l7H/NiGtg1lmHaqcOlZMh2I7v/mSwVQ== Received: from PH7P220CA0002.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:326::34) by SA3PR12MB9228.namprd12.prod.outlook.com (2603:10b6:806:39c::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9094.22; Wed, 10 Sep 2025 04:18:10 +0000 Received: from SN1PEPF00036F3D.namprd05.prod.outlook.com (2603:10b6:510:326:cafe::67) by PH7P220CA0002.outlook.office365.com (2603:10b6:510:326::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9115.15 via Frontend Transport; Wed, 10 Sep 2025 04:18:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9115.13 via Frontend Transport; Wed, 10 Sep 2025 04:18:09 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 9 Sep 2025 21:17:41 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 9 Sep 2025 21:17:40 -0700 Received: from dondevbox.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.14 via Frontend Transport; Tue, 9 Sep 2025 21:17:40 -0700 From: Donald Shannon To: , , , CC: , , , , , , , Subject: [PATCH v9 2/2] ARM: dts: aspeed: Add NVIDIA GB200 UT3.0b board Date: Tue, 9 Sep 2025 21:17:36 -0700 Message-ID: <20250910041736.245451-3-donalds@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250910041736.245451-1-donalds@nvidia.com> References: <20250910041736.245451-1-donalds@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|SA3PR12MB9228:EE_ X-MS-Office365-Filtering-Correlation-Id: 558fd5b3-5b27-47dd-48d0-08ddf0210d12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|7416014|82310400026|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pPYLxI/NIZ0kYNcpQ01i9zsYnFwUvmjI6DE5fwZ8Bo0SDu3lWKw0Jsjz30xl?= =?us-ascii?Q?WlIl8RkHr3hNtreS97NjVtpDDdTq6SO+oaSSwfDjYK/5FvpU/bKl+52Tat3V?= =?us-ascii?Q?p/3DKVwsK6n8Fljqpu2xQBJ8eiYuiWh42SogqI8pAHKjKwGZ7BW0X7M2WHog?= =?us-ascii?Q?bTHVGbEZpKVmLF4fIlGsgdirz36R3p7VVwArUN3/NJpir7MgN3OymqrBvgPU?= =?us-ascii?Q?JU+WnYoyTGAm4yfBN71hKfqx9Nz4JvE5rstwqbkK8fGOOUhEa/7a18+JisL+?= =?us-ascii?Q?mI9HKzKBkVvHmYxqIfaSlZfkzMYMVelgmw8NbZLt2x4dzvagp3HGD6np1HSF?= =?us-ascii?Q?u/szgyrFNXd6JYkOJ08Hg3QGWBkMUjwSHv5zegjPlvQd0j0j3HlmNuHpnHns?= =?us-ascii?Q?V8mK0gS/MVOwDq3S7lGPq7QYC1O395EPRysa3JZvrWyiPxhSJTriGrZIZmd4?= =?us-ascii?Q?VNp3C5+YFxa4Z6hlXUUUq1hy9U/k8daW7WIRN3Olko/JdoRgKM31Cirtpbak?= =?us-ascii?Q?wuM8bS7inwOFarMf0n0Tu7Nb6hbZi0sq7SDNb1dDV9aF+DVIY5hQoDHHGDz+?= =?us-ascii?Q?gqDxmD2aVss6S5VtR/oVoGH02yQ/YVd/vNzzAISVPnznCv+VhdzzXH5PSS6y?= =?us-ascii?Q?XbkU7LuOLiJJHNvIfOki7AGPLYNbkWCg4nHc8kxNp85IKl+6Q5y9FkVEKdtL?= =?us-ascii?Q?DPazFJcu5pl65mfl6laq0A3jfAb27ZTUQWrwNZtmMcskogZFB0iBymPatQEZ?= =?us-ascii?Q?YWm8GfvBRkrfwJZ9h2exvpuo+XBeVVgFbzTATAAA375G2rg2xTngt+MbZb3e?= =?us-ascii?Q?SEOTyZtb7znjp8fylE1wtvwE59Tx7DyToMh6JZ+3SGUY8wvbT92S5v+8uRBa?= =?us-ascii?Q?diZkBgihFsM1NGjRjFiN/pXuHUtLEtKGodqSXrtLNPPaWYSVKJwWim3SgdaV?= =?us-ascii?Q?p732+gSO5EaVGi1noRJiWJ4+peojKcQ0PSW/r6cfqU34n8RMwV3i+Fe8v9iP?= =?us-ascii?Q?2LTdTsSum8nuuA1QLI1riWstjP6vmmrV9SKyYSYrOF+ch8dXR1Xfp3troSW8?= =?us-ascii?Q?Wibvif9vW83LQK8GeYjXXF/4RgFTtRtqXWZuWLUXyUp6ti20+P7PuqLrVshw?= =?us-ascii?Q?rRVKc5RiYZXvCqTQ/5pJzjXxxz/i8V45vvaLhKFPrx4RdGjK1UaXbdq6th6A?= =?us-ascii?Q?vVR+O2BbCbL8oZ/BzwoOObSUFD0Tiv4HU2EZ5jFB6t2KDE2olQfDeSrqN6fv?= =?us-ascii?Q?E6gcZWxf6Ds+SmA3MN1ArgHXO6BbE5UdMLcpy+jQlRLAJdnlqLJIFDtVtLgs?= =?us-ascii?Q?lB38ZRqbQXReLhgXQpcuOS0V2jxJ1AEKO6Q4dvKbop/Mxtt+R9A6tyWgc580?= =?us-ascii?Q?2rBwLgpv4nXnyefTXRgNmNt9v/pd4gYzOShfJcULuirGxuTUmEqqIHPnVKXJ?= =?us-ascii?Q?wMPr7SD+m0GN0yPwySEcVb7TUn1faFIYawj/9AuwWibZV9eh0VpCj3vCH7Pe?= =?us-ascii?Q?DHpSh+oF4F6EkSQJP4FzCqd9sI1aeElyCi8EwDOm3TP6NkbZxJIFxQeJJQ?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2025 04:18:09.7444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 558fd5b3-5b27-47dd-48d0-08ddf0210d12 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9228 Content-Type: text/plain; charset="utf-8" This is an Aspeed AST2600 based unit testing platform for GB200. UT3.0b is different than nvidia-gb200nvl-bmc due to networking topology differences, additional gpio expanders, and voltage regulator gating some devices. Reference to Ast2600 SOC [1]. Reference to Blackwell GB200NVL Platform [2]. Link: https://www.aspeedtech.com/server_ast2600/ [1] Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2] Signed-off-by: Donald Shannon --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts | 1032 +++++++++++++++++ 2 files changed, 1033 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.= dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/M= akefile index aba7451ab749..37edc4625a9f 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-lenovo-hr630.dtb \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ + aspeed-bmc-nvidia-gb200-ut30b.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts b/a= rch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts new file mode 100644 index 000000000000..3707e8f7bf79 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts @@ -0,0 +1,1032 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include + +/ { + model =3D "AST2600 GB200 UT3.0b BMC"; + compatible =3D "nvidia,gb200-ut30b", "aspeed,ast2600"; + + aliases { + serial2 =3D &uart3; + serial4 =3D &uart5; + i2c16 =3D &imux16; + i2c17 =3D &imux17; + i2c18 =3D &imux18; + i2c19 =3D &imux19; + i2c20 =3D &imux20; + i2c21 =3D &imux21; + i2c22 =3D &imux22; + i2c23 =3D &imux23; + i2c24 =3D &imux24; + i2c25 =3D &imux25; + i2c26 =3D &imux26; + i2c27 =3D &imux27; + i2c28 =3D &imux28; + i2c29 =3D &imux29; + i2c30 =3D &imux30; + i2c31 =3D &imux31; + i2c32 =3D &imux32; + i2c33 =3D &imux33; + i2c34 =3D &imux34; + i2c35 =3D &imux35; + i2c36 =3D &imux36; + i2c37 =3D &imux37; + i2c38 =3D &imux38; + i2c39 =3D &imux39; + i2c40 =3D &e1si2c0; + i2c41 =3D &e1si2c1; + i2c42 =3D &e1si2c2; + i2c43 =3D &e1si2c3; + i2c48 =3D &i2c17mux0; + i2c49 =3D &i2c17mux1; + i2c50 =3D &i2c17mux2; + i2c51 =3D &i2c17mux3; + i2c52 =3D &i2c25mux0; + i2c53 =3D &i2c25mux1; + i2c54 =3D &i2c25mux2; + i2c55 =3D &i2c25mux3; + i2c56 =3D &i2c29mux0; + i2c57 =3D &i2c29mux1; + i2c58 =3D &i2c29mux2; + i2c59 =3D &i2c29mux3; + }; + + buttons { + compatible =3D "gpio-keys"; + button-power { + label =3D "power_btn"; + linux,code =3D <116>; + gpios =3D <&sgpiom0 156 GPIO_ACTIVE_LOW>; + }; + button-uid { + label =3D "uid_btn"; + linux,code =3D <478>; + gpios =3D <&sgpiom0 154 GPIO_ACTIVE_LOW>; + }; + }; + + chosen { + stdout-path =3D &uart5; + }; + + leds { + compatible =3D "gpio-leds"; + led-0 { + label =3D "uid_led"; + gpios =3D <&sgpiom0 27 GPIO_ACTIVE_LOW>; + }; + led-1 { + label =3D "fault_led"; + gpios =3D <&sgpiom0 29 GPIO_ACTIVE_LOW>; + }; + led-2 { + label =3D "power_led"; + gpios =3D <&sgpiom0 31 GPIO_ACTIVE_LOW>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x80000000 0x80000000>; + }; + + reg_3v3_stby: regulator-3v3-standby { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3-standby"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + gpio =3D <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + gfx_memory: framebuffer { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x01000000>; + alignment =3D <0x01000000>; + }; + + ramoops@a0000000 { + compatible =3D "ramoops"; + reg =3D <0xa0000000 0x100000>; /* 1MB */ + record-size =3D <0x10000>; /* 64KB */ + max-reason =3D <2>; /* KMSG_DUMP_OOPS */ + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg =3D <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x02000000>; /* 32M */ + alignment =3D <0x01000000>; + }; + }; +}; + +// USB Port B Controller +&ehci1 { + status =3D "okay"; +}; + +// Need custom layout for Root of Trust +&fmc { + status =3D "okay"; + flash@0 { + compatible =3D "jedec,spi-nor"; + label =3D "bmc"; + spi-max-frequency =3D <50000000>; + status =3D "okay"; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u-boot@0 { + // 896KB + reg =3D <0x0 0xe0000>; + label =3D "u-boot"; + }; + + kernel@100000 { + // 9MB + reg =3D <0x100000 0x900000>; + label =3D "kernel"; + }; + + rofs@a00000 { + // 55292KB (extends to end of 64MB SPI - 4KB) + reg =3D <0xa00000 0x35FF000>; + label =3D "rofs"; + }; + }; + }; +}; + +&gpio0 { + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "", "", + /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", + /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_S= EL-O", + "", "", "", "SGPIO_BMC_EN-O", + /*F0-F7*/ "", "", "", "", "", "", "", "", + /*G0-G7*/ "", "", "", "", "", "", "", "", + /*H0-H7*/ "", "", "", "", "", "", "", "", + /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_D= DR4_TEN-O", + /*J0-J7*/ "", "", "", "", "", "", "", "", + /*K0-K7*/ "", "", "", "", "", "", "", "", + /*L0-L7*/ "", "", "", "", "", "", "", "", + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWE= R_EN-O", + "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", + /*N0-N7*/ "", "", "", "", "", "", "", "", + /*O0-O7*/ "", "", "", "", "", "", "", "", + /*P0-P7*/ "", "", "", "", "", "", "", "", + /*Q0-Q7*/ "", "", "", "", "", "", "", "", + /*R0-R7*/ "", "", "", "", "", "", "", "", + /*S0-S7*/ "", "", "", "", "", "", "", "", + /*T0-T7*/ "", "", "", "", "", "", "", "", + /*U0-U7*/ "", "", "", "", "", "", "", "", + /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "= ","", "", + /*W0-W7*/ "", "", "", "", "", "", "", "", + /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", + /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", + /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; +}; + +&gpio1 { + /* 36 1.8V GPIOs */ + gpio-line-names =3D + /*A0-A7*/ "", "", "", "", "", "", "", "", + /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", + /*C0-C7*/ "", "", "", "", "", "", "", "", + /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_= INT_L-I", + /*E0-E7*/ "", "", "", "", "", "", "", ""; +}; + +// I2C1, SSIF IPMI interface +&i2c0 { + clock-frequency =3D <400000>; + status =3D "okay"; + ssif-bmc@10 { + compatible =3D "ssif-bmc"; + reg =3D <0x10>; + }; +}; + +// I2C3 +// BMC_I2C0_FPGA - Primary FPGA +&i2c2 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; +}; + +// I2C5 +// RTC Driver +// IO Expander +&i2c4 { + clock-frequency =3D <400000>; + status =3D "okay"; + // Module 0, Expander @0x21 + exp4: gpio@21 { + compatible =3D "nxp,pca9555"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "RTC_MUX_SEL-O", + "PCI_MUX_SEL-O", + "TPM_MUX_SEL-O", + "FAN_MUX-SEL-O", + "SGMII_MUX_SEL-O", + "DP_MUX_SEL-O", + "UPHY3_USB_SEL-O", + "NCSI_MUX_SEL-O", + "BMC_PHY_RST-O", + "RTC_CLR_L-O", + "BMC_12V_CTRL-O", + "PS_RUN_IO0_PG-I", + "", + "", + "", + ""; + }; +}; + +// I2C6 +// Module 0/1 I2C MUX x3 +&i2c5 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; + + i2c-mux@71 { + compatible =3D "nxp,pca9546"; + reg =3D <0x71>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux16: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + imux17: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c17mux0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c17mux1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + i2c17mux2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + i2c17mux3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + }; + + imux18: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + imux19: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; + + i2c-mux@72 { + compatible =3D "nxp,pca9546"; + reg =3D <0x72>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux20: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux21: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "RST_CX_0_L-O", + "RST_CX_1_L-O", + "CX0_SSD0_PRSNT_L-I", + "CX1_SSD1_PRSNT_L-I", + "CX_BOOT_CMPLT_CX0-I", + "CX_BOOT_CMPLT_CX1-I", + "CX_TWARN_CX0_L-I", + "CX_TWARN_CX1_L-I", + "CX_OVT_SHDN_CX0-I", + "CX_OVT_SHDN_CX1-I", + "FNP_L_CX0-O", + "FNP_L_CX1-O", + "", + "MCU_GPIO-I", + "MCU_RST_N-O", + "MCU_RECOVERY_N-O"; + }; + }; + + imux22: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux23: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@73 { + compatible =3D "nxp,pca9546"; + reg =3D <0x73>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux24: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux25: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c25mux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c25mux3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + + imux26: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux27: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@75 { + compatible =3D "nxp,pca9546"; + reg =3D <0x75>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux28: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux29: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + i2c-mux@74 { + compatible =3D "nxp,pca9546"; + reg =3D <0x74>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + i2c29mux0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c29mux3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + }; + + imux30: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux31: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@76 { + compatible =3D "nxp,pca9546"; + reg =3D <0x76>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux32: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux33: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux34: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux35: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + i2c-mux@77 { + compatible =3D "nxp,pca9546"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + imux36: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux37: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux38: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + imux39: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +// I2C7 +// Module 0/1 Leak Sensors +// Module 0/1 Fan Controllers +&i2c6 { + clock-frequency =3D <400000>; + status =3D "okay"; + + pmic@12 { + compatible =3D "ti,lm5066i"; + reg =3D <0x12>; + shunt-resistor-micro-ohms =3D <190>; + }; + + pmic@14 { + compatible =3D "ti,lm5066i"; + reg =3D <0x14>; + shunt-resistor-micro-ohms =3D <190>; + }; + + pwm@20 { + compatible =3D "maxim,max31790"; + reg =3D <0x20>; + }; + + pwm@23 { + compatible =3D "maxim,max31790"; + reg =3D <0x23>; + }; + + pwm@2c { + compatible =3D "maxim,max31790"; + reg =3D <0x2c>; + }; + + pwm@2f { + compatible =3D "maxim,max31790"; + reg =3D <0x2f>; + }; +}; + +// I2C9 +// M.2 +&i2c8 { + clock-frequency =3D <400000>; + multi-master; + status =3D "okay"; +}; + +// I2C10 +// Module 0/1 IO Expanders +&i2c9 { + clock-frequency =3D <400000>; + status =3D "okay"; + + // Module 0, Expander @0x20 + exp0: gpio@20 { + compatible =3D "nxp,pca9555"; + reg =3D <0x20>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "FPGA_THERM_OVERT_L-I", + "FPGA_READY_BMC-I", + "HMC_BMC_DETECT-O", + "HMC_PGOOD-O", + "", + "BMC_STBY_CYCLE-O", + "FPGA_EROT_FATAL_ERROR_L-I", + "WP_HW_EXT_CTRL_L-O", + "EROT_FPGA_RST_L-O", + "FPGA_EROT_RECOVERY_L-O", + "BMC_EROT_FPGA_SPI_MUX_SEL-O", + "USB_HUB_RESET_L-O", + "NCSI_CS1_SEL-O", + "SGPIO_EN_L-O", + "B2B_IOEXP_INT_L-I", + "I2C_BUS_MUX_RESET_L-O"; + }; + + // UT3.0b Expander @0x22 + exp2: gpio@22 { + compatible =3D "nxp,pca9555"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "BMC1_FANCTRL_FAIL_L-I", + "IOEXP_BMC_RST_12V-O", + "NODE_RST_STBY_H-O", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + }; + + // UT3.0b Expander @0x23 + exp3: gpio@23 { + compatible =3D "nxp,pca9555"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gpio1>; + interrupts =3D ; + vcc-supply =3D <®_3v3_stby>; + gpio-line-names =3D + "PEXSW_FL_SPI_MUX_SEL-O", + "PEX_SW_FATAL_ERROR_3V3_L-I", + "IOEXP_PDB_NODE_EN_L-O", + "NODE_PWOK_ISO-I", + "BMC_FAN_PWR_EN-O", + "BMC_ETHERNET_INT-I", + "BMC_ENET_RST-O", + "IOEXP_BMC_RST_SENSE-O", + "BMC_ID-I", + "TPM_MUX_3V3_SEL_N-O", + "IOEXP_TPM_RST_N-O", + "TPM_DOWN_SPI_INT_L-I", + "PS_BRD_PGOOD-I", + "FP_BUTTON_POWER_N-I", + "FP_BUTTON_RESET_N-I", + "FP_LED_POWER_GPIOEXP_N-O"; + }; +}; + +// I2C11 +// BMC FRU EEPROM +// BMC Temp Sensor +&i2c10 { + clock-frequency =3D <400000>; + status =3D "okay"; + + // BMC FRU EEPROM - 256 bytes + eeprom@50 { + compatible =3D "atmel,24c02"; + reg =3D <0x50>; + pagesize =3D <8>; + }; + + temp-sensor@48 { + compatible =3D "ti,tmp1075"; + reg =3D <0x48>; + }; +}; + +// I2C12 +&i2c11 { + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +// I2C15 +// Module 1 UPHY3 SMBus +&i2c14 { + clock-frequency =3D <100000>; + multi-master; + status =3D "okay"; + + //E1.S drive slot 0-3 + i2c-mux@77 { + compatible =3D "nxp,pca9546"; + reg =3D <0x77>; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-mux-idle-disconnect; + vdd-supply =3D <®_3v3_stby>; + + e1si2c0: i2c@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c1: i2c@1 { + reg =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c2: i2c@2 { + reg =3D <2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + e1si2c3: i2c@3 { + reg =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; +}; + +&mac0 { + pinctrl-names =3D "default"; + phy-handle =3D <ðphy0>; + pinctrl-0 =3D <&pinctrl_rgmii1_default>; + status =3D "okay"; +}; + +&mdio0 { + status =3D "okay"; + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + }; +}; + +&rng { + status =3D "okay"; +}; + +&sgpiom0 { + ngpios =3D <128>; + status =3D "okay"; + gpio-line-names =3D + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O", + "RUN_POWER_PG-I","PWR_BRAKE_L-O", + "SYS_RST_OUT_L-I","RUN_POWER_EN-O", + "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O", + "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O", + "SHDN_OK_L-I","UID_LED_N-O", + "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O", + "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O", + "FPGA_RSVD_FFU3-I","", + "FPGA_RSVD_FFU2-I","", + "FPGA_RSVD_FFU1-I","", + "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O", + "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O", + "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O", + "THERM_BB_WARN_L-I","UART_MUX_SEL-O", + "THERM_BB_OVERT_L-I","", + "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O", + "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O", + "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O", + "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O", + "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O", + "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O", + "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O", + "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O", + "CPU1_UPHY3_PRSNT1_L-I","", + "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS", + "CPU1_UPHY2_PRSNT1_L-I","", + "CPU1_UPHY2_PRSNT0_L-I","", + "CPU1_UPHY1_PRSNT1_L-I","", + "CPU1_UPHY1_PRSNT0_L-I","", + "CPU1_UPHY0_PRSNT1_L-I","", + "CPU1_UPHY0_PRSNT0_L-I","", + "FAN1_PRESENT_L-I","", + "FAN0_PRESENT_L-I","", + "","", + "IPEX_CABLE_PRSNT_L-I","", + "M2_1_PRSNT_L-I","", + "M2_0_PRSNT_L-I","", + "CPU1_UPHY4_PRSNT1_L-I","", + "CPU0_UPHY4_PRSNT0_L-I","", + "","", + "I2C_RTC_ALERT_L-I","", + "FAN7_PRESENT_L-I","", + "FAN6_PRESENT_L-I","", + "FAN5_PRESENT_L-I","", + "FAN4_PRESENT_L-I","", + "FAN3_PRESENT_L-I","", + "FAN2_PRESENT_L-I","", + "IOBRD0_IOX_INT_L-I","", + "IOBRD1_PRSNT_L-I","", + "IOBRD0_PRSNT_L-I","", + "IOBRD1_PWR_GOOD-I","", + "IOBRD0_PWR_GOOD-I","", + "","", + "","", + "FAN_FAIL_IN_L-I","", + "","", + "","", + "","", + "PDB_CABLE_PRESENT_L-I","", + "","", + "CHASSIS_PWR_BRK_L-I","", + "","", + "IOBRD1_IOX_INT_L-I","", + "10GBE_SMBALRT_L-I","", + "PCIE_WAKE_L-I","", + "I2C_M21_ALERT_L-I","", + "I2C_M20_ALERT_L-I","", + "TRAY_FAST_SHDN_L-I","", + "UID_BTN_N-I","", + "PWR_BTN_L-I","", + "PSU_SMB_ALERT_L-I","", + "","", + "","", + "NODE_LOC_ID[0]-I","", + "NODE_LOC_ID[1]-I","", + "NODE_LOC_ID[2]-I","", + "NODE_LOC_ID[3]-I","", + "NODE_LOC_ID[4]-I","", + "NODE_LOC_ID[5]-I","", + "FAN10_PRESENT_L-I","", + "FAN9_PRESENT_L-I","", + "FAN8_PRESENT_L-I","", + "FPGA1_READY_HMC-I","", + "DP_HPD-I","", + "HMC_I2C3_FPGA_ALERT_L-I","", + "HMC_I2C2_FPGA_ALERT_L-I","", + "FPGA0_READY_HMC-I","", + "","", + "","", + "","", + "","", + "LEAK_DETECT_ALERT_L-I","", + "MOD1_B2B_CABLE_PRESENT_L-I","", + "MOD1_CLINK_CABLE_PRESENT_L-I","", + "FAN11_PRESENT_L-I","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "","", + "RSVD_SGPIO_IN_CRC[0]","RSVD_SGPIO_O_CRC[7]", + "RSVD_SGPIO_IN_CRC[1]","RSVD_SGPIO_O_CRC[6]", + "RSVD_SGPIO_IN_CRC[2]","RSVD_SGPIO_O_CRC[5]", + "RSVD_SGPIO_IN_CRC[3]","RSVD_SGPIO_O_CRC[4]", + "RSVD_SGPIO_IN_CRC[4]","RSVD_SGPIO_O_CRC[3]", + "RSVD_SGPIO_IN_CRC[5]","RSVD_SGPIO_O_CRC[2]", + "RSVD_SGPIO_IN_CRC[6]","RSVD_SGPIO_O_CRC[1]", + "RSVD_SGPIO_IN_CRC[7]","RSVD_SGPIO_O_CRC[0]"; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2_default>; + status =3D "okay"; + // Data SPI is 64MB in size + flash@0 { + label =3D "config"; + spi-max-frequency =3D <50000000>; + status =3D "okay"; + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + u-boot-env@0 { + // 256KB + reg =3D <0x0 0x40000>; + label =3D "u-boot-env"; + }; + + rwfs@40000 { + // 16MB + reg =3D <0x40000 0x1000000>; + label =3D "rwfs"; + }; + + log@1040000 { + // 40MB + reg =3D <0x1040000 0x2800000>; + label =3D "log"; + }; + }; + }; +}; + +&uart1 { + status =3D "okay"; +}; + +// Enabling SOL +&uart3 { + status =3D "okay"; +}; + +// BMC Debug Console +&uart5 { + status =3D "okay"; +}; + +// USB Port B Controller +&uhci { + status =3D "okay"; +}; + +// USB port A vhub +&vhub { + status =3D "okay"; +}; + +&video { + memory-region =3D <&video_engine_memory>; + status =3D "okay"; +}; --=20 2.43.0