From nobody Thu Oct 2 22:40:29 2025 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 903A11F3BAE; Wed, 10 Sep 2025 03:06:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473566; cv=none; b=a5WdrYq+6sJHvWSYJKHmYeQTKOsODCQyuG5qidsUPhRgJOCxSCYuOxOKiXnnOkOu6Zru60kyU0fuMi5NtgBB+sQEUujaSixNIT0772kAJ/I12ARuxB9vy1Ch8a4dOTCDBkXODl5fSjmX4RiK66h/FOtwuVrz1KJA32zzp3w7CE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473566; c=relaxed/simple; bh=x7Nhy2p6x6dpnDCTAhpQcAybiGnaauxFUjBRMxr2l9E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fGLCkvIGnmgNkiKiLMgjHq4NMkdDb7IZODgZr0l6mG7mp199QyW78ajNS8v1HOHAfXy9U89ctusNgWTxRckqpYAobbxbBuS4mgfIa134jV9NY1/G8grGR084jMdPsS9bDMLOMLZiUEYTxUa7npupiqIjTXQM4CycrGAprdz4xOc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=C1lLdInW; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="C1lLdInW" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-7723f0924a3so8301015b3a.2; Tue, 09 Sep 2025 20:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757473564; x=1758078364; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lApSKWlbDDCVaUIvBgJHVYgBpeBz7q+50mzfJPpQ9Tw=; b=C1lLdInWaYRmRZzsxhUQl/S73bAoPIuQ/Qqkp4aax5RsKPQd+fHTg1SSFb8/V569Av 0vHo3Njz9ukUr0eL7AOPyC/STZN84Vihw0CnVRqB1CQu6RLRFQs+k6t7TgWWKDxG4z6b D508VcsYE2V61rw1w7vKMF/ZlIU6dH4wbQFO27sTFxxfnQVx4ftKMo5OWSrx9Hcx1jIO PDoKLV53tD8RTJ0NHGAhwtrwcM6bmrmhJN3KPC5vQ7VJtbyKu1NLw1Krcbb/ExIZcULI Fb8zSaJfVEYCChDnaUqzVcxgXXI0FgCjoe8gQcu596HhroAu9oULU0wU8zzdcnJ/RKqj bSMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757473564; x=1758078364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lApSKWlbDDCVaUIvBgJHVYgBpeBz7q+50mzfJPpQ9Tw=; b=rg9eVK/14UpBkhAh3+AFmhrrFUHgQrJkHlcUJ06vso66PblxJc6oCAuofPfF7XirPo k3sGyF6ia8ptO3uZUjvXWXrPYXGwdM2ziY3i0IroWUmFFYbUw1haNsHdBWu9jA2b493a Qwd35rDlgwtSMNMr2RWpjLHzJkirLhd4vp9ffX6fkwIO9tkN62fAxF1tFuLDv1ul9tdf +d6o74RmfDzyOr6Am9+ew2JlDvyAnOBTimSteQIRayl2GNsNsF/ctiEDIgyWwFGzvvrm 3HyhIHZ67Hwuosx5Mve9CAjlC8hmQsK18XgZMZWZEuxajF/eX0hm8UyoskY/FwbaB2vn vb1A== X-Forwarded-Encrypted: i=1; AJvYcCUuiBhMrp2HJ2HuVZR8iDlvSdayCPRjrYsumisdP4sc6EmsY1aa0jT0By1l3TnGW7iVdyXviqFzsyZJ0Q4y@vger.kernel.org, AJvYcCWfPUeiNOEawgXOn3itKkZ0SZITF42zZYOPQOJOLSDFEnyBFBTZ+woKrBJzfxUu8uwZnXLd6y7TAawK@vger.kernel.org X-Gm-Message-State: AOJu0Yw3rdmCtG9BWm60sY7NCubhFUmsRQCbeyBTP3WmvUNP7d6z3Gni +Ye0WX2V5INF+R3gttqDMP32ULglNUzsUTTjepWkvprw4NnScmt43IPl X-Gm-Gg: ASbGncvSTjcWp+PhSVwRSnXvcMiJYoS+ir2N4atx7UZlAc0RsnBy9ULXDhBdcJF4Y3E 6nIyFwS1mZvlm1b9aEQSAhOygKfetEY1RToj2bTGyJ/tgPBesXT9F9VceAYtkc8AKetDbEEEaoP h+S09FnKsYw0qOkdnEe8jYlTeIjQupGcLSJvpXzJvVV3Q356dDn9NAMpQTFFKrUZczX32FEqIAR 1huyKyyabhhnAbxcyX8gRQ+hQ4cEW2KvX/S+jrG6xtYaKzIrK8r0q+7IEO86L6FN0BCidd5524E AYdC4s3FzOnXQaOVziYyXfjt0OkLUHyisyezJVq/JHIHG0PoL25aQAtzaE1IbI7EMtqF1A1XSVv DjEnc0rpUNMSPftk6rarlkF9gvqwqmQR00Wu+TwVuJvZmNpxGECwWU9uWucak4Ecj+QYPLIYH65 z1cjyAnxmLxyWTiEViAWhrv1AuwpHIs5Qw0xHX9/RDzySN6Mghbg3ksPY= X-Google-Smtp-Source: AGHT+IHCY2/ZUuieJa6b8+0cszmNX36/5F/Lrag0799NXHCWBy1pFhZxsR4kZ6/iF+Li0mFGFmNmFw== X-Received: by 2002:a05:6a21:998d:b0:24e:e270:2f5d with SMTP id adf61e73a8af0-2534547a6fbmr21524873637.43.1757473563820; Tue, 09 Sep 2025 20:06:03 -0700 (PDT) Received: from twhmp6px (mxsmtp211.mxic.com.tw. [211.75.127.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-774662908a5sm3512047b3a.60.2025.09.09.20.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 20:06:03 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id F16A2800FC; Wed, 10 Sep 2025 11:10:36 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: tudor.ambarus@linaro.org, mmkurbanov@salutedevices.com, Takahiro.Kuwano@infineon.com, pratyush@kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 1/3] dt-bindings: mtd: spi-nand: Add enable-randomizer-otp property Date: Wed, 10 Sep 2025 11:02:59 +0800 Message-Id: <20250910030301.1368372-2-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250910030301.1368372-1-linchengming884@gmail.com> References: <20250910030301.1368372-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Add a new boolean property "enable-randomizer-otp" to enable the randomizer feature on supported SPI-NAND devices. Signed-off-by: Cheng Ming Lin --- Documentation/devicetree/bindings/mtd/spi-nand.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/spi-nand.yaml b/Document= ation/devicetree/bindings/mtd/spi-nand.yaml index 77a8727c7..432bc79e9 100644 --- a/Documentation/devicetree/bindings/mtd/spi-nand.yaml +++ b/Documentation/devicetree/bindings/mtd/spi-nand.yaml @@ -21,6 +21,10 @@ properties: description: Encode the chip-select line on the SPI bus maxItems: 1 =20 + enable-randomizer-otp: + description: Enable the randomizer feature + type: boolean + required: - compatible - reg --=20 2.25.1 From nobody Thu Oct 2 22:40:29 2025 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FFB3263F52; Wed, 10 Sep 2025 03:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473568; cv=none; b=qRst665e4xlThtvWx2bNXAyxbukh/JkrkNlFStEc0XvqjcHSU2yzzoWWxSynha2SWKEE1PGkByW5V6XUhb5MD4gkgd1MTMz5GeQHtDUZug5YfLAYzeuW7Sr5Kn/5y8BzwqdDSaqvSBy1HCux2vgS3uoPxkVXAPPln1ep7K32kSw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473568; c=relaxed/simple; bh=ClKHMj7+eQj549knrXAT6PHut2TRrIvc0PmKzpsj0aU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Bp64rpBipcNRdZ967dnrjTtz12nybBTfAgtiwNMUc381Me3CqEuu68JvXSNS8wwZH/32rvRfR0rvYOMBXfglifmkWuH7jrzqPb1r825+T7jPKemb/mh4wRXmnRw7tOGaoG6z943rBZ7qdCNlTw0WteLJs/mkOL7VTxf9uNTYzI0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JRNX4WEQ; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JRNX4WEQ" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-32b590d819aso5473231a91.3; Tue, 09 Sep 2025 20:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757473566; x=1758078366; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uTD4jfZ+v4XVtMAIsHdMuiuSYceyzDlRY16CdCXeB+w=; b=JRNX4WEQ8szeXeZsV8ytUZluIe46CTi4qR1vgYMKolY+NibjNO1QI+Zl6QobGJz9vc l9zMsTYDX8FOMhUaL+/hxSl1jZ/re3rPVGKbhOnExtyPZo9qYPeZwFTggsk/CONUYBJ1 khxRduD9N1/TWhgWW5x4txuL+B3pQu4XU6juaOxd8eOVDRh8OgSSLMZ1V4O8xaUNHE45 orO0A/UA4HfTGsqG5xkrhcWk+ezZmcIqam/3ZZbRlvHE29lMG5S2/XIjiRb05F6+k/py VGg3pQyC4zZbVu3gIZ4WKDHRr2xpzAE3O9hr0MXlvdNra7eS609BHbLFuwLWLuIRzEMo NYNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757473566; x=1758078366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uTD4jfZ+v4XVtMAIsHdMuiuSYceyzDlRY16CdCXeB+w=; b=HIpZ5CKOgypv/GxGJP9nDxQlF6KVo14lup4yAsF/EUWTJG7ODnC28bOby5uv2PA7CJ My9IR9UiFvK3Qb5UmrUQ9sQr2qWtm2WxB5jYV/thSt5OSMPPMSMX4uQNJlI7IbvjQXNM DxKpkKY3kFVtyIgjLzTfzAHQHKLf8TAkKQ/SwvKiFdga2ahcq5bHwQ9TXDehgvNrg98U wTFNEUqCQxbg9V05/AE3rq92NvXhWtJrdKJdJb560GoTKNjUz9YMNm4KKTUkzKgbqYrY nQKlrXIMu2O8USnCFcs/jfdZP0gkqFmCe/x6qa+0VoM5kAYzER4FUXGTtkj6pK+eoHRl owSg== X-Forwarded-Encrypted: i=1; AJvYcCWnpyAjKIgRQ5Abxa3h/VBgjq5K+53gOYvD3UBxjSUYQzSK9DZcoBXUDbdZwefYI2ubJcnCQmyiRv1S@vger.kernel.org, AJvYcCWwyC33mSV/uk45/aFKerKjQ8wWw3etmgX6rAx1Au6U0EDqKw1GkoyaBXswUxQXQFh/OS7UHz5MeeTimhg9@vger.kernel.org X-Gm-Message-State: AOJu0Yyu2d+2haQGb5IU3cR07SZOsMuexCXiKrKoeoFYlwos8u2j/Qot Qz+xU54X0MsrcbrB4n7a59acDT2zbcqhbrX7L2L/TB+U2Jq5s0BJG4af X-Gm-Gg: ASbGncsILuSfteiDuK2TaB4Q+YzDcsT3/bnI3hdBu0LaMMiqcYt84OQ8YcLk3pS2fNz ByH5kDBrqMyKwMnMEkrnMH7HMpru3popU9eH2V9n9mtzh/sKrWar3a3R9GAiuSgDFuVRzn5a446 RqOZD2hiAX/N70+zE5EWBqWtsjxOtjQt5GFhi+DG/TiuItZ+8GTSVd5mTVSFVzOtQFzGe7yOCKL /Yj9bpWpAj+YKp/O+wX1WGhRu//8EC7v3poIeOKKoVUzJQ6uwsdCgLk1C99aa1Y6olimS6maL0J /Osv0udqlB2Z98/xtlqtqzYlM3g8GCVklrq2hftI3W7YW/kMWP+NDsT5vpt3xpJuQcT/rCY5slR 8JMDlaAE+1Yp1YbzHN+jI3bavi6nzEYvjGnwVDc7qVKtH/n8Q00K/BA4DcTPbwZhTf44vaCsP2i aajg8+qjHQtl+YvULYSUHbPMyOvlIiA5M7OejPKJDVb+d1fgZCUN3Oo7Y= X-Google-Smtp-Source: AGHT+IH28usqYyuiorxIFP4IsRvkvrFAv/8CQm1Kx2W+C4unMcjMCStN7qDcg/tOWpZ0Mdpz4/RywA== X-Received: by 2002:a17:90b:1dcb:b0:329:ed5b:ecdb with SMTP id 98e67ed59e1d1-32d43fb5b92mr18030127a91.18.1757473565788; Tue, 09 Sep 2025 20:06:05 -0700 (PDT) Received: from twhmp6px (mxsmtp211.mxic.com.tw. [211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32dbb5f3deesm672029a91.14.2025.09.09.20.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 20:06:05 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 570A8802C7; Wed, 10 Sep 2025 11:10:38 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: tudor.ambarus@linaro.org, mmkurbanov@salutedevices.com, Takahiro.Kuwano@infineon.com, pratyush@kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 2/3] mtd: spi-nand: Add support for randomizer Date: Wed, 10 Sep 2025 11:03:00 +0800 Message-Id: <20250910030301.1368372-3-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250910030301.1368372-1-linchengming884@gmail.com> References: <20250910030301.1368372-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Introduce randomizer initialization for SPI-NAND devices. According to JESD22-A117E, there is no single data pattern that represents a universal worst-case across all failure mechanisms. Different mechanisms may stress programmed cells, erased cells, or cells influenced by adjacent states, and thus specific patterns such as fully programmed, checkerboard, or mostly erased are each only worst-case for certain desings or processes. Given that no fixed pattern can cover all cases, the use of a randomized data pattern is considered a practical mitigation strategy. A randomizer distributes stress more evenly across the device by scrambling incoming data before storage and restoring it on read. This helps reduce pattern-dependent degradation and can therefore improve flash reliability. Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/core.c | 24 ++++++++++++++++++++++++ include/linux/mtd/spinand.h | 7 +++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index ea47028d0..770304403 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -854,6 +854,25 @@ static void spinand_cont_read_init(struct spinand_devi= ce *spinand) } } =20 +static int spinand_randomizer_init(struct spinand_device *spinand) +{ + struct nand_device *nand =3D spinand_to_nand(spinand); + struct device_node *dn =3D nanddev_get_of_node(nand); + int ret, rand_dt; + + rand_dt =3D of_property_read_bool(dn, "enable-randomizer-otp"); + if (!rand_dt) + return 0; + + if (spinand->set_randomizer) { + ret =3D spinand->set_randomizer(spinand); + if (ret) + return ret; + } + + return 0; +} + static bool spinand_use_cont_read(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops) { @@ -1367,6 +1386,7 @@ int spinand_match_and_init(struct spinand_device *spi= nand, spinand->user_otp =3D &table[i].user_otp; spinand->read_retries =3D table[i].read_retries; spinand->set_read_retry =3D table[i].set_read_retry; + spinand->set_randomizer =3D table[i].set_randomizer; =20 op =3D spinand_select_op_variant(spinand, info->op_variants.read_cache); @@ -1544,6 +1564,10 @@ static int spinand_init(struct spinand_device *spina= nd) */ spinand_cont_read_init(spinand); =20 + ret =3D spinand_randomizer_init(spinand); + if (ret) + goto err_cleanup_ecc_engine; + mtd->_read_oob =3D spinand_mtd_read; mtd->_write_oob =3D spinand_mtd_write; mtd->_block_isbad =3D spinand_mtd_block_isbad; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 927c10d78..66ea8eed4 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -500,6 +500,7 @@ struct spinand_user_otp { * @user_otp: SPI NAND user OTP info. * @read_retries: the number of read retry modes supported * @set_read_retry: enable/disable read retry for data recovery + * @set_randomizer: enable randomizer * * Each SPI NAND manufacturer driver should have a spinand_info table * describing all the chips supported by the driver. @@ -521,6 +522,7 @@ struct spinand_info { int (*configure_chip)(struct spinand_device *spinand); int (*set_cont_read)(struct spinand_device *spinand, bool enable); + int (*set_randomizer)(struct spinand_device *spinand); struct spinand_fact_otp fact_otp; struct spinand_user_otp user_otp; unsigned int read_retries; @@ -579,6 +581,9 @@ struct spinand_info { .read_retries =3D __read_retries, \ .set_read_retry =3D __set_read_retry =20 +#define SPINAND_RANDOMIZER(__set_randomizer) \ + .set_randomizer =3D __set_randomizer + #define SPINAND_INFO(__model, __id, __memorg, __eccreq, __op_variants, \ __flags, ...) \ { \ @@ -634,6 +639,7 @@ struct spinand_dirmap { * @user_otp: SPI NAND user OTP info. * @read_retries: the number of read retry modes supported * @set_read_retry: Enable/disable the read retry feature + * @set_randomizer: Enable the randomizer feature */ struct spinand_device { struct nand_device base; @@ -667,6 +673,7 @@ struct spinand_device { bool cont_read_possible; int (*set_cont_read)(struct spinand_device *spinand, bool enable); + int (*set_randomizer)(struct spinand_device *spinand); =20 const struct spinand_fact_otp *fact_otp; const struct spinand_user_otp *user_otp; --=20 2.25.1 From nobody Thu Oct 2 22:40:29 2025 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C8AC265298; Wed, 10 Sep 2025 03:06:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473569; cv=none; b=mUCgdcrW9fpel/U9uTsKftz7pCk0ZMxxS9SAJs56UHB24BFMCZrtn/2kfmQhqflizxjmt6LzyFkuY54dLHCQIXdqQL4Le32L3Fi12MyIkNXRSLIZnsEEgQUlCt6x5xbKAvmj89Lh6vNc6eXHFtKvw0coaGTnb98tU10uO495u7I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473569; c=relaxed/simple; bh=eu5PJ687HqYgIi4QPsqNXeNaD1HG6MbkGt0mNUlLe/4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=K2MEESkvzZiM9XDuw/Mm9yZR+PLIJkSz5rBwdmbXAJ9xhAM09ta9CuluqoYuR+c2W4/cb0HC3PoMbBV5G31OpE90u66Npdmn5KzWBNL0JSbMVcgdho6W8+1Th7zFzq3K2tK3/aHmGKEtzbk83Vgg3AuMyBhT+V8zdekEdu7fSjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PQnN8lvA; arc=none smtp.client-ip=209.85.210.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PQnN8lvA" Received: by mail-pf1-f178.google.com with SMTP id d2e1a72fcca58-77238cb3cbbso6655878b3a.0; Tue, 09 Sep 2025 20:06:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757473566; x=1758078366; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jfsu13HN8biP/n/EW77zykxwoqDcdIlmZQ9zgwYNdFA=; b=PQnN8lvAG6TVkCa2Xg3rSNAQZWgq5rfuGTIIvmUuTGMYbACEe9B93+ViaEP+4zEw3M X0vBjri2MmSXcXr33HaLbL2Bqy38gdmyDb2pZYEt3Naffm3NZAfBHICAyZPKuhKFLHpa UrCedAkqdmf9kLqu1LBlLbSgpU/lTjjz9AqT4c7bOPvhWALNp6FvTHBRjgjnxaXWJCij W4VipxRTnQsd/HHlI2GGbLKUVPFHe4/61FbjQW4H+Kdo5Pq9gv3Q5IIQAEdBbyhX+LaI d5Jo2LIfDYYs6olkYrIVUJRv47AKH8+tScj7Fpozf3X0uOuao/8XOTnsAKNyPpGzuAB7 eMMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757473566; x=1758078366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jfsu13HN8biP/n/EW77zykxwoqDcdIlmZQ9zgwYNdFA=; b=FIg1r+7h0SHUt7Bp+NtqFE5bK/sBig9hDP8O8ZAb2OYifTJTSH3XRhe06QWrgHbWzw TyJSmbcbV2xz/EXr9jxAV5826iEOME5+J58wKSCcMiSKlS6IKOKtggzg9AK4Jz7bx9W0 U0jm5kMXwb1EuVRSAf7GxDcfjxULbbcofssH06+XskoZ7CZYs1wWK7sItYAOQU3Bt5cB iu2LEd/U+0vReZoudEnLQw0cOAz0zQBze004782BTnBpJGwA+r7joOTiVhcUXJpWu6PE z5epx3E+4d7C9UXG6RG9aaZkboMFJZhFn6un5Pj5V4S23AoYJHbYCc11bIBetkxI1AEA LTJw== X-Forwarded-Encrypted: i=1; AJvYcCU7+eToZbsD0l2DMeHfwNKlWl1jCBDCE6cQLHKojoW9GYqEFhmNeCCTP33L59EAhSf97nYYnroMaoj9NJVK@vger.kernel.org, AJvYcCWAfPP4ikpF46lLtZ3r4tjH+hqKyJgz549nVEsSuQVfKZoxbti3kxSLdJE3uTEU1zyMRNWWXecmiGPv@vger.kernel.org X-Gm-Message-State: AOJu0Yy145TCjhD0RFRaHW3yJt/W3/eBdanzNWxPT370uJLvajw9m26g v9PdVMOzUVbdb43/dalgLHoNMp8AsGUcKXlVjkTgdTpKT510x2qGCxLt X-Gm-Gg: ASbGncublOoJRk04sfGDMalvxpQ5jvWwkHWJVtTUyFJMZ9lOQ28naE3oLkmEKALP5Qp pOyFwPPaGops/Ghf0QDiLmlfGP1wLdc7Ztav3QFyyDbnQiaiP2lLMnOmEhaJ3vAUMN0VrtZR0Tt OTv4Uop9K18/FhHJXGiCo7FwfPezer7EXrM7WJXNiLlp9xFh2+4LG3E81nSJE/MsaXlkpgqBa8Q UP2REBJvrsE1i3jvS/Wr2Xu4boimKKqQDBAy1XkZqXF4hCK53FQe6MXsWIYVr8zsLCtyGWsxY3s sQXrNcyDs51qJGW6XUJ5D00c/MYgsF6k0E9ZXqMYlzrZJsKmyO70BzgD1J3R1r/qXFiGVMAeF9N 48NuZiavGIHSDOPVMSp/MTFjjG79bftdxAJLysyd3LhVn5YxxBtlF/8uDasVBxqjHciX3bWnX2/ bKYwaVljiMUjpNlHrA+I2oyyOWvh0AZ1nh/w2LKbagmn99CHwPCByFeVg= X-Google-Smtp-Source: AGHT+IH5S+qulOuahC60MPb/08HMw3Py358hrTsN36Vcd02nHOLBhopc+QqWl4qPf7wjy70VRA23tQ== X-Received: by 2002:a05:6a21:7781:b0:253:6b75:babc with SMTP id adf61e73a8af0-2536b75bdf1mr17467774637.46.1757473566397; Tue, 09 Sep 2025 20:06:06 -0700 (PDT) Received: from twhmp6px (mxsmtp211.mxic.com.tw. [211.75.127.162]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b548a50c49csm1071459a12.15.2025.09.09.20.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 20:06:05 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 0EC6B804B6; Wed, 10 Sep 2025 11:10:39 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: tudor.ambarus@linaro.org, mmkurbanov@salutedevices.com, Takahiro.Kuwano@infineon.com, pratyush@kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alvinzhou@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 3/3] mtd: spi-nand: macronix: Add randomizer support Date: Wed, 10 Sep 2025 11:03:01 +0800 Message-Id: <20250910030301.1368372-4-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250910030301.1368372-1-linchengming884@gmail.com> References: <20250910030301.1368372-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin Enable randomizer function by specific flowchart to set the default value of RANDEN to 1. Randomizer introduces a new DT property "mxic,randopt" to define the randomizer area per page. The penalty of randomizer are subpage accesses prohibited and more time period is needed in program operation and entering deep power-down mode. i.e., tPROG 320us to 360us (randomizer enabled). Signed-off-by: Cheng Ming Lin --- drivers/mtd/nand/spi/macronix.c | 89 +++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macroni= x.c index edf63b999..7450ee1d3 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -14,6 +14,10 @@ #define MACRONIX_ECCSR_BF_LAST_PAGE(eccsr) FIELD_GET(GENMASK(3, 0), eccsr) #define MACRONIX_ECCSR_BF_ACCUMULATED_PAGES(eccsr) FIELD_GET(GENMASK(7, 4)= , eccsr) #define MACRONIX_CFG_CONT_READ BIT(2) +#define MACRONIX_CFG_ENPGM BIT(0) +#define MACRONIX_CFG_RANDEN BIT(1) +#define MACRONIX_CFG_RANDOPT BIT(2) +#define MACRONIX_FEATURE_ADDR_RANDOMIZER 0x10 #define MACRONIX_FEATURE_ADDR_READ_RETRY 0x70 #define MACRONIX_NUM_READ_RETRY_MODES 5 =20 @@ -155,6 +159,61 @@ static int macronix_set_read_retry(struct spinand_devi= ce *spinand, return spi_mem_exec_op(spinand->spimem, &op); } =20 +static int macronix_set_randomizer(struct spinand_device *spinand) +{ + struct spi_mem_op exec_op =3D SPINAND_PROG_EXEC_1S_1S_0_OP(0); + struct nand_device *nand =3D spinand_to_nand(spinand); + struct device_node *dn =3D nanddev_get_of_node(nand); + int randopt, ret; + u8 cfg, status; + + ret =3D spinand_read_reg_op(spinand, MACRONIX_FEATURE_ADDR_RANDOMIZER, &c= fg); + if (ret) + return ret; + if (cfg) + return 0; + + cfg =3D MACRONIX_CFG_ENPGM | MACRONIX_CFG_RANDEN; + randopt =3D of_property_read_bool(dn, "mxic,randopt"); + if (randopt) + cfg |=3D MACRONIX_CFG_RANDOPT; + + ret =3D spinand_write_reg_op(spinand, MACRONIX_FEATURE_ADDR_RANDOMIZER, c= fg); + if (ret) + return ret; + + ret =3D spinand_write_enable_op(spinand); + if (ret) + return ret; + + ret =3D spi_mem_exec_op(spinand->spimem, &exec_op); + if (ret) + return ret; + + ret =3D spinand_wait(spinand, + SPINAND_WRITE_INITIAL_DELAY_US, + SPINAND_WRITE_POLL_DELAY_US, + &status); + if (ret) + return ret; + + if (status & STATUS_PROG_FAILED) + return -EIO; + + ret =3D spinand_read_reg_op(spinand, MACRONIX_FEATURE_ADDR_RANDOMIZER, &s= tatus); + if (ret) + return ret; + if (status !=3D cfg) + return -EIO; + + cfg &=3D ~MACRONIX_CFG_ENPGM; + ret =3D spinand_write_reg_op(spinand, MACRONIX_FEATURE_ADDR_RANDOMIZER, c= fg); + if (ret) + return ret; + + return 0; +} + static const struct spinand_info macronix_spinand_table[] =3D { SPINAND_INFO("MX35LF1GE4AB", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12), @@ -213,7 +272,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF2G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1), @@ -225,7 +285,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_PROG_PLANE_SELECT_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x64, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -236,7 +297,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF4G24AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 2, 1, 1), @@ -248,7 +310,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_PROG_PLANE_SELECT_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35LF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x75, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -259,7 +322,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX31LF1GE4BC", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), @@ -305,7 +369,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF4G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xf5, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -317,7 +382,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF4GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7, 0x03), NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), @@ -355,7 +421,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF2G24AD-Z4I8", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xe4, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -367,7 +434,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF2GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6, 0x03), NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), @@ -413,7 +481,8 @@ static const struct spinand_info macronix_spinand_table= [] =3D { SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, macronix_ecc_get_status), SPINAND_READ_RETRY(MACRONIX_NUM_READ_RETRY_MODES, - macronix_set_read_retry)), + macronix_set_read_retry), + SPINAND_RANDOMIZER(macronix_set_randomizer)), SPINAND_INFO("MX35UF1GE4AD", SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96, 0x03), NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), --=20 2.25.1