From nobody Wed Sep 10 23:24:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E22A327A12; Wed, 10 Sep 2025 17:39:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757525965; cv=none; b=Jqo7Q5Rk7OvJxOzwCMXVEjdplmVe1Q6BjWWkxjN2L0yQaWF1LYk46U9F59Mvb9jsPqxcO7mwhJRD9qomJZmA5D0EsMr7bxqueK60wqEZmki+0dHFaGKoJSdId8lUUur8l0hLs6I3I4D2B36fun0MmLT9hpKfl+DK0t5jzMwKWUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757525965; c=relaxed/simple; bh=suPO+5JTYQEo4LDSfjlfIJExBwCp9N3UqosjVAZBfYk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ClGTjEOTJO/r/U2junVAI9N5WOCq2vkpzTO5rtQfB+OYFAo7HG3uxuUuC2gk/dUv+ieD/ti/MezDdfv3ooorTXXQkEhJuxsjmvmf+h5ITjbTi9tFgwQkzpKTkp2n8xiuvj5kH1L4xMeyKRvX6IkL5OBAfKn1EwF3wJEEklsNhak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VrgNK5nm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VrgNK5nm" Received: by smtp.kernel.org (Postfix) with ESMTPS id D1AE7C4CEF0; Wed, 10 Sep 2025 17:39:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757525964; bh=suPO+5JTYQEo4LDSfjlfIJExBwCp9N3UqosjVAZBfYk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VrgNK5nmBoFy0slg+DVdiE48DDr4ahNcvj8aM9UsPrN44mm1DL43iwx+H5wrAWlHx fuNYbEw+BtBCYNhQnIhD9nxTk7OJRHSaISnF6X+wjdPCI69WBQUwFS8HC6NCLeUoeQ HRaESDCsL6CbJSvQtuW2oxdzSiAwH7zC2AHQkkojVNV4iG6R0ytEvFzWQ0xdiDH1h6 PcRmJ1KfIhKr6YpBPuDilLxZB5DIHcBwYsCoKl4JN5KBaFVPRa/tCfrHhukYH5aH8y AApmCQnPZnbHR0bnaXr2aaTBFgmcmvsyJwIqp/2J7g5NLuKY1zyjUKypb06A+xR3Rr vS4x8mw3IbwFg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6A27CA0FED; Wed, 10 Sep 2025 17:39:24 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 10 Sep 2025 23:09:20 +0530 Subject: [PATCH 1/2] PCI: Extend pci_idt_bus_quirk() for IDT switch with Device ID 0x8090 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-pci-acs-v1-1-fe9adb65ad7d@oss.qualcomm.com> References: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> In-Reply-To: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> To: Bjorn Helgaas , Joerg Roedel , Will Deacon , Robin Murphy , Greg Kroah-Hartman Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel , iommu@lists.linux.dev, Anders Roxell , Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Manivannan Sadhasivam , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1800; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=F1zn/e3u//vrD8NT+S3b2bYGHBAjod1HSL73CfBCa2s=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBowbfKIsbljvZZO1jxubZqxR2RwT326BD2EYLym lsxnouTuiOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaMG3ygAKCRBVnxHm/pHO 9eecCACj8Q14c0+RcOMVe1jcVdN2q2XiQtNonvov3RaMAGPhIpkrpyRFgd+MK1H1V4sT1X8oHQd 9X+4cBk2lJ+K9CtrvCGiJXyfVqtGLkle3/YdUJ33o1lfFKnfeTk9O70ZjI3TQ1zYSwxR/PigPo2 mHD98aR+g84BbtKLKH0LjkI8MsuWenkanDA5rDO1zWC1Dlk04C7bsSjLIaGCt3s7l7EqS2dc3Um b6eE/h921Jt6pHaDR6/D/5FGmJC15PrR5RfD/8LBEF6v7cdBN0k062rXJRzUUkQ/O45nvePw/MS 13BFh/hPSF/czp8yt+DAcde8+fAAqn/bqZNnQfZ1ckxPFGdk X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam If ACS is enabled, the IDT switch with Device ID 0x8090 found in ARM Juno R2 development board incorrectly raises an ACS Source Validation error on Completions for Config Read Requests, even though PCIe r6.0, sec 6.12.1.1, says that Completions are never affected by ACS Source Validation. This behavior is documented in non-public erratum 89H32H8G3-YC and there is already a quirk available to workaround this issue. Hence, extend the quirk for Device ID 0x8090 to make the switch functional if ACS is enabled. Note: The commit mentioned in the Fixes tag causes ACS to be enabled before the enumeration of the switch downstream port. So it ended up breaking PCIe on ARM Juno R2 board, which used to work before this commit until someone forcefully enabled ACS with cmdline. Cc: stable@vger.kernel.org # 6.15 Fixes: bcb81ac6ae3c ("iommu: Get DT/ACPI parsing into the proper probe path= ") Closes: https://lists.linaro.org/archives/list/lkft-triage@lists.linaro.org= /message/CBYO7V3C5TGYPKCMWEMNFFMRYALCUDTK Signed-off-by: Manivannan Sadhasivam --- drivers/pci/probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index f41128f91ca76ab014ad669ae84a53032c7c6b6b..2320818bc8e58c61d9ada312dfb= d8c0fbfbadc0c 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2500,7 +2500,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, = int devfn, u32 *l, * ACS Source Validation errors on completions for config reads. */ if (bridge && bridge->vendor =3D=3D PCI_VENDOR_ID_IDT && - bridge->device =3D=3D 0x80b5) + (bridge->device =3D=3D 0x80b5 || bridge->device =3D=3D 0x8090)) return pci_idt_bus_quirk(bus, devfn, l, timeout); #endif =20 --=20 2.45.2 From nobody Wed Sep 10 23:24:02 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4535432ED52; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-pci-acs-v1-2-fe9adb65ad7d@oss.qualcomm.com> References: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> In-Reply-To: <20250910-pci-acs-v1-0-fe9adb65ad7d@oss.qualcomm.com> To: Bjorn Helgaas , Joerg Roedel , Will Deacon , Robin Murphy , Greg Kroah-Hartman Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Joerg Roedel , iommu@lists.linux.dev, Anders Roxell , Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Manivannan Sadhasivam , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2676; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=s3IWPWrtmYAF1td5P6U9N7afV7EwajwvWtWy1fRfcR0=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBowbfLBKMpPRmXeHjCf82JrGyQlLaBTrURN4KsN QgzqkNRMXCJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaMG3ywAKCRBVnxHm/pHO 9cuaB/9aEE0RS60+8mmPH7waGER7/F4s9uVWLBpZtCDkWRZyWUdJ7SMdDR50TXthG97BiOw0ZEl 4e6l/R90xwaAnmLqpLJMEtBSGR9tGHIrcG+/CiSN5xNqV2SZBSFPxxdsp4DSywhRmXfHw1KShMd RC4g15WALpt1tcpI7nYLmC2Ice8R9lTycjTI23MvuU8H+F5CVsODjWbHUN+5xH1MGM0LoQnpdVd jH1+LY4a3TqtbeSVCGJPg8zBe/WRZzLLGB85PgXMKoINILTQu6Zxt/OlppSIEbwIL9KFB9nYhmW XWvmR+84jPDpHrO27Hyx7es3T68W6UA577cF56W8GUUtYQrl X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Xingang Wang When booting with devicetree, ACS is enabled for all ACS capable PCI devices except the first Root Port enumerated in the system. This is due to calling pci_request_acs() after the enumeration and initialization of the Root Port device. But afterwards, ACS is getting enabled for the rest of the PCI devices, since pci_request_acs() sets the 'pci_acs_enable' flag and the PCI core uses this flag to enable ACS for the rest of the ACS capable devices. Ideally, pci_request_acs() should only be called if the 'iommu-map' DT property is set for the host bridge device. Hence, call pci_request_acs() from devm_of_pci_bridge_init() if the 'iommu-map' property is present in the host bridge DT node. This aligns with the implementation of the ARM64 ACPI driver (drivers/acpi/arm64/iort.c) as well. With this change, ACS will be enabled for all the PCI devices including the first Root Port device of the DT platforms. Cc: stable@vger.kernel.org # 5.6 Fixes: 6bf6c24720d33 ("iommu/of: Request ACS from the PCI core when configu= ring IOMMU linkage") Signed-off-by: Xingang Wang Signed-off-by: Pavankumar Kondeti [mani: reworded subject, description and comment] Signed-off-by: Manivannan Sadhasivam --- drivers/iommu/of_iommu.c | 1 - drivers/pci/of.c | 8 +++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c index 6b989a62def20ecafd833f00a3a92ce8dca192e0..c31369924944d36a3afd3d4ff08= c86fc6daf55de 100644 --- a/drivers/iommu/of_iommu.c +++ b/drivers/iommu/of_iommu.c @@ -141,7 +141,6 @@ int of_iommu_configure(struct device *dev, struct devic= e_node *master_np, .np =3D master_np, }; =20 - pci_request_acs(); err =3D pci_for_each_dma_alias(to_pci_dev(dev), of_pci_iommu_init, &info); of_pci_check_device_ats(dev, master_np); diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3579265f119845637e163d9051437c89662762f8..98c2523f898667b1618c37451d1= 759959d523da1 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -638,9 +638,15 @@ static int pci_parse_request_of_pci_ranges(struct devi= ce *dev, =20 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge) { - if (!dev->of_node) + struct device_node *node =3D dev->of_node; + + if (!node) return 0; =20 + /* Enable ACS if IOMMU mapping is detected for the host bridge */ + if (of_property_read_bool(node, "iommu-map")) + pci_request_acs(); + bridge->swizzle_irq =3D pci_common_swizzle; bridge->map_irq =3D of_irq_parse_and_map_pci; =20 --=20 2.45.2