From nobody Wed Sep 10 23:21:40 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CC8A23ABAF; Wed, 10 Sep 2025 16:16:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757520989; cv=none; b=FRDoJY9qEttTHbhGstus5l59kxHj2NlgX+icrO3ciGtANU8qDIp1MnPifxpNMWhws63AXGj4iq9zpARNuiAawX+SwDnEAOmt/qCU9peSMGVAzJlukgYWy3tysr1dnkYLAMFrpiSaTyiMohRVcMWukYNvf9XV96y9k/BJU8ITLyk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757520989; c=relaxed/simple; bh=3zZCd4F5TNJy+F1irODC06X4kSaGRUOro4Xbmp9NzTc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p+7ppeYYgLR3r2+TfOXNNuzZW4HF8UPHC3omON/bv6AGJ84tJ4rVI/nlryn6On4bvMitlhvDPB/P+AlnRObSeilTMeC7hpqhjsgLL5Molx80zFN81AM1nIuM6DD6jKb7ve57qcJ3r4TviUOxRvI/m0viZK9MpUY5jkIihb9b8y0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=u+J6hsC7; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="u+J6hsC7" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 7A7654E40BBC; Wed, 10 Sep 2025 16:16:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 66436606D4; Wed, 10 Sep 2025 16:16:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 23702102F2915; Wed, 10 Sep 2025 18:16:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757520985; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=AM4ZgSHOUeHDIPf7yX4LJ/KF76YVa1eQBXVvqrWoGMs=; b=u+J6hsC7ooDoxnDGLzRcmYF1x+hfTYFcE2E2MZs5SPRcny4iWEidnvVKcnD2U4CEFCitPx 36vCIE2CbBXFEXNLNbgflYGc4MS+Xd9wC9k/ruvSWxS1eQ1teFliGPF2g8s5TiI3IbB3tI 4FletdLCm02B+iwLww9fM6k477a8f7Ys7ck963JsjCuxgk//KbM1ePvvYcRfxsvtvpgeCK N7q3OrPxg84warMgwJ8gW4HyDwc8GW3liqLtBR+S/ml7eI/Xf2ViBtlv0KjlGCIeowLwuT tFxCn4Sg1IOTKJs4x84G9F+VN7i1FWvRbswymdvvJYeO7OTVpRIJSnkCrNuwXg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 10 Sep 2025 18:15:30 +0200 Subject: [PATCH net v5 1/5] dt-bindings: net: cdns,macb: allow tsu_clk without tx_clk Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-macb-fixes-v5-1-f413a3601ce4@bootlin.com> References: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> In-Reply-To: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Geert Uytterhoeven , Harini Katakam , Richard Cochran , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Allow providing tsu_clk without a tx_clk as both are optional. This is about relaxing unneeded constraints. It so happened that in the past HW that needed a tsu_clk always needed a tx_clk. Fixes: 4e5b6de1f46d ("dt-bindings: net: cdns,macb: Convert to json-schema") Reviewed-by: Krzysztof Kozlowski Acked-by: Nicolas Ferre Signed-off-by: Th=C3=A9o Lebrun --- Documentation/devicetree/bindings/net/cdns,macb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documen= tation/devicetree/bindings/net/cdns,macb.yaml index 559d0f733e7e7ac2909b87ab759be51d59be51c2..6e20d67e7628cd9dcef6e430b2a= 49eeedd0991a7 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -85,7 +85,7 @@ properties: items: - enum: [ ether_clk, hclk, pclk ] - enum: [ hclk, pclk ] - - const: tx_clk + - enum: [ tx_clk, tsu_clk ] - enum: [ rx_clk, tsu_clk ] - const: tsu_clk =20 --=20 2.51.0 From nobody Wed Sep 10 23:21:40 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39FF325C80E for ; Wed, 10 Sep 2025 16:16:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757520999; cv=none; b=VJV0o8ZbaYrPILON07WcoP/Yp9ICf+ZbsjBDyIZ96KETMscZyieu1IMb2V9gkyoECFduTLCs1N5ULtosoCgrSz9s4I+D/dMn1xaJWrYrzsO2YzZBIqyksCc+tYhmxEc+d9t+2KUv7kmViEcioR34XVhkJsxSqnTFXG0cX5qmtks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757520999; c=relaxed/simple; bh=Hw3S4Yh1b9uVhqXs5nOnRXPDZIBl16sL7jFuN1px3s8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ALUwXg3Gkgzze8Cufb14Mcpoh0m5ww5OjDz12MXDciOtZ5PIYyCMSNyh4ekWCj1Pe726kT0G3ujw9u92e1JClDRwsRwoALr3i2mXOehVRZT6HVl2uPg7HXnCN/8e0o664BVFDWw5caBhV8QsOniXwurtCJ+kX2B+kHEemP2jqzk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ni7JKBdx; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ni7JKBdx" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id B258FC6B38C; Wed, 10 Sep 2025 16:16:19 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 7F3C6606D4; Wed, 10 Sep 2025 16:16:35 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7A0C7102F2870; Wed, 10 Sep 2025 18:16:25 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757520992; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=XWwRlk2s1La7LFWvZ8yGGl3dun8e0qyYKsEMxtd/N1E=; b=ni7JKBdxxxk0nw3HOcz4yns3Ts9nX8kD95XiteM8uxLEhvyqxJwFUvlZC8WCvzQoaWHYBQ cU+MA3Tde0nfLvAUr98QUUzwfF0RaerDOiCdjbGoTJC1vE1aKdByiS9QgLaG4Y0uL0yzJ5 nSIDz0q0T8r6UXHU5k7E1ph5hyJ5pDY2zqQgYfuzx2IE1GnU1KmFrDZgPBTzhGe5BSSJO8 b0mTEdSydPWFTChWUr5g5yUKkL7qGuTKNAOEMlk+tgoR7D/E/Phn1G/lk6yaQtCccGEJFu D8J+NaDL2zrF9ba49OrvQGBJlSWY6CuHUX0IZ5g7PEKE9CsUc8IL83ZKui5Rew== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 10 Sep 2025 18:15:31 +0200 Subject: [PATCH net v5 2/5] net: macb: remove illusion about TBQPH/RBQPH being per-queue Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-macb-fixes-v5-2-f413a3601ce4@bootlin.com> References: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> In-Reply-To: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Geert Uytterhoeven , Harini Katakam , Richard Cochran , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Sean Anderson X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The MACB driver acts as if TBQPH/RBQPH are configurable on a per queue basis; this is a lie. A single register configures the upper 32 bits of each DMA descriptor buffers for all queues. Concrete actions: - Drop GEM_TBQPH/GEM_RBQPH macros which have a queue index argument. Only use MACB_TBQPH/MACB_RBQPH constants. - Drop struct macb_queue->TBQPH/RBQPH fields. - In macb_init_buffers(): do a single write to TBQPH and RBQPH for all queues instead of a write per queue. - In macb_tx_error_task(): drop the write to TBQPH. - In macb_alloc_consistent(): if allocations give different upper 32-bits, fail. Previously, it would have lead to silent memory corruption as queues would have used the upper 32 bits of the alloc from queue 0 and their own low 32 bits. - In macb_suspend(): if we use the tie off descriptor for suspend, do the write once for all queues instead of once per queue. Fixes: fff8019a08b6 ("net: macb: Add 64 bit addressing support for GEM") Fixes: ae1f2a56d273 ("net: macb: Added support for many RX queues") Reviewed-by: Sean Anderson Acked-by: Nicolas Ferre Signed-off-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb.h | 4 --- drivers/net/ethernet/cadence/macb_main.c | 57 ++++++++++++++--------------= ---- 2 files changed, 24 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cad= ence/macb.h index c9a5c8beb2fa8166195d1d83f187d2d0c62668a8..a7e845fee4b3a2e3d14abb49abd= baf3e8e6ea02b 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -213,10 +213,8 @@ =20 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) -#define GEM_TBQPH(hw_q) (0x04C8) #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) -#define GEM_RBQPH(hw_q) (0x04D4) #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) @@ -1214,10 +1212,8 @@ struct macb_queue { unsigned int IDR; unsigned int IMR; unsigned int TBQP; - unsigned int TBQPH; unsigned int RBQS; unsigned int RBQP; - unsigned int RBQPH; =20 /* Lock to protect tx_head and tx_tail */ spinlock_t tx_ptr_lock; diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index c769b7dbd3baf5cafe64008e18dff939623528d4..3e634049dadf14d371eac68448f= 80b111f228dfd 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -495,19 +495,19 @@ static void macb_init_buffers(struct macb *bp) struct macb_queue *queue; unsigned int q; =20 +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + /* Single register for all queues' high 32 bits. */ + if (bp->hw_dma_cap & HW_DMA_CAP_64B) { + macb_writel(bp, RBQPH, + upper_32_bits(bp->queues[0].rx_ring_dma)); + macb_writel(bp, TBQPH, + upper_32_bits(bp->queues[0].tx_ring_dma)); + } +#endif + for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - if (bp->hw_dma_cap & HW_DMA_CAP_64B) - queue_writel(queue, RBQPH, - upper_32_bits(queue->rx_ring_dma)); -#endif queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - if (bp->hw_dma_cap & HW_DMA_CAP_64B) - queue_writel(queue, TBQPH, - upper_32_bits(queue->tx_ring_dma)); -#endif } } =20 @@ -1166,10 +1166,6 @@ static void macb_tx_error_task(struct work_struct *w= ork) =20 /* Reinitialize the TX desc queue */ queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - if (bp->hw_dma_cap & HW_DMA_CAP_64B) - queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); -#endif /* Make TX ring reflect state of hardware */ queue->tx_head =3D 0; queue->tx_tail =3D 0; @@ -2546,6 +2542,7 @@ static int macb_alloc_consistent(struct macb *bp) { struct macb_queue *queue; unsigned int q; + u32 upper; int size; =20 for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { @@ -2553,7 +2550,9 @@ static int macb_alloc_consistent(struct macb *bp) queue->tx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, &queue->tx_ring_dma, GFP_KERNEL); - if (!queue->tx_ring) + upper =3D upper_32_bits(queue->tx_ring_dma); + if (!queue->tx_ring || + upper !=3D upper_32_bits(bp->queues[0].tx_ring_dma)) goto out_err; netdev_dbg(bp->dev, "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", @@ -2567,8 +2566,11 @@ static int macb_alloc_consistent(struct macb *bp) =20 size =3D RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; queue->rx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, - &queue->rx_ring_dma, GFP_KERNEL); - if (!queue->rx_ring) + &queue->rx_ring_dma, + GFP_KERNEL); + upper =3D upper_32_bits(queue->rx_ring_dma); + if (!queue->rx_ring || + upper !=3D upper_32_bits(bp->queues[0].rx_ring_dma)) goto out_err; netdev_dbg(bp->dev, "Allocated RX ring of %d bytes at %08lx (mapped %p)\n", @@ -4309,12 +4311,6 @@ static int macb_init(struct platform_device *pdev) queue->TBQP =3D GEM_TBQP(hw_q - 1); queue->RBQP =3D GEM_RBQP(hw_q - 1); queue->RBQS =3D GEM_RBQS(hw_q - 1); -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - if (bp->hw_dma_cap & HW_DMA_CAP_64B) { - queue->TBQPH =3D GEM_TBQPH(hw_q - 1); - queue->RBQPH =3D GEM_RBQPH(hw_q - 1); - } -#endif } else { /* queue0 uses legacy registers */ queue->ISR =3D MACB_ISR; @@ -4323,12 +4319,6 @@ static int macb_init(struct platform_device *pdev) queue->IMR =3D MACB_IMR; queue->TBQP =3D MACB_TBQP; queue->RBQP =3D MACB_RBQP; -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - if (bp->hw_dma_cap & HW_DMA_CAP_64B) { - queue->TBQPH =3D MACB_TBQPH; - queue->RBQPH =3D MACB_RBQPH; - } -#endif } =20 /* get irq: here we use the linux queue index, not the hardware @@ -5452,6 +5442,11 @@ static int __maybe_unused macb_suspend(struct device= *dev) */ tmp =3D macb_readl(bp, NCR); macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE))); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) + macb_writel(bp, RBQPH, + upper_32_bits(bp->rx_ring_tieoff_dma)); +#endif for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { /* Disable RX queues */ @@ -5461,10 +5456,6 @@ static int __maybe_unused macb_suspend(struct device= *dev) /* Tie off RX queues */ queue_writel(queue, RBQP, lower_32_bits(bp->rx_ring_tieoff_dma)); -#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT - queue_writel(queue, RBQPH, - upper_32_bits(bp->rx_ring_tieoff_dma)); -#endif } /* Disable all interrupts */ queue_writel(queue, IDR, -1); --=20 2.51.0 From nobody Wed Sep 10 23:21:40 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EE4A3375C2; Wed, 10 Sep 2025 16:16:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521002; cv=none; b=ZXD5sGqfBJGmG+JLmlJ+9fU/dzr5aYP+RrOA7C7B75RN0GwQUmJPAbItp3gUPd0Fpe6qfkL6NVtCrPAvqLjLbedV5b4tfkhsSjzB1bERz2Zvo21hSFFQrhcFeNfZHtjfbvbR5KvweaS1f09L6Wv0o0O5apvSXrwXrNnkQVyDN7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757521002; c=relaxed/simple; bh=BeobAv07xjOjICoXgtgNMpxQ/3t9JQQYycP5qPziRLc=; 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Wed, 10 Sep 2025 16:16:38 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id AB15D606D4; Wed, 10 Sep 2025 16:16:38 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A8BC0102F28A8; Wed, 10 Sep 2025 18:16:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757520997; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=brKOdnCK4c79eJgxsJqiOYDIVJbIJn3tEsmqO4UvEPQ=; b=RZN5P6ceUy23JZd0SwqAYEZJe9ol0o1dLImJ2kAFd3unpcUX6rdZrMgJ5ABPLxXcc9Fqar lYMewixIcRO8NHXv3UrdBwM1BTpoMc/BGD/rC0wozyepfzZb5Xbz2xVXNSmS5Yz5EBZFnd L7aYK+MtbQlxc5LdpsEhhcXzXv+YW1NlLlG6dS0As6Aj3JNPRLNvoW0RDAeGWeCs6cIR8H ZQ1lgANiZI7NoiK55xbaMHg1XX4AbnmGwnGp7zLw/pdq4LLO81G7srU0+uGcipnpDEDprS dmFfbQEoHbe6Ua4bG4z6WWqvLBm1s8aszAqtJ6sPcGiLLIHlMAAHhbP2nQNw9A== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 10 Sep 2025 18:15:32 +0200 Subject: [PATCH net v5 3/5] net: macb: move ring size computation to functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-macb-fixes-v5-3-f413a3601ce4@bootlin.com> References: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> In-Reply-To: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Geert Uytterhoeven , Harini Katakam , Richard Cochran , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 The tx/rx ring size calculation is somewhat complex and partially hidden behind a macro. Move that out of the {RX,TX}_RING_BYTES() macros and macb_{alloc,free}_consistent() functions into neat separate functions. In macb_free_consistent(), we drop the size variable and directly call the size helpers in the arguments list. In macb_alloc_consistent(), we keep the size variable that is used by netdev_dbg() calls. Acked-by: Nicolas Ferre Signed-off-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb_main.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index 3e634049dadf14d371eac68448f80b111f228dfd..73840808ea801b35a64a296dedc= 3a91e6e1f9f51 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -51,14 +51,10 @@ struct sifive_fu540_macb_mgmt { #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ #define MIN_RX_RING_SIZE 64 #define MAX_RX_RING_SIZE 8192 -#define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ - * (bp)->rx_ring_size) =20 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ #define MIN_TX_RING_SIZE 64 #define MAX_TX_RING_SIZE 4096 -#define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ - * (bp)->tx_ring_size) =20 /* level of occupied TX descriptors under which we wake up TX process */ #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) @@ -2470,11 +2466,20 @@ static void macb_free_rx_buffers(struct macb *bp) } } =20 +static unsigned int macb_tx_ring_size_per_queue(struct macb *bp) +{ + return macb_dma_desc_get_size(bp) * bp->tx_ring_size + bp->tx_bd_rd_prefe= tch; +} + +static unsigned int macb_rx_ring_size_per_queue(struct macb *bp) +{ + return macb_dma_desc_get_size(bp) * bp->rx_ring_size + bp->rx_bd_rd_prefe= tch; +} + static void macb_free_consistent(struct macb *bp) { struct macb_queue *queue; unsigned int q; - int size; =20 if (bp->rx_ring_tieoff) { dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), @@ -2488,14 +2493,14 @@ static void macb_free_consistent(struct macb *bp) kfree(queue->tx_skb); queue->tx_skb =3D NULL; if (queue->tx_ring) { - size =3D TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; - dma_free_coherent(&bp->pdev->dev, size, + dma_free_coherent(&bp->pdev->dev, + macb_tx_ring_size_per_queue(bp), queue->tx_ring, queue->tx_ring_dma); queue->tx_ring =3D NULL; } if (queue->rx_ring) { - size =3D RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; - dma_free_coherent(&bp->pdev->dev, size, + dma_free_coherent(&bp->pdev->dev, + macb_rx_ring_size_per_queue(bp), queue->rx_ring, queue->rx_ring_dma); queue->rx_ring =3D NULL; } @@ -2546,7 +2551,7 @@ static int macb_alloc_consistent(struct macb *bp) int size; =20 for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { - size =3D TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; + size =3D macb_tx_ring_size_per_queue(bp); queue->tx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, &queue->tx_ring_dma, GFP_KERNEL); @@ -2564,7 +2569,7 @@ static int macb_alloc_consistent(struct macb *bp) if (!queue->tx_skb) goto out_err; =20 - size =3D RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; + size =3D macb_rx_ring_size_per_queue(bp); queue->rx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, &queue->rx_ring_dma, GFP_KERNEL); --=20 2.51.0 From nobody Wed Sep 10 23:21:40 2025 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 299273376A3; Wed, 10 Sep 2025 16:16:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Sbsa6cNf" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id A7166C6B38C; Wed, 10 Sep 2025 16:16:25 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 766CE606D4; Wed, 10 Sep 2025 16:16:41 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 97FA9102F28F3; Wed, 10 Sep 2025 18:16:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1757520999; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=oMWyc4KCjaYuFjPAmTfCSPaCrCpIfWNEPyjtZueqdro=; b=Sbsa6cNffE58RlgGBZ0jIEwF5lbWbkw5ZPpa5bkln+ZahGyHnHYmef4YVlL3YROlaVxvr1 iOVZVS0fRolkeAogoTlRjXTlR1aOwOm9EDkmRS1zkv0AnPF78DSoDYyGmYZPYCKr4k8fpm Y//5nCYhS+dj0b4TDrFHpBAMzDPyjMJaJq+IhVO0NsldJINuKCLGStMRsDDyxqAxtkzKrJ FaULjBpFkqG8lAhQ6TP2JnW0Xo09gpua6TFgTggSsYLc/WStyknvgD4CaWOuz6KuvoI2Ur Dsm2K88YHDuCf8xunbb350MIUM9A5U4zBRJBKf1TIiH3MBHjqWO5YFBnDYAIBw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 10 Sep 2025 18:15:33 +0200 Subject: [PATCH net v5 4/5] net: macb: single dma_alloc_coherent() for DMA descriptors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-macb-fixes-v5-4-f413a3601ce4@bootlin.com> References: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> In-Reply-To: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Geert Uytterhoeven , Harini Katakam , Richard Cochran , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Sean Anderson X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 Move from 2*NUM_QUEUES dma_alloc_coherent() for DMA descriptor rings to 2 calls overall. Issue is with how all queues share the same register for configuring the upper 32-bits of Tx/Rx descriptor rings. Taking Tx, notice how TBQPH does *not* depend on the queue index: #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) #define GEM_TBQPH(hw_q) (0x04C8) queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT if (bp->hw_dma_cap & HW_DMA_CAP_64B) queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); #endif To maximise our chances of getting valid DMA addresses, we do a single dma_alloc_coherent() across queues. This improves the odds because alloc_pages() guarantees natural alignment. Other codepaths (IOMMU or dev/arch dma_map_ops) don't give high enough guarantees (even page-aligned isn't enough). Two consideration: - dma_alloc_coherent() gives us page alignment. Here we remove this constraint meaning each queue's ring won't be page-aligned anymore. - This can save some tiny amounts of memory. Fewer allocations means (1) less overhead (constant cost per alloc) and (2) less wasted bytes due to alignment constraints. Example for (2): 4 queues, default ring size (512), 64-bit DMA descriptors, 16K pages: - Before: 8 allocs of 8K, each rounded to 16K =3D> 64K wasted. - After: 2 allocs of 32K =3D> 0K wasted. Fixes: 02c958dd3446 ("net/macb: add TX multiqueue support for gem") Reviewed-by: Sean Anderson Acked-by: Nicolas Ferre Tested-by: Nicolas Ferre # on sam9x75 Signed-off-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb_main.c | 80 ++++++++++++++++------------= ---- 1 file changed, 41 insertions(+), 39 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index 73840808ea801b35a64a296dedc3a91e6e1f9f51..fc082a7a5a313be3d58a008533c= 3815cb1b1639a 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -2478,32 +2478,30 @@ static unsigned int macb_rx_ring_size_per_queue(str= uct macb *bp) =20 static void macb_free_consistent(struct macb *bp) { + struct device *dev =3D &bp->pdev->dev; struct macb_queue *queue; unsigned int q; + size_t size; =20 if (bp->rx_ring_tieoff) { - dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), + dma_free_coherent(dev, macb_dma_desc_get_size(bp), bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma); bp->rx_ring_tieoff =3D NULL; } =20 bp->macbgem_ops.mog_free_rx_buffers(bp); =20 + size =3D bp->num_queues * macb_tx_ring_size_per_queue(bp); + dma_free_coherent(dev, size, bp->queues[0].tx_ring, bp->queues[0].tx_ring= _dma); + + size =3D bp->num_queues * macb_rx_ring_size_per_queue(bp); + dma_free_coherent(dev, size, bp->queues[0].rx_ring, bp->queues[0].rx_ring= _dma); + for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { kfree(queue->tx_skb); queue->tx_skb =3D NULL; - if (queue->tx_ring) { - dma_free_coherent(&bp->pdev->dev, - macb_tx_ring_size_per_queue(bp), - queue->tx_ring, queue->tx_ring_dma); - queue->tx_ring =3D NULL; - } - if (queue->rx_ring) { - dma_free_coherent(&bp->pdev->dev, - macb_rx_ring_size_per_queue(bp), - queue->rx_ring, queue->rx_ring_dma); - queue->rx_ring =3D NULL; - } + queue->tx_ring =3D NULL; + queue->rx_ring =3D NULL; } } =20 @@ -2545,41 +2543,45 @@ static int macb_alloc_rx_buffers(struct macb *bp) =20 static int macb_alloc_consistent(struct macb *bp) { + struct device *dev =3D &bp->pdev->dev; + dma_addr_t tx_dma, rx_dma; struct macb_queue *queue; unsigned int q; - u32 upper; - int size; + void *tx, *rx; + size_t size; + + /* + * Upper 32-bits of Tx/Rx DMA descriptor for each queues much match! + * We cannot enforce this guarantee, the best we can do is do a single + * allocation and hope it will land into alloc_pages() that guarantees + * natural alignment of physical addresses. + */ + + size =3D bp->num_queues * macb_tx_ring_size_per_queue(bp); + tx =3D dma_alloc_coherent(dev, size, &tx_dma, GFP_KERNEL); + if (!tx || upper_32_bits(tx_dma) !=3D upper_32_bits(tx_dma + size - 1)) + goto out_err; + netdev_dbg(bp->dev, "Allocated %zu bytes for %u TX rings at %08lx (mapped= %p)\n", + size, bp->num_queues, (unsigned long)tx_dma, tx); + + size =3D bp->num_queues * macb_rx_ring_size_per_queue(bp); + rx =3D dma_alloc_coherent(dev, size, &rx_dma, GFP_KERNEL); + if (!rx || upper_32_bits(rx_dma) !=3D upper_32_bits(rx_dma + size - 1)) + goto out_err; + netdev_dbg(bp->dev, "Allocated %zu bytes for %u RX rings at %08lx (mapped= %p)\n", + size, bp->num_queues, (unsigned long)rx_dma, rx); =20 for (q =3D 0, queue =3D bp->queues; q < bp->num_queues; ++q, ++queue) { - size =3D macb_tx_ring_size_per_queue(bp); - queue->tx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, - &queue->tx_ring_dma, - GFP_KERNEL); - upper =3D upper_32_bits(queue->tx_ring_dma); - if (!queue->tx_ring || - upper !=3D upper_32_bits(bp->queues[0].tx_ring_dma)) - goto out_err; - netdev_dbg(bp->dev, - "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n", - q, size, (unsigned long)queue->tx_ring_dma, - queue->tx_ring); + queue->tx_ring =3D tx + macb_tx_ring_size_per_queue(bp) * q; + queue->tx_ring_dma =3D tx_dma + macb_tx_ring_size_per_queue(bp) * q; + + queue->rx_ring =3D rx + macb_rx_ring_size_per_queue(bp) * q; + queue->rx_ring_dma =3D rx_dma + macb_rx_ring_size_per_queue(bp) * q; =20 size =3D bp->tx_ring_size * sizeof(struct macb_tx_skb); queue->tx_skb =3D kmalloc(size, GFP_KERNEL); if (!queue->tx_skb) goto out_err; - - size =3D macb_rx_ring_size_per_queue(bp); - queue->rx_ring =3D dma_alloc_coherent(&bp->pdev->dev, size, - &queue->rx_ring_dma, - GFP_KERNEL); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-macb-fixes-v5-5-f413a3601ce4@bootlin.com> References: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> In-Reply-To: <20250910-macb-fixes-v5-0-f413a3601ce4@bootlin.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , Claudiu Beznea , Geert Uytterhoeven , Harini Katakam , Richard Cochran , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Sean Anderson X-Mailer: b4 0.14.2 X-Last-TLS-Session-Version: TLSv1.3 bp->dev->dev_addr is of type `unsigned char *`. Casting it to a u32 pointer and dereferencing implies dealing manually with endianness, which is error-prone. Replace by calls to get_unaligned_le32|le16() helpers. This was found using sparse: =E2=9F=A9 make C=3D2 drivers/net/ethernet/cadence/macb_main.o warning: incorrect type in assignment (different base types) expected unsigned int [usertype] bottom got restricted __le32 [usertype] warning: incorrect type in assignment (different base types) expected unsigned short [usertype] top got restricted __le16 [usertype] ... Reviewed-by: Sean Anderson Signed-off-by: Th=C3=A9o Lebrun --- drivers/net/ethernet/cadence/macb_main.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index fc082a7a5a313be3d58a008533c3815cb1b1639a..c16d60048185b4cb473ddfcf463= 3fa2f6dea20cc 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -271,12 +271,10 @@ static bool hw_is_gem(void __iomem *addr, bool native= _io) =20 static void macb_set_hwaddr(struct macb *bp) { - u32 bottom; - u16 top; + u32 bottom =3D get_unaligned_le32(bp->dev->dev_addr); + u16 top =3D get_unaligned_le16(bp->dev->dev_addr + 4); =20 - bottom =3D cpu_to_le32(*((u32 *)bp->dev->dev_addr)); macb_or_gem_writel(bp, SA1B, bottom); - top =3D cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); macb_or_gem_writel(bp, SA1T, top); =20 if (gem_has_ptp(bp)) { --=20 2.51.0