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Wed, 10 Sep 2025 00:13:00 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:41 +0200 Subject: [PATCH v2 05/15] gpio: ath79: use the generic GPIO chip lock for IRQ handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-5-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski This driver uses its own raw spinlock in interrupt routines while the generic GPIO chip callbacks use a separate one. This is, of course, racy so use the fact that the lock in generic GPIO chip is also a raw spinlock and convert the interrupt handling functions in this module to using the provided generic GPIO chip locking API. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-ath79.c | 51 ++++++++++++++++++-------------------------= ---- 1 file changed, 19 insertions(+), 32 deletions(-) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index 8879f23f1871ed323513082f4d2ebb2c40544cde..2ad9f6ac66362fba8cdab152a2b= 2c782dddf427c 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -31,7 +31,6 @@ struct ath79_gpio_ctrl { struct gpio_generic_chip chip; void __iomem *base; - raw_spinlock_t lock; unsigned long both_edges; }; =20 @@ -72,23 +71,22 @@ static void ath79_gpio_irq_unmask(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); - raw_spin_lock_irqsave(&ctrl->lock, flags); + + guard(gpio_generic_lock_irqsave)(&ctrl->chip); + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static void ath79_gpio_irq_mask(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); - ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); + gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); } =20 @@ -96,24 +94,20 @@ static void ath79_gpio_irq_enable(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static void ath79_gpio_irq_disable(struct irq_data *data) { struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); - raw_spin_unlock_irqrestore(&ctrl->lock, flags); } =20 static int ath79_gpio_irq_set_type(struct irq_data *data, @@ -122,7 +116,6 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, struct ath79_gpio_ctrl *ctrl =3D irq_data_to_ath79_gpio(data); u32 mask =3D BIT(irqd_to_hwirq(data)); u32 type =3D 0, polarity =3D 0; - unsigned long flags; bool disabled; =20 switch (flow_type) { @@ -144,7 +137,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, return -EINVAL; } =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + guard(gpio_generic_lock_irqsave)(&ctrl->chip); =20 if (flow_type =3D=3D IRQ_TYPE_EDGE_BOTH) { ctrl->both_edges |=3D mask; @@ -169,8 +162,6 @@ static int ath79_gpio_irq_set_type(struct irq_data *dat= a, ath79_gpio_update_bits( ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); =20 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - return 0; } =20 @@ -192,26 +183,24 @@ static void ath79_gpio_irq_handler(struct irq_desc *d= esc) struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct ath79_gpio_ctrl *ctrl =3D container_of(gen_gc, struct ath79_gpio_ctrl, chip); - unsigned long flags, pending; + unsigned long pending; u32 both_edges, state; int irq; =20 chained_irq_enter(irqchip, desc); =20 - raw_spin_lock_irqsave(&ctrl->lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &ctrl->chip) { + pending =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); =20 - pending =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); - - /* Update the polarity of the both edges irqs */ - both_edges =3D ctrl->both_edges & pending; - if (both_edges) { - state =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); - ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, - both_edges, ~state); + /* Update the polarity of the both edges irqs */ + both_edges =3D ctrl->both_edges & pending; + if (both_edges) { + state =3D ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); + ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, + both_edges, ~state); + } } =20 - raw_spin_unlock_irqrestore(&ctrl->lock, flags); - for_each_set_bit(irq, &pending, gc->ngpio) generic_handle_domain_irq(gc->irq.domain, irq); =20 @@ -256,8 +245,6 @@ static int ath79_gpio_probe(struct platform_device *pde= v) if (IS_ERR(ctrl->base)) return PTR_ERR(ctrl->base); =20 - raw_spin_lock_init(&ctrl->lock); - config =3D (struct gpio_generic_chip_config) { .dev =3D dev, .sz =3D 4, --=20 2.48.1