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Wed, 10 Sep 2025 00:12:58 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:40 +0200 Subject: [PATCH v2 04/15] gpio: ath79: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-4-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-ath79.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c index de4cc12e5e0399abcef61a89c8c91a1b203d20fb..8879f23f1871ed323513082f4d2= ebb2c40544cde 100644 --- a/drivers/gpio/gpio-ath79.c +++ b/drivers/gpio/gpio-ath79.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -28,7 +29,7 @@ #define AR71XX_GPIO_REG_INT_MASK 0x24 =20 struct ath79_gpio_ctrl { - struct gpio_chip gc; + struct gpio_generic_chip chip; void __iomem *base; raw_spinlock_t lock; unsigned long both_edges; @@ -37,8 +38,9 @@ struct ath79_gpio_ctrl { static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *dat= a) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); =20 - return container_of(gc, struct ath79_gpio_ctrl, gc); + return container_of(gen_gc, struct ath79_gpio_ctrl, chip); } =20 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) @@ -72,7 +74,7 @@ static void ath79_gpio_irq_unmask(struct irq_data *data) u32 mask =3D BIT(irqd_to_hwirq(data)); unsigned long flags; =20 - gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data)); + gpiochip_enable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); raw_spin_unlock_irqrestore(&ctrl->lock, flags); @@ -87,7 +89,7 @@ static void ath79_gpio_irq_mask(struct irq_data *data) raw_spin_lock_irqsave(&ctrl->lock, flags); ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); raw_spin_unlock_irqrestore(&ctrl->lock, flags); - gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data)); + gpiochip_disable_irq(&ctrl->chip.gc, irqd_to_hwirq(data)); } =20 static void ath79_gpio_irq_enable(struct irq_data *data) @@ -187,8 +189,9 @@ static void ath79_gpio_irq_handler(struct irq_desc *des= c) { struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct ath79_gpio_ctrl *ctrl =3D - container_of(gc, struct ath79_gpio_ctrl, gc); + container_of(gen_gc, struct ath79_gpio_ctrl, chip); unsigned long flags, pending; u32 both_edges, state; int irq; @@ -224,6 +227,7 @@ MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); =20 static int ath79_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct ath79_gpio_ctrl *ctrl; struct gpio_irq_chip *girq; @@ -253,21 +257,26 @@ static int ath79_gpio_probe(struct platform_device *p= dev) return PTR_ERR(ctrl->base); =20 raw_spin_lock_init(&ctrl->lock); - err =3D bgpio_init(&ctrl->gc, dev, 4, - ctrl->base + AR71XX_GPIO_REG_IN, - ctrl->base + AR71XX_GPIO_REG_SET, - ctrl->base + AR71XX_GPIO_REG_CLEAR, - oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, - oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, - 0); + + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D ctrl->base + AR71XX_GPIO_REG_IN, + .set =3D ctrl->base + AR71XX_GPIO_REG_SET, + .clr =3D ctrl->base + AR71XX_GPIO_REG_CLEAR, + .dirout =3D oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, + .dirin =3D oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, + }; + + err =3D gpio_generic_chip_init(&ctrl->chip, &config); if (err) { - dev_err(dev, "bgpio_init failed\n"); + dev_err(dev, "failed to initialize generic GPIO chip\n"); return err; } =20 /* Optional interrupt setup */ if (device_property_read_bool(dev, "interrupt-controller")) { - girq =3D &ctrl->gc.irq; + girq =3D &ctrl->chip.gc.irq; gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip); girq->parent_handler =3D ath79_gpio_irq_handler; girq->num_parents =3D 1; @@ -280,7 +289,7 @@ static int ath79_gpio_probe(struct platform_device *pde= v) girq->handler =3D handle_simple_irq; } =20 - return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); + return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); } =20 static struct platform_driver ath79_gpio_driver =3D { --=20 2.48.1