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Wed, 10 Sep 2025 00:12:55 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:39 +0200 Subject: [PATCH v2 03/15] gpio: hlwd: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-3-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-hlwd.c | 105 ++++++++++++++++++++++++-------------------= ---- 1 file changed, 54 insertions(+), 51 deletions(-) diff --git a/drivers/gpio/gpio-hlwd.c b/drivers/gpio/gpio-hlwd.c index 0580f6712bea9a4d510bd332645982adbc5c6a32..a395f87436ac4df386ce2ee345f= c0a7cc34c843d 100644 --- a/drivers/gpio/gpio-hlwd.c +++ b/drivers/gpio/gpio-hlwd.c @@ -6,6 +6,7 @@ // Nintendo Wii (Hollywood) GPIO driver =20 #include +#include #include #include #include @@ -48,7 +49,7 @@ #define HW_GPIO_OWNER 0x3c =20 struct hlwd_gpio { - struct gpio_chip gpioc; + struct gpio_generic_chip gpioc; struct device *dev; void __iomem *regs; int irq; @@ -61,45 +62,44 @@ static void hlwd_gpio_irqhandler(struct irq_desc *desc) struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_desc_get_handler_data(desc)); struct irq_chip *chip =3D irq_desc_get_chip(desc); - unsigned long flags; unsigned long pending; int hwirq; u32 emulated_pending; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); - pending =3D ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); - pending &=3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { + pending =3D ioread32be(hlwd->regs + HW_GPIOB_INTFLAG); + pending &=3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); =20 - /* Treat interrupts due to edge trigger emulation separately */ - emulated_pending =3D hlwd->edge_emulation & pending; - pending &=3D ~emulated_pending; - if (emulated_pending) { - u32 level, rising, falling; + /* Treat interrupts due to edge trigger emulation separately */ + emulated_pending =3D hlwd->edge_emulation & pending; + pending &=3D ~emulated_pending; + if (emulated_pending) { + u32 level, rising, falling; =20 - level =3D ioread32be(hlwd->regs + HW_GPIOB_INTLVL); - rising =3D level & emulated_pending; - falling =3D ~level & emulated_pending; + level =3D ioread32be(hlwd->regs + HW_GPIOB_INTLVL); + rising =3D level & emulated_pending; + falling =3D ~level & emulated_pending; =20 - /* Invert the levels */ - iowrite32be(level ^ emulated_pending, - hlwd->regs + HW_GPIOB_INTLVL); + /* Invert the levels */ + iowrite32be(level ^ emulated_pending, + hlwd->regs + HW_GPIOB_INTLVL); =20 - /* Ack all emulated-edge interrupts */ - iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); + /* Ack all emulated-edge interrupts */ + iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG); =20 - /* Signal interrupts only on the correct edge */ - rising &=3D hlwd->rising_edge; - falling &=3D hlwd->falling_edge; + /* Signal interrupts only on the correct edge */ + rising &=3D hlwd->rising_edge; + falling &=3D hlwd->falling_edge; =20 - /* Mark emulated interrupts as pending */ - pending |=3D rising | falling; + /* Mark emulated interrupts as pending */ + pending |=3D rising | falling; + } } - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); =20 chained_irq_enter(chip, desc); =20 for_each_set_bit(hwirq, &pending, 32) - generic_handle_domain_irq(hlwd->gpioc.irq.domain, hwirq); + generic_handle_domain_irq(hlwd->gpioc.gc.irq.domain, hwirq); =20 chained_irq_exit(chip, desc); } @@ -116,30 +116,29 @@ static void hlwd_gpio_irq_mask(struct irq_data *data) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 mask; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); - mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); - mask &=3D ~BIT(data->hwirq); - iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); - gpiochip_disable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); + scoped_guard(gpio_generic_lock_irqsave, &hlwd->gpioc) { + mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); + mask &=3D ~BIT(data->hwirq); + iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); + } + gpiochip_disable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); } =20 static void hlwd_gpio_irq_unmask(struct irq_data *data) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 mask; =20 - gpiochip_enable_irq(&hlwd->gpioc, irqd_to_hwirq(data)); - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); + gpiochip_enable_irq(&hlwd->gpioc.gc, irqd_to_hwirq(data)); + + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); + mask =3D ioread32be(hlwd->regs + HW_GPIOB_INTMASK); mask |=3D BIT(data->hwirq); iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK); - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); } =20 static void hlwd_gpio_irq_enable(struct irq_data *data) @@ -173,10 +172,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *dat= a, unsigned int flow_type) { struct hlwd_gpio *hlwd =3D gpiochip_get_data(irq_data_get_irq_chip_data(data)); - unsigned long flags; u32 level; =20 - raw_spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&hlwd->gpioc); =20 hlwd->edge_emulation &=3D ~BIT(data->hwirq); =20 @@ -197,11 +195,9 @@ static int hlwd_gpio_irq_set_type(struct irq_data *dat= a, unsigned int flow_type) hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type); break; default: - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); return -EINVAL; } =20 - raw_spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags); return 0; } =20 @@ -225,6 +221,7 @@ static const struct irq_chip hlwd_gpio_irq_chip =3D { =20 static int hlwd_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct hlwd_gpio *hlwd; u32 ngpios; int res; @@ -244,25 +241,31 @@ static int hlwd_gpio_probe(struct platform_device *pd= ev) * systems where the AHBPROT memory firewall hasn't been configured to * permit PPC access to HW_GPIO_*. * - * Note that this has to happen before bgpio_init reads the - * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong - * values. + * Note that this has to happen before gpio_generic_chip_init() reads + * the HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the + * wrong values. */ iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER); =20 - res =3D bgpio_init(&hlwd->gpioc, &pdev->dev, 4, - hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT, - NULL, hlwd->regs + HW_GPIOB_DIR, NULL, - BGPIOF_BIG_ENDIAN_BYTE_ORDER); + config =3D (struct gpio_generic_chip_config) { + .dev =3D &pdev->dev, + .sz =3D 4, + .dat =3D hlwd->regs + HW_GPIOB_IN, + .set =3D hlwd->regs + HW_GPIOB_OUT, + .dirout =3D hlwd->regs + HW_GPIOB_DIR, + .flags =3D BGPIOF_BIG_ENDIAN_BYTE_ORDER, + }; + + res =3D gpio_generic_chip_init(&hlwd->gpioc, &config); if (res < 0) { - dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res); + dev_warn(&pdev->dev, "failed to initialize generic GPIO chip: %d\n", res= ); return res; } =20 res =3D of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios); if (res) ngpios =3D 32; - hlwd->gpioc.ngpio =3D ngpios; + hlwd->gpioc.gc.ngpio =3D ngpios; =20 /* Mask and ack all interrupts */ iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK); @@ -282,7 +285,7 @@ static int hlwd_gpio_probe(struct platform_device *pdev) return hlwd->irq; } =20 - girq =3D &hlwd->gpioc.irq; + girq =3D &hlwd->gpioc.gc.irq; gpio_irq_chip_set_chip(girq, &hlwd_gpio_irq_chip); girq->parent_handler =3D hlwd_gpio_irqhandler; girq->num_parents =3D 1; @@ -296,7 +299,7 @@ static int hlwd_gpio_probe(struct platform_device *pdev) girq->handler =3D handle_level_irq; } =20 - return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd); + return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc.gc, hlwd); } =20 static const struct of_device_id hlwd_gpio_match[] =3D { --=20 2.48.1