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Wed, 10 Sep 2025 00:13:14 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 10 Sep 2025 09:12:47 +0200 Subject: [PATCH v2 11/15] gpio: sifive: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250910-gpio-mmio-gpio-conv-part4-v2-11-f3d1a4c57124@linaro.org> References: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> In-Reply-To: <20250910-gpio-mmio-gpio-conv-part4-v2-0-f3d1a4c57124@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Keguang Zhang , Alban Bedel , Doug Berger , Florian Fainelli , Broadcom internal kernel review list , Matthias Brugger , AngeloGioacchino Del Regno , Paul Walmsley , Samuel Holland , Yixun Lan , Andy Shevchenko Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski Reviewed-by: Samuel Holland --- drivers/gpio/gpio-sifive.c | 73 ++++++++++++++++++++++++------------------= ---- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index 98ef975c44d9a6c9238605cfd1d5820fd70a66ca..2ced87ffd3bbf219c11857391eb= 4ea808adc0527 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -32,7 +33,7 @@ =20 struct sifive_gpio { void __iomem *base; - struct gpio_chip gc; + struct gpio_generic_chip gen_gc; struct regmap *regs; unsigned long irq_state; unsigned int trigger[SIFIVE_GPIO_MAX]; @@ -41,10 +42,10 @@ struct sifive_gpio { =20 static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offs= et) { - unsigned long flags; unsigned int trigger; =20 - raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(&chip->gen_gc); + trigger =3D (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0); @@ -54,7 +55,6 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, = unsigned int offset) (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0); regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0); - raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); } =20 static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigg= er) @@ -72,13 +72,12 @@ static int sifive_gpio_irq_set_type(struct irq_data *d,= unsigned int trigger) } =20 static void sifive_gpio_irq_enable(struct irq_data *d) -{ + { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct sifive_gpio *chip =3D gpiochip_get_data(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); int offset =3D hwirq % SIFIVE_GPIO_MAX; u32 bit =3D BIT(offset); - unsigned long flags; =20 gpiochip_enable_irq(gc, hwirq); irq_chip_enable_parent(d); @@ -86,13 +85,13 @@ static void sifive_gpio_irq_enable(struct irq_data *d) /* Switch to input */ gc->direction_input(gc, offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - /* Clear any sticky pending interrupts */ - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { + /* Clear any sticky pending interrupts */ + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); + } =20 /* Enable interrupts */ assign_bit(offset, &chip->irq_state, 1); @@ -118,15 +117,14 @@ static void sifive_gpio_irq_eoi(struct irq_data *d) struct sifive_gpio *chip =3D gpiochip_get_data(gc); int offset =3D irqd_to_hwirq(d) % SIFIVE_GPIO_MAX; u32 bit =3D BIT(offset); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - /* Clear all pending interrupts */ - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) { + /* Clear all pending interrupts */ + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit); + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit); + } =20 irq_chip_eoi_parent(d); } @@ -179,6 +177,7 @@ static const struct regmap_config sifive_gpio_regmap_co= nfig =3D { =20 static int sifive_gpio_probe(struct platform_device *pdev) { + struct gpio_generic_chip_config config; struct device *dev =3D &pdev->dev; struct irq_domain *parent; struct gpio_irq_chip *girq; @@ -217,13 +216,17 @@ static int sifive_gpio_probe(struct platform_device *= pdev) */ parent =3D irq_get_irq_data(chip->irq_number[0])->domain; =20 - ret =3D bgpio_init(&chip->gc, dev, 4, - chip->base + SIFIVE_GPIO_INPUT_VAL, - chip->base + SIFIVE_GPIO_OUTPUT_VAL, - NULL, - chip->base + SIFIVE_GPIO_OUTPUT_EN, - chip->base + SIFIVE_GPIO_INPUT_EN, - BGPIOF_READ_OUTPUT_REG_SET); + config =3D (struct gpio_generic_chip_config) { + .dev =3D dev, + .sz =3D 4, + .dat =3D chip->base + SIFIVE_GPIO_INPUT_VAL, + .set =3D chip->base + SIFIVE_GPIO_OUTPUT_VAL, + .dirout =3D chip->base + SIFIVE_GPIO_OUTPUT_EN, + .dirin =3D chip->base + SIFIVE_GPIO_INPUT_EN, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + }; + + ret =3D gpio_generic_chip_init(&chip->gen_gc, &config); if (ret) { dev_err(dev, "unable to init generic GPIO\n"); return ret; @@ -236,12 +239,12 @@ static int sifive_gpio_probe(struct platform_device *= pdev) regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0); chip->irq_state =3D 0; =20 - chip->gc.base =3D -1; - chip->gc.ngpio =3D ngpio; - chip->gc.label =3D dev_name(dev); - chip->gc.parent =3D dev; - chip->gc.owner =3D THIS_MODULE; - girq =3D &chip->gc.irq; + chip->gen_gc.gc.base =3D -1; + chip->gen_gc.gc.ngpio =3D ngpio; + chip->gen_gc.gc.label =3D dev_name(dev); + chip->gen_gc.gc.parent =3D dev; + chip->gen_gc.gc.owner =3D THIS_MODULE; + girq =3D &chip->gen_gc.gc.irq; gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip); girq->fwnode =3D dev_fwnode(dev); girq->parent_domain =3D parent; @@ -249,7 +252,7 @@ static int sifive_gpio_probe(struct platform_device *pd= ev) girq->handler =3D handle_bad_irq; girq->default_type =3D IRQ_TYPE_NONE; =20 - return gpiochip_add_data(&chip->gc, chip); + return gpiochip_add_data(&chip->gen_gc.gc, chip); } =20 static const struct of_device_id sifive_gpio_match[] =3D { --=20 2.48.1